This document describes the design and implementation of an AHB2APB bridge to efficiently connect the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) in an AMBA-based system on chip (SoC) design. The AHB2APB bridge interfaces the two buses by buffering addresses and controlling the flow of data and control signals between the AHB and APB. Behavioral simulations were performed to verify the functionality of the bridge during single read/write, burst read/write, and back-to-back operations. The results indicate the bridge efficiently implements the AHB to APB protocol with low resource utilization on an Artix-7 FPGA board.