Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
This document summarizes a research paper that proposes a synthesizable checker for the AMBA AXI protocol. The AXI protocol is commonly used for on-chip communication in system-on-chip (SoC) designs. The proposed checker contains 44 rules to verify AXI protocol compliance and was implemented using Verilog. Simulation results showed the checker design requires 70.7K gate counts and has a critical path of 4.13 ns, allowing it to operate at 242 MHz. The checker is intended to improve SoC integration by verifying correct protocol usage and helping debug communication issues.
This document summarizes a research paper that proposes a synthesizable AMBA AXI protocol checker to verify communication properties in a system-on-chip (SoC) design. It contains 44 rules to check the AMBA AXI protocol and provides verification of the AXI master, slave, and default slave protocols. The protocol checker uses a rule-based methodology and model simulation to thoroughly verify chip-level behaviors and help debug issues, improving design quality and reducing verification time and costs.
Design and Analysis of Xilinx Verified AMBA Bridge for SoC Systemsidescitation
ARM introduced the Advanced Microcontroller Bus
Architecture (AMBA) 4.0 and its specifications define five
buses/interfaces: Advanced eXtensible Interface Bus (AXI),
Advanced High-performance Bus (AHB), Advanced System Bus
(ASB), Advanced Peripheral Bus (APB) and Advanced Trace
Bus (ATB). That means more and more existing Intellectual
Property (IP) must be able to communicate with AMBA4.0
bus. This paper presents an IP core design of APB Bridge, to
provide interface between AXI-Lite bus and APB bus operating
at different frequencies. The maximum operating frequency
of the module is 168.464MHz. Test cases are run to perform
multiple read and write operations. Synthesis and Simulation
is done using Xilinx ISE and Modelsim.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIPVLSICS Design
This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding algorithms for the three currently most important error-correcting codes: the low-density parity-check (LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER performances of the corresponding statistical decoding algorithms for the three codes and channels. In all cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual and relative performances of the algorithms. Thus there is no performance loss, and sometimes a significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system implementation. In addition, we have found that the processing complexity of the non-statistical algorithms is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for the LDPC codes over all of the channels.
IP forwarding architectures and Overlay ModelPradnya Saval
The document discusses different approaches to IP forwarding in routers, including:
1. Category 1 retains the same forwarding paradigm but improves performance by modifying internal architecture, like replacing bus backplanes with switch backplanes.
2. Category 2 simplifies lookup using short, fixed-length labels instead of long, variable-length IP prefixes, like using VCI/VPI in ATM networks.
3. The overlay model overlays an IP network onto an ATM network, essentially creating two network infrastructures. The peer model maintains a single network infrastructure using existing IP addresses to identify systems and set up ATM connections.
This document summarizes a research paper that proposes a synthesizable checker for the AMBA AXI protocol. The AXI protocol is commonly used for on-chip communication in system-on-chip (SoC) designs. The proposed checker contains 44 rules to verify AXI protocol compliance and was implemented using Verilog. Simulation results showed the checker design requires 70.7K gate counts and has a critical path of 4.13 ns, allowing it to operate at 242 MHz. The checker is intended to improve SoC integration by verifying correct protocol usage and helping debug communication issues.
This document summarizes a research paper that proposes a synthesizable AMBA AXI protocol checker to verify communication properties in a system-on-chip (SoC) design. It contains 44 rules to check the AMBA AXI protocol and provides verification of the AXI master, slave, and default slave protocols. The protocol checker uses a rule-based methodology and model simulation to thoroughly verify chip-level behaviors and help debug issues, improving design quality and reducing verification time and costs.
Design and Analysis of Xilinx Verified AMBA Bridge for SoC Systemsidescitation
ARM introduced the Advanced Microcontroller Bus
Architecture (AMBA) 4.0 and its specifications define five
buses/interfaces: Advanced eXtensible Interface Bus (AXI),
Advanced High-performance Bus (AHB), Advanced System Bus
(ASB), Advanced Peripheral Bus (APB) and Advanced Trace
Bus (ATB). That means more and more existing Intellectual
Property (IP) must be able to communicate with AMBA4.0
bus. This paper presents an IP core design of APB Bridge, to
provide interface between AXI-Lite bus and APB bus operating
at different frequencies. The maximum operating frequency
of the module is 168.464MHz. Test cases are run to perform
multiple read and write operations. Synthesis and Simulation
is done using Xilinx ISE and Modelsim.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIPVLSICS Design
This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding algorithms for the three currently most important error-correcting codes: the low-density parity-check (LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER performances of the corresponding statistical decoding algorithms for the three codes and channels. In all cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual and relative performances of the algorithms. Thus there is no performance loss, and sometimes a significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system implementation. In addition, we have found that the processing complexity of the non-statistical algorithms is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for the LDPC codes over all of the channels.
IP forwarding architectures and Overlay ModelPradnya Saval
The document discusses different approaches to IP forwarding in routers, including:
1. Category 1 retains the same forwarding paradigm but improves performance by modifying internal architecture, like replacing bus backplanes with switch backplanes.
2. Category 2 simplifies lookup using short, fixed-length labels instead of long, variable-length IP prefixes, like using VCI/VPI in ATM networks.
3. The overlay model overlays an IP network onto an ATM network, essentially creating two network infrastructures. The peer model maintains a single network infrastructure using existing IP addresses to identify systems and set up ATM connections.
This document summarizes an implementation of a data error corrector using VLSI techniques. It describes a convolutional encoder and Viterbi decoder with a constraint length of 9 and code rate of 1/2, realized using Verilog HDL. Convolutional codes are used for forward error correction in digital data transmission by adding redundant bits. The Viterbi algorithm performs maximum likelihood decoding by using a trellis structure to calculate path metrics and select the most probable transmitted sequence. The implemented Viterbi decoder contains branch metric, path metric, and survivor memory units to decode a received bit stream encoded with a convolutional code. It was simulated and synthesized using Xilinx 13.1i tools.
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
Master's Degree Thesis on High Order Modulation and Coding Shemes for Satellite Transmitters
Advisors
Prof.dr. Roberto Garello
Eng.dr. Domenico Giancristofaro
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document describes an implementation of an LDPC decoder for IEEE 802.11n wireless networks using Vivado High-Level Synthesis. It implemented the decoder as a C program using Vivado HLS directives to optimize parallelism and throughput. The implementation achieved throughputs of over 1 Gbps and error correction performance comparable to an RTL implementation but with higher productivity due to the higher level of abstraction of C compared to RTL.
Design and Implementation of HDLC Controller by Using Crc-16IJMER
This document summarizes a research paper that designed, simulated, and implemented an HDLC controller using VHDL on a Spartan 3 FPGA. The HDLC controller supports data transmission rates up to 155.52 Mbps and complies with ITU and X.25 standards. It allows synchronous, transparent data transmission over point-to-point and multipoint channels. The design was tested through simulation and synthesis, and implemented CRC-16, bit stuffing/removal and error detection. The goal was to efficiently utilize FPGA resources to run the programmed design at high speeds.
This document describes using MATLAB Simulink to program and communicate between two dsPIC30f microcontrollers over a Controller Area Network (CAN) protocol. It presents the development of a real-time digital system using Simulink, Real-Time Workshop and Embedded Coder to generate C code from Simulink models. The C code is then compiled and run on the dsPIC30f microcontrollers. Specifically, it communicates engine RPM values transmitted by one microcontroller over CAN to the other microcontroller, which decodes and displays the RPM on an LCD screen. The decoding algorithm is also described.
This document contains information about various VLSI and low power projects, including titles, codes, and brief descriptions. It lists 30 projects related to topics like area-efficient adders and multipliers, low power filter and encryption designs, testing techniques, and transforms. The projects aim to optimize aspects like area, speed, power consumption and implementation on FPGAs or ASICs.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
This paper evaluates the performance of the IEEE 802.11p standard for vehicular communication networks. The authors analyze the architecture of the Wireless Access in Vehicular Environments (WAVE) system and the IEEE 802.11p standard. They implement the key parameters of 802.11p in the ns-2 network simulator and use a realistic vehicular mobility model from VanetMobiSim. The performance metrics of throughput, end-to-end delay, and packet loss ratio are analyzed for a scenario of vehicles on a highway, with an ambulance transmitting periodic safety messages. The results show that vehicles can receive broadcast messages when within 138 meters of the ambulance, with little packet loss and similar throughput between vehicles
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET - Design of AMBA based AHB2APB Protocol for Efficient Utilization of AH...IRJET Journal
This document describes the design and implementation of an AHB2APB bridge to efficiently connect the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) in an AMBA-based system on chip (SoC) design. The AHB2APB bridge interfaces the two buses by buffering addresses and controlling the flow of data and control signals between the AHB and APB. Behavioral simulations were performed to verify the functionality of the bridge during single read/write, burst read/write, and back-to-back operations. The results indicate the bridge efficiently implements the AHB to APB protocol with low resource utilization on an Artix-7 FPGA board.
A defect is any serious or persistent event that interrupts transmission service. SDH uses defect processing to report and locate failures across entire circuits or specific network nodes. An alarm indication signal (AIS) is sent downstream to notify the next network element of an event, and a remote defect indication (RDI) is sent backwards in response. Depending on the affected service, AIS can take the form of MS-AIS, AU-AIS, TU-AIS, or PDH-AIS by setting bits to "1". Enhanced RDI provides additional information to differentiate between server, connectivity, and payload defects.
Design of Adjustable Reconfigurable Wireless Single Core CORDIC based Rake Re...IOSR Journals
In wireless communication system transmitted signals are subjected to multiple reflections,
diffractions and attenuation caused by obstacles such as buildings and hills, etc. At the receiver end, multiple
copies of the transmitted signal are received that arrive at clearly distinguishable time instants and are faded by
signal cancellation. Rake receiver is a technique to combine these so called multi-paths [2] by utilizing multiple
correlation receivers allocated to those delay positions on which the significant energy arrives which achieves a
significant improvement in the SNR of the output signal. This paper shows how the rake, including dispreading
and descrambling could be replaced by a receiver that can be implemented on a CORDIC based hardware
architecture. The performance in conjunction with the computational requirements of the receiver is widely
adjustable which is significantly better than that of the conventional rake receiver
This document provides a summary of Kumar Chandan and Mayank Kumar's summer internship report on RTL design, Verilog, and FPGA programming at Tevatron Technology in Noida, India. It includes an acknowledgements section thanking their mentor and institution for supporting the project. The abstract indicates that the main objective was to study digital circuit behavior and design using Xilinx software. An introduction is provided on topics like VLSI, HDLs, Verilog, modeling styles in Verilog, and system tasks.
Hardware implementation of (63, 51) bch encoder and decoder for wban using lf...ijitjournal
Error Correcting Codes are required to have a reliable communication through a medium that has an
unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area
Network (WBAN), data gets corrupted during the transmission and reception due to noises and
interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple
block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY.
In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The
incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct
up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register
(LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less
Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried
out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and
tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an
implementation of (63, 51) BCH encoder and decoder carried out.
Communication Protocols Augmentation in VLSI Design ApplicationsIJERA Editor
With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual) & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
This document summarizes research on verifying driver logic for the Advanced eXtensible Interface (AXI) protocol using the Universal Verification Methodology (UVM). It describes the AXI protocol and its advantages over other protocols. The research implemented a UVM verification environment for an AXI design with a master and slave agent. It verified the signaling of the five AXI channels: write address, write data, write response, read address, and read data. Address calculation formulas and the driver logic flow for each channel are presented. Simulation results showed the AXI design operated correctly according to the protocol.
October 2020: Top Read Articles in VLSI design & Communication Systems - Arti...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Top Trending Article in Academia! - VLSI design & Communication Systems (VLSI...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
A Review On AMBA AHB Lite Protocol And Verification Using UVM MethodologyTodd Turner
This document provides an overview of the AMBA protocol and discusses the AMBA AHB-Lite protocol and verification using the UVM methodology. It classifies the different types of AMBA protocols and describes their features and specifications. It then discusses the AMBA AHB-Lite protocol in more detail, describing its operation and features as a high performance bus with one master and multiple slaves. Finally, it describes the need for verification, the evolution of verification techniques, and the advantages of the Universal Verification Methodology (UVM) over conventional verification methods.
This document summarizes an implementation of a data error corrector using VLSI techniques. It describes a convolutional encoder and Viterbi decoder with a constraint length of 9 and code rate of 1/2, realized using Verilog HDL. Convolutional codes are used for forward error correction in digital data transmission by adding redundant bits. The Viterbi algorithm performs maximum likelihood decoding by using a trellis structure to calculate path metrics and select the most probable transmitted sequence. The implemented Viterbi decoder contains branch metric, path metric, and survivor memory units to decode a received bit stream encoded with a convolutional code. It was simulated and synthesized using Xilinx 13.1i tools.
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
Master's Degree Thesis on High Order Modulation and Coding Shemes for Satellite Transmitters
Advisors
Prof.dr. Roberto Garello
Eng.dr. Domenico Giancristofaro
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document describes an implementation of an LDPC decoder for IEEE 802.11n wireless networks using Vivado High-Level Synthesis. It implemented the decoder as a C program using Vivado HLS directives to optimize parallelism and throughput. The implementation achieved throughputs of over 1 Gbps and error correction performance comparable to an RTL implementation but with higher productivity due to the higher level of abstraction of C compared to RTL.
Design and Implementation of HDLC Controller by Using Crc-16IJMER
This document summarizes a research paper that designed, simulated, and implemented an HDLC controller using VHDL on a Spartan 3 FPGA. The HDLC controller supports data transmission rates up to 155.52 Mbps and complies with ITU and X.25 standards. It allows synchronous, transparent data transmission over point-to-point and multipoint channels. The design was tested through simulation and synthesis, and implemented CRC-16, bit stuffing/removal and error detection. The goal was to efficiently utilize FPGA resources to run the programmed design at high speeds.
This document describes using MATLAB Simulink to program and communicate between two dsPIC30f microcontrollers over a Controller Area Network (CAN) protocol. It presents the development of a real-time digital system using Simulink, Real-Time Workshop and Embedded Coder to generate C code from Simulink models. The C code is then compiled and run on the dsPIC30f microcontrollers. Specifically, it communicates engine RPM values transmitted by one microcontroller over CAN to the other microcontroller, which decodes and displays the RPM on an LCD screen. The decoding algorithm is also described.
This document contains information about various VLSI and low power projects, including titles, codes, and brief descriptions. It lists 30 projects related to topics like area-efficient adders and multipliers, low power filter and encryption designs, testing techniques, and transforms. The projects aim to optimize aspects like area, speed, power consumption and implementation on FPGAs or ASICs.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
This paper evaluates the performance of the IEEE 802.11p standard for vehicular communication networks. The authors analyze the architecture of the Wireless Access in Vehicular Environments (WAVE) system and the IEEE 802.11p standard. They implement the key parameters of 802.11p in the ns-2 network simulator and use a realistic vehicular mobility model from VanetMobiSim. The performance metrics of throughput, end-to-end delay, and packet loss ratio are analyzed for a scenario of vehicles on a highway, with an ambulance transmitting periodic safety messages. The results show that vehicles can receive broadcast messages when within 138 meters of the ambulance, with little packet loss and similar throughput between vehicles
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET - Design of AMBA based AHB2APB Protocol for Efficient Utilization of AH...IRJET Journal
This document describes the design and implementation of an AHB2APB bridge to efficiently connect the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) in an AMBA-based system on chip (SoC) design. The AHB2APB bridge interfaces the two buses by buffering addresses and controlling the flow of data and control signals between the AHB and APB. Behavioral simulations were performed to verify the functionality of the bridge during single read/write, burst read/write, and back-to-back operations. The results indicate the bridge efficiently implements the AHB to APB protocol with low resource utilization on an Artix-7 FPGA board.
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Verification of amba axi bus protocol implementing incr and wrap burst using ...eSAT Journals
Abstract This paper describes the development of verification environment for AMBA AXI (Advanced Extensible Interface) protocol using
System Verilog. AXI supports high performance, high-frequency system designs. It is an On-Chip communication protocol. It is
suitable for high-bandwidth and high frequency designs with minimal delays. It provides flexibility in the implementation of
interconnect architectures and avoid use of complex bridges. It is backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are that it consists of separate address, control and data phases. It support unaligned data
transfers using byte strobes. It requires only start address to be issued in a burst-based transaction. It has separate read and write
data channels that provide low-cost Direct Memory Access (DMA). This paper is aimed at the verification of various burst type
transaction (INCR and WRAP) of the AXI bus protocol and the Verification Environment is built using System Verilog coding[1].
Keywords: AMBA AXI, INCR, Wrap Burst, System Verilog
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VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
DOI : 10.5121/vlsic.2018.9303 31
VERIFICATION OF DRIVER LOGIC USING AMBA-
AXI UVM
Bijal Thakkar1
and V Jayashree2
1
Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering
Institute, Ichalkaranji, Maharashtra, India.
2
Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute,
Ichalkaranji, Maharashtra, India.
ABSTRACT
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of
its high performance and high-frequency operation without using complex bridges. AXI is also backward-
compatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is
presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and
AXI also supports out of order transfer based on the transaction ID which is generated at the start of the
transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification
Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI
protocol,the signals of these channels are driven to the interconnect and results are observed for single
master and single slave. The driver logic has been implemented and verified successfully according to AXI
protocol using the Rivera Pro. The results observed for single master and single slave have shown the
correctness of AMBA-AXI design in Verilog.
KEYWORDS
AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible Interface),UVM(Universal
Verification Methodology),channel.
1. INTRODUCTION
AXI stands for (Advanced Extensible Interface) and it is an On-Chip communication protocol. It
is a part of the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM
(Advanced RISC Machines) company. It provides high-frequency operation without using
complex bridges to meet the interface requirements of a wide range of components. It is suitable
for memory controllers with high initial access latency. AXI-UVM has separate address/control
and data phases. It supports for unaligned data transfers using byte strobes instead of supporting
burst based transactions with only start address issued. Also supports multiple outstanding
addresses without order response. Because of these features, AXI is the most commonly used on
chip bus protocols in the day-to-day high performance System On Chip (SOC’s).
In reference on AMBA AXI protocol specification, the signalling information and handshaking
signals and working of protocol from AMBA-AXI protocol has been reported[1].Gayathri M, and
RSA have reported, an efficient SV-UVM framework for the verification of Serial Gigabit Media
Independent Interface (SGMII) IP core, a single lane 1.25 Gbps data rate interface between
Ethernet Media Access Control (MAC) and Physical (PRY) layer[2].Rini Sebastian ,SGA
reported on benefits associated with Assertion Based Verification (ABV) which was successfully
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
32
applied to multiple levels of design abstraction . All simulations were carried out in NCsim and
waveforms were analysed in Simvision. All the assertions carried out were ensured without any
failure and shown the coverage capability of ABV through a case study on Serial Gigabit Media
Independent Interface (SGMII) IP core[3]. Golla Mahesh, Sakthivel.S.M reported on Verification
IP for an AMBA-AXI Protocol using System Verilog using the questa sim tool. In the verification
environment mailbox are used for communication between the different classes have presented
the coverage driven verification environment with functional coverage of 100%[4].
Mahendra.B.M,Ramachandra.A.C,Bus Functional Model Verification IP Development of AXI
Protocol have verified the various features of the AXI such as out of burst transactions and out of
order transactions and they are verified using the questa sim simulator [5]. AnushaRanga, L.
HariVenkatesh, Venkanna, Design and Implementation of AMBA-AXI Protocol Using VHDL
for SOC Integration have presented the rules for verifying the SOC as SOC is the complex design
and contains various components and in that they have verified the AXI protocol using the model
sim simulator[6].
Taking the literature review into account we have attempted to implemented the reusable
verification environment UVM (Universal Verification Methodology) for testing slave agent of
AXI protocol using AMBA bus. Also coverage analysis has been used as a parameter for testing
and also to demonstrate its usefulness using various assertions. Accordingly in Section II, the
architecture of the AXI-UVM is described where as in section III the methodology implemented
for AMBA-AXI with address calculation formulae is presented. Results and observations are
presented in sectionIV. Conclusion and future scope is explained in section V.
2. THEORETICAL BACKGROUND:ARCHITECTURE OF AXI-UVM
AXI provide flexibility in the implementation of interconnect architectures and it is also
backward-compatible with existing AHB and APB interfaces because of this main features AXI
protocol is efficient protocol because of its ultra-high-performance. It contains of five channels,
viz.; write address, write data,write response, read address, read data channel of AXI protocol.
These are considered for verification. The implemented AMBA AXI-UVM block diagram as
shown in Figure1. Universal Verification Methodology consist three blocks. 2.1.Top block having
test. 2.2. Testblock having environment with virtual sequence and 2.3. Environment and design
under test or interconnect
2.1 TOP BLOCK HAVING TEST
The top block creates instances of the Device Under Test (DUT) of the test bench. Top interface
module holds all the signals of the DUT. This acts as a link to the monitor, the driver and the
DUT.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
33
Figure. 1. Block diagram of AMBA AXI-UVM
2.2 TEST BLOCK HAVING ENVIRONMENT WITH VIRTUAL SEQUENCE
Test block is a top level block in UVM. It has two purposes first one is to create the environment
block and then to connect the sequencer to the sequence.
2.3 ENVIRONMENT AND DESIGN UNDER TEST OR INTERCONNECT
Environment consist of the five blocks viz, 2.3.1. Master agent 2.3.2 Slave agent
2.3.3 Scoreboard 2.3.4. Coverage 2.3.5. Virtual sequencer.
The environment is top most UVM verification environment.
2.3.1 MASTER AGENT
Master agent holds drivers, sequencer and monitors.Sequences signify the input to the DUT, such
as instructions, networking packets and bus transactions.
2.3.2 SLAVE AGENT
Slave agent holds drivers, sequencer and monitors. Monitors, sequencers and drivers can be used
independently.
2.3.3 SCOREBOARD
Scoreboard is built to check the response from the DUT against the expected response. It is done
by comparing them to the Reference Model.
2.3.4 COVERAGE
Functional coverage is the determination of how much functionality of the design has been
exercised by the verification environment.
2.3.5 VIRTUAL SEQUENCER
The virtual sequencer has the handles of physical sequencers which are pointed to physical
sequencers in the environment.
3. METHODOLOGY OF IMPLEMENTATION
Implementation of AXI-UVM is carried out using Rivera-Pro software. Rivera-Pro is tool
provided by aldec to deliver its customer innovative products in shorter time with high
performance simulation and containing supporting features that support verification libraries such
as UVM and also support verilog,system C and many more.The driver logic channels to be
verified for AXI-UVM are five which are mentioned as further.
3.1 Signals of write address channel
3.2 Signals of write data channel
3.3 Signals of write response channel
3.4 Signals of read address and control channel
3.5 Signals of read data and control channel
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
34
3.1. SIGNALS OF WRITE ADDRESS CHANNEL
During write logic transaction, the master asserts the AWVALID (Write address valid
signifies availability of valid write address and control information) signal only when it
drives valid address and control information. When asserted, AWVALID must remain
asserted until the rising clock edge after the slave asserts of AWREADY(Write address
ready indicates that slave is ready to accept an address). The default state of AWREADY
can be either HIGH or LOW. When AWREADY is HIGH the slave accepts any valid
address that is presented to it. The flowchart for implementation of Signals for write
address channel is as shown in figure 2.
Figure.2.Flow chart of driver logic of write address channel
Write Address calculation protocol is as shown below
i. Start Address = AxADDR
ii. Number of Bytes = 2 ^ AxSIZE
iii. Burst Length = AxLEN + 1
Here A stands for the AXI protocol and x stands for W for write channels and R for read
channels.
iv.
(1)
v. The equation used to determine the address of the first transfer in a burst:
Address_1 = Start Address. (2)
vi. For an INCR burst, and for a WRAP burst for which the address has not wrapped, this
equation (3) determines the address of any transfer after the first transfer in a burst:
(3)
vii. For a WRAP burst, the Wrap Boundary variable defines the wrapping boundary:
)x Burstlength))
x(No.ofBytes)x (Burst length) (4)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
35
3.2. SIGNALS OF WRITE DATA CHANNEL
The flow chart for the write data channel is similar to the write address channel shown in Fig
2.The difference is AWVALID,AWREADY,AWID(write address ID signal is an identification
tag for write data) in the address channel are WVALID(write valid signal indicates that a valid
write data is available),WREADY (write ready signal signifies that slave can accept valid write
data ) and WID (write ID tag signal is an ID tag of write data transfer) signals in the write data
channel. The master asserts the WVALID signal only when it drives valid write data. When
asserted, WVALID remains high until the rising clock edge after the slave asserts WREADY.
WLAST (write last this indicates the last transfer in burst) signal while it is driving the final write
transfer in the burst.
3.3 SIGNALS OF WRITE RESPONSE CHANNEL
As per the AXI protocol of driver logic, during write logic transaction,the slave asserts the
BVALID(write response valid,this signal indicates that the channel signaling a valid response)
signal only when it drives valid write response. When asserted, BVALID remains asserted until
the rising clock edge after the master asserts BREADY (Response ready, signal indicates that
master can accept a write response). The default state of BREADY can be HIGH, but only if the
master can always accepts a write response in a single cycle. The implementation of Signals of
write response channel is as shown in flowchart for of Figure 3.
Figure.3.Flow chart of driver logic of write response channel
3.4 SIGNALS OF READ ADDRESS CHANNEL
The flowchart of the read address channel is similar to the write address channel,the only
difference is the signals AWVALID,AWREADY,AWID in the write address channel is replaced
by the ARVALID(read address valid signal indicates that slave is ready to accept an
address),ARREADY(Read address ready signal indicates that slave is ready to accept an address)
and ARID (Read address ID signal is the identification tag for read address signals) as shown in
figure 4. As per AXI protocol of driver logic, during read logic transaction the master asserts the
ARVALID signal only when it drives valid address and control information. When asserted,
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ARVALID must remain asserted until the rising clock edge after the slave asserts the ARREADY
signal. The default state of ARREADY can be either HIGH or LOW. This specification
recommends a default state of HIGH, provided the slave must be able to accept any valid address
that is presented to it. The implementation of Signals of read address and control channel is as
shown in flowchart of Fig.4.
Figure.4.Flow chart of driver logic of read address channel.
3.5 SIGNALS OF READ DATA AND CONTROL CHANNEL
The read data and control channel is similar to the write data channel as shown in the flowchart
5,The slave assert the RVALID(Read valid signal indicates that the channel is signaling read data
) signal only when it drives valid read data. When asserted, RVALID must remain asserted until
the rising clock edge after the master asserts RREADY (Read ready signal indicates master can
accept read data and response information). Even if a slave has only one source of read data, it
asserts the RVALID signal only in response to a request for data. The master interface uses the
RREADY signal to indicate that it accepts the data. The implemented driver logic of read data
channel is as shown in flowchart of Fig.5
Figure.5.Flow chart of driver logic of read data channel
4 RESULTS AND OBSERVATION
Result for verification of AMBA-AXI for all five channels obtained from UVM environment of
Rivera-Pro is presented as below
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4.1. OUTPUT OF DRIVER LOGIC OF WRITE ADDRESS CHANNEL
Figure.6.Output of driver logic of write address channel
It is observed from Figure 6,for output of driver logic of write address channel that, when
AWVALID and AWREADY signal is high, then AWID and 32 bit AWADDR is generated as per
address calculation in the protocol.
4.2 OUTPUT OF DRIVER LOGIC OF WRITE DATA CHANNEL
Figure.7.Output of write data channel driver logic
It is observed from the waveform of Figure 7,that write identification match, WID match is
found with AWID as per the requirement .When WVALID signal is asserted,then WDATA is
sent according to the WID and WLAST signal is seen to be asserted after receiving last signal in
the burst.Here length of the data received is decided on the value of signal AWLEN
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4.3 OUTPUT OF DRIVER LOGIC OF WRITE RESPONSE CHANNEL
Figure.8. Output of driver logic of write response channel
It is observed from the waveform of Figure 8, on output driver logic of write response channel
that, after receiving all the data from the WDATA correctly, then BVALID signal has been
asserted. Though BREADY can be high or low, BREADY signal is found high as per
requirement of the protocol. Also match between BID, AWID and WID is seen as per
requirement after BVALID signal has arrived and the BRESP signal has gone low.
4.4 OUTPUT OF DRIVER LOGIC OF READ ADDRESS CHANNEL
Figure.9.Output of driver logic of read address channel
It is observed from the waveform of Figure 9 that, the read address channel operations are same
as the write address channel. ARADDR and ARID are found to be generated when ARVALID
and ARREADY signal is high. The ARREADY can come before ARVALID or it can come after
ARVALID or both ARREADY and ARVALID both can occur at same time. ARVALID and
ARREADY are seen to occur at the same time in the verification of read address channel as an
effect of randomization .
4.5 OUTPUT OF DRIVER LOGIC READ DATA AND CONTROL CHANNEL
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Figure.10. Output of driver logic of read data channel
It is seen from the waveform of Figure 10 that, according to the value of ARLEN signal the
length of the data is decided, the RID and ARID match is found as per protocol. RDATA signal
has come in output after receiving RVALID signal. Since RREADY signal can be high or it can
be low this RREADY signal is found to be high in the output as per required in the protocol also
RLAST(read last signal indicates the last transfer in read burst) signal is asserted after receiving
the last data in the burst and as decided according to the burst length.
5 CONCLUSION AND FUTURE SCOPE
In this paper the driver logic has been implemented and verified successfully according to the
protocol using the Rivera Pro and results are observed for single master and single slave. The
results have shown the correctness of AMBA-AXI protocol. Testing the design using coverage as
performance parameter and making it cacheable and bufferable are the future future scopes this
implemented design on AMBA AXI. This design can be used to implement the monitor logic in
which the signals driven by the channels can be collected in the monitor logic and can be
compared in the scoreboard in order to ensure the data driven and collected are exactly the same.
The axi can be used to observe the out of order transactions and out of burst transactions.
ACKNOWLEDGMENT
I would like to express my sincere gratitude towards Prof. Dr. Mrs.V.Jayashree Professor in
Electronics Engineering of DKTE Society's Textile & Engineering Institute, Ichalkaranji (An
Autonomous Institute) , who has been my supervisor. She has been my philosopher, mentor and
guide. She provided me with many helpful suggestions, important advice and constant
encouragement in this work.
REFERENCES
[1] Amba axi protocol specification, arm, 2011.
[2] Gayathri m, rini sebastian, silpa rose mary, anoop thomas, “a sv-uvm framework verification
of sgmii ip core with reusable axi to wb bridge uvc”, ieee ,3rd international on advance
computing and communication systems,jan 22 & 23 ,2016 ,coimbatore, india.
[3] Rini sebastian, silpa rose mary, gayathri m, anoop thomas, “assertion based verification of
sgmii ip core incorporating axi transaction verification model”, ieee,international conference
on control, communication & computing india (iccc), 19-21 november 2015 , trivandrum.
[4] Golla mahesh, sakthivel.s.m, verification ip for an amba-axi protocol using system verilog,
international journal ofengineering research and general science, volume 3, issue 1, january-
february, 2015.
[5] Mahendra.b.m,ramachandra.a.c, bus functional model verification ip development of axi
protocol, international journal ofengineeringresearch andgeneral science, volume 3, special
issue 1, february, 2014
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[6] Anusharanga, l. harivenkatesh, venkanna, design and implementation of amba-axi protocol
using vhdl for soc integration, international journal of engineering research and general
science, vol. 2, issue4, july-august 20,2012.
AUTHORS
Bijal Thakkar is currently pursuing her M.Tech in Electronics from Shivaji University,
Ichalkarnji .Doing project in DKTE Society’s Textile & Engineering Institute. She
Obtained her bachelor’s degree in Electronics and communication engineering from
Shivaji University,Kolhapur.Her interest includes,digital circuits design and Verification.