This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
Abstract
Frequency shift keying (FSK) is the most common form of digital modulation in the high-frequency radio spectrum. The
demodulation of Binary FSK involves complex operations on the modulated signal like reconstruction of carrier signal and
multiplication of carrier signal with the modulated signal. In this paper, BFSK is realized as two separate ASKs and a much
simpler incoherent method is proposed for demodulation of BFSK modulated signal. Since power consumption is one of the main
factors in electronic devices, low power devices are always demanding. Power Consumption could be minimized by reducing the
actual block diagram of the system by opting an alternative approach to achieve the same output signal. The same BFSK
demodulator can be used to demodulate an ASK modulated signal if it follow certain criteria’s.
Key Words: FSK, ASK, Demodulator, filters, MATLAB
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
Abstract
Frequency shift keying (FSK) is the most common form of digital modulation in the high-frequency radio spectrum. The
demodulation of Binary FSK involves complex operations on the modulated signal like reconstruction of carrier signal and
multiplication of carrier signal with the modulated signal. In this paper, BFSK is realized as two separate ASKs and a much
simpler incoherent method is proposed for demodulation of BFSK modulated signal. Since power consumption is one of the main
factors in electronic devices, low power devices are always demanding. Power Consumption could be minimized by reducing the
actual block diagram of the system by opting an alternative approach to achieve the same output signal. The same BFSK
demodulator can be used to demodulate an ASK modulated signal if it follow certain criteria’s.
Key Words: FSK, ASK, Demodulator, filters, MATLAB
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
Design and optimization of multi user OFDM orthogonal chaotic vector shift ke...journalBEEI
This paper study and present, power allocation strategy on sub-carriers of multiuser OFDM employed for orthogonal chaotic vector shift keying (MU OFDM-OCVSK) over multipath frequency selective fading channels. firstly, the MU OFDM-OCVSK system is modeled with power allocated on reference and information bearing subcarriers. Then, the computed bit error rate equation of the power allocation MU OFDM-OCVSK system is derived. The optimal power allocation strategy on subcarriers is obtained using convex optimization. Finally, compared with the traditional MU OFDM-DCSK and MU OFDM-OCVSK without power allocation system the proposed system can achieve an excellent BER performance under multipath Rayleigh fading channels. Numerical and Simulation results emphasize the remarkable features of the proposed optimal power allocation strategy.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. We propose a novel approach named tri-state buffer with common data bus which reduces the total power & delay of elastic buffer. The paper presents a design and implementation of tri-state buffer mechanism. This design offers also the advantage of third state (High Impedance state) of tri-state buffer. The proposed elastic buffer design using tri-state buffer is implemented in Cadence tools. The obtained result shows that our design is effective in terms 20.50 % reduction in total power, 89.67% reduction in delay.
Hybrid protocol for wireless EH network over weibull fading channel: performa...IJECEIAES
In this paper, the hybrid TSR-PSR protocol for wireless energy harvesting (EH) relaying network over the Weibull fading channel is investigated. The system network is working in half-duplex (HD) mode. For evaluating the system performance, the closed-form and integral-form expressions of the outage probability (OP) are investigated and derived. After that, numerical results convinced that our derived analytical results are the same with the simulation results by using Monte Carlo simulation. This paper provides a novel recommendation for the wireless EH relaying network.
Relay Vehicle Formations for Optimizing Communication Quality in Robot NetworksMd Mahbubur Rahman
Communication relay has vital importance in military, mining,
surveillance and rescue missions, where robots are remotely
controlled by an operator (e.g, drone) who stays in a safe location.
Problem: Wireless signal over distance degrades. Obstacles, terrain,
weather condition further attenuates the signal.
Solution: Relay robots are placed in between the operator and
remotely placed robotic units.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
Design and optimization of multi user OFDM orthogonal chaotic vector shift ke...journalBEEI
This paper study and present, power allocation strategy on sub-carriers of multiuser OFDM employed for orthogonal chaotic vector shift keying (MU OFDM-OCVSK) over multipath frequency selective fading channels. firstly, the MU OFDM-OCVSK system is modeled with power allocated on reference and information bearing subcarriers. Then, the computed bit error rate equation of the power allocation MU OFDM-OCVSK system is derived. The optimal power allocation strategy on subcarriers is obtained using convex optimization. Finally, compared with the traditional MU OFDM-DCSK and MU OFDM-OCVSK without power allocation system the proposed system can achieve an excellent BER performance under multipath Rayleigh fading channels. Numerical and Simulation results emphasize the remarkable features of the proposed optimal power allocation strategy.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. We propose a novel approach named tri-state buffer with common data bus which reduces the total power & delay of elastic buffer. The paper presents a design and implementation of tri-state buffer mechanism. This design offers also the advantage of third state (High Impedance state) of tri-state buffer. The proposed elastic buffer design using tri-state buffer is implemented in Cadence tools. The obtained result shows that our design is effective in terms 20.50 % reduction in total power, 89.67% reduction in delay.
Hybrid protocol for wireless EH network over weibull fading channel: performa...IJECEIAES
In this paper, the hybrid TSR-PSR protocol for wireless energy harvesting (EH) relaying network over the Weibull fading channel is investigated. The system network is working in half-duplex (HD) mode. For evaluating the system performance, the closed-form and integral-form expressions of the outage probability (OP) are investigated and derived. After that, numerical results convinced that our derived analytical results are the same with the simulation results by using Monte Carlo simulation. This paper provides a novel recommendation for the wireless EH relaying network.
Relay Vehicle Formations for Optimizing Communication Quality in Robot NetworksMd Mahbubur Rahman
Communication relay has vital importance in military, mining,
surveillance and rescue missions, where robots are remotely
controlled by an operator (e.g, drone) who stays in a safe location.
Problem: Wireless signal over distance degrades. Obstacles, terrain,
weather condition further attenuates the signal.
Solution: Relay robots are placed in between the operator and
remotely placed robotic units.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI CircuitsVLSICS Design
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is
robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often
found in critical paths of various large scale high performance circuits. Yet, due to high switching activity
they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we
propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and
Domino logic styles. For a given circuit, we extract the unate and binate components using a unate
decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,
area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate
blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our
approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and
22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS
logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATORVLSICS Design
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
The Gate diffusion input (GDI) is a novel technique
for low power digital circuit design. This techniq
ue
reduces the power dissipation, propagation delay, a
rea of digital circuits and it maintains low comple
xity
of logic design. In this paper, the 4×1 Multiplexer
, 8×3 Encoder, BCD Counter and Mealy State Machine
were implemented by using Pass Transistors (PT), Tr
ansmission Gate (TG) and Gate Diffusion Input (GDI)
technique and then they were compared with each oth
er for power dissipation. The Multiplexers and
Encoders are combinational circuits and Counters an
d mealy machines are sequential circuits both of th
em
are very important digital systems so power optimiz
ation should be done to those digital circuits. The
whole processes for development of digital circuits
and simulation was done by using the mentor graphi
cs
backend tool. This method can also be extended to t
he processors and other high level designs for
optimization of power dissipation, area and delay i
n order to increase the circuit efficiency.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
Area-Efficient Design of Scheduler for Routing Node of Network-On-ChipVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
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Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
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This is widely accepted that Network-on-Chip represents a promising solution for forthcoming complex embedded systems. The current SoC Solutions are built from heterogeneous hardware and Software components integrated around a complex communication infrastructure. The crossbar is a vital component of in any NoC router. In this work, we have designed a crossbar interconnect for serial bit data transfer and 128-parallel bit data transfer. We have shown comparision between power and delay for the serial bit and parallel bit data transfer through crossbar switch. The design is implemented in 0.180 micron TSM technology.The bit rate achived in serial transfer is slow as compared with parallel data transfer. The simulation resuls show that the critical path delay is less for parallel bit data transfer but power dissipation is high.
A ULTRA-LOW POWER ROUTER DESIGN FOR NETWORK ON CHIPijaceeejournal
The design of more complex systems becomes an increasingly difficult task because of different issues
related to latency, design reuse, throughput and cost that has to be considered while designing. In
Real-time applications there are different communication needs among the cores. When NoCs (Networks
on chip) are the means to interconnect the cores, use of some techniques to optimize the
communication are indispensable. From the performance point of view, large buffer sizes ensure
performance during different applications execution. But unfortunately, these same buffers are the main
responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case
latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router
architecture for NOC is designed for processing elements communicate over a second
communication level using direct-links between another node elements. Several possibilities to use the
router as additional resources to enhance complexity of modules are presented. The reconfigurable router
is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used
the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency
results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was
possible to reduce the congestion in the network, while at the same time reducing power dissipation and
improving energy.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace DFF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Improved Network on Chip Router for Low Power ApplicationsIJTET Journal
Abstract— On chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs. Buffers consume significant portions of router area. While running a traffic trace, however not all input ports of routers have incoming packets needed to be transferred simultaneously. So large numbers of buffer queues in the network are empty and other queues are mostly busy. This observation motivates us to design Router architecture with Shared Queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing multiple buffer queues among input ports. In the network design of the NoC the most essential things are a network topology and a routing algorithm. Routers route the packets based on the algorithm that they use. Every system has its own requirements for the routing algorithm. A new adaptive weighted XY routing algorithm for eight port router Architecture is proposed in order to decrease the latency of the network on chip router.
Design and verification environment for amba axi protocol for soc integrationeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIPVLSICS Design
This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
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SMART MULTICROSSBAR ROUTER DESIGN IN NOC
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
DOI : 10.5121/vlsic.2013.4207 75
SMART MULTICROSSBAR ROUTER DESIGN IN NOC
Bhavana Prakash Shrivastava1
and Kavita Khare2
1
Department of Electronics and Communication Engineering, Maulana Azad National
Institute of Technology, Bhopal, India
sonibhavana1@gmail.com
2
Department of Electronics and Communication Engineering, Maulana Azad National
Institute Of Technology, Bhopal, India
kavita_khare1@yahoo.co.in
ABSTRACT
This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router.
KEYWORDS
Network on chip, Virtual Channel, Virtual Allocator, Elastic Buffer, Power Delay Product (PDP).
1. INTRODUCTION
As the technology increases in order to improve the performance of future multi-cores the
researcher reduce the wire delay[1] .Insertion of buffer reduce wire delay as a result power
consumption increases. In order to solve these wire delay and scalability issues, researchers
suggested the use of a packet based communication network which is known as Network-on-Chip
(NoC)[2,3]. One of the major research challenges currently faced by NoC designers is that of
power dissipation, Power is dissipated by the NoCs in communicating data across the links as
well as in the storage and switching functions within the routers [4,5]. Researchers have shown
that almost 46% of the router power was consumed by the input buffers. Here elastic buffer (EB)
flow control utilizes existing pipeline flip-flops in the channels to implement distributed FIFOs,
eliminating the need for input buffers at the routers[6]. In the proposed design the in place of
single crossbar ,muticrossbar switch is used. The multi-crossbar configuration provides the lower
area due to split crossbars, reduces delay due to shorter path lengths and higher throughput due to
selective merging of different output ports.Here performance is evaluated on the basis of power
and delay product.
2. RELATED WORK
Different techniques have been proposed to reduce or eliminate the size of input buffers. Initially
iDEAL, a low-power area-efficient NoC ia achive by reducing the number of buffers within the
router[9]. Other designs targeting power saving with router design have different approaches. A
dynamic buffering resources allocation design named ViChaR (Virtual Channel Regulator)
focuses on efficiently allocating buffers to all virtual channels, by deploying a unified buffering
unit instead of a series of separated buffers, and minimizing the required size[10]. Another
approach utilizing channel buffering is the Elastic Channel Buffers (ECB), which replaces the
repeaters with flip-flops, and eliminates the router buffers altogether [6]. Other bufferless
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
76
networks such as FlitBLESS [7] and SCARAB [8] adopt either deflecting or dropping conflicting
packets, thereby reducing the latency and power, while sustaining throughput at low network
loads while at higher network loads, these networks suffer deflection/dropping leading to an
increase in power consumption. The crossbar within the NoC has also received a lot of attention
due to area overhead and power consumption.Reasearcher have proposed crossbar optimizations
that reduced the power consumption and area overhead and channel buffer organization. In the
proposed design elastic buffer multicrossbar router is implemented in which elastic buffer is used
for storage , single channel ,and muticrossbar configuration is defined.
3. ARCHITECTURE OF BASELINE ROUTER
A router in NoCs consists of buffers, switches, and control units which are required to store and
forward flits from the input ports to the desired output ports. The architecture is actually similar to
that of modern routers, but with smaller area and buffer size .Figure :1 shows a NoC 16 buffer
slots per input port. The buffer slots are divided into four queues, and each queue is called a
virtual channel (VC) [11,14]. There are four cardinal input ports and output ports connected from
and to +x, -x,+y and- y directions. The last pair of input/output ports are connected from and to
the processing element (PE). The four VCs are sandwiched between the de-multiplexer connected
to the input port, and the multiplexer connected to the crossbar. Each input unit can communicate
with router, virtual-channel allocator, and switch allocator[13], which are responsible for Routing
Computation (RC), Virtual-Channel Allocation (VA), and Switch Allocation (SA), respectively.
The crossbar is controlled by the switch allocator for correctly connecting input ports to output
ports [12].
Figure: 1 Base Line Router
Figure: 1 Base Line Router
4. PROPOSED ELASTIC BUFFER MULTICROSSBAR DESIGN
In the proposed multicrossbar router shown in Figure: 2 single cross bar is split into four smaller
crossbars to reduce area and delay. The division of the 4 crossbars are along the 4 quadrants: (+x,
+y) [North-East], (-x, -y) [South-West], (-x, +y) [North-West] and (+x, -y) [South-East].The
packet arrives from +x direction into I0, indicating that the quadrant is (x+, y+). This packet can
be routed to either O0 (+x direction) or O2 (+y direction) using the North-East crossbar. Similarly,
if the packet arrives from +x direction from I0 direction into the South-East crossbar, then the
possible outgoing directions will be O0 and O3, indicating that the destination quadrant is (x+, y-).
Routing Computation
(RC)
Virtual channel
Allocator
Switch Allocator
VC 0
VC 1
VC2
VC3
D
e
m
u
x
M
u
x
+X
-X
+Y
-Y
+X
-X
-Y
-Y
Crossbar
Processing Element
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
77
Therefore, by limiting the crossbar connections and combining select crossbar outputs, we
adaptively provide more opportunities for the output ports to be occupied than a conventional
crossbar. The multi-crossbar configuration provides lower area due to split crossbars, reduce
delay due to shorter path lengths and higher throughput due to selective merging of different
output ports.
Figure: 2 Proposed Elastic Buffer Router Using Multicrossbar
The function of processing element is to give feedback from output to input to show whether the
flit is valid or not. Buffers are in which the data moves serially as the virtual channel is eliminated
so the virtual allocator stage is eliminated. Switch arbiter (SA) is modified to make control over
the Demux and Mux to maintain the correct packet flow in the crossbars.
4.1. Elastic buffer
Elastic buffers (EBs) is an efficient flow-control scheme that uses the storage already present in
pipelined channels instead of input virtual-channel buffers(VCBs). Removing VCBs reduces the
area and power consumed by routers, but prevents the use of virtual-channel.
4.1.1 Elastic Buffer Channel
Here elastic buffer channel is discussed. EB channel is implemented by using Dflip-flop (DFF)
and control logic. Dflip-flop (DFF) shown in Figure: 3(a) is implemented using master slave flip
flop. EBs shown in Figure: 3(b) use a ready-valid handshake to advance a flit (flow-control
digit).An upstream ready (R) signal indicates that the downstream EB has at least one empty
storage location and can store an additional flit. A downstream valid (V) signal indicates that the
flit currently being driven is valid. A flit advances when both the ready and valid signals between
two EBs are asserted at the rising clock edge.
Routing Computation
(RC)
Switch arbiter
(SA)
Look ahead
signal
Elastic
Buffer
Elastic
Buffer
Elastic
Buffer
Elastic
Buffer
Processing Element
+X
-X
+Y
-Y
+X
-X
+Y
-Y
+X, +Y
-X,-Y
-X, +Y
+X,-Y
I0
I2
I1
I3
I1
′
I2
′
I0
′
I3
′
O0
O1
O2
O3
O4
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78
0 2
1 new
1 old
A
A
E2= 0
B
B
C
V_in
R_in
D
R_in =1
V_out=0
E2=0
E1=1
R_in =1
V_out=1
E2=1
E1=1
R_in =0
V_out=1
E2=0
E1=0
V_in V_out
R_outR_in
E1 E2
CLKCLK
ENSENM
Figure: 3(a) DFF (D-flip flop) using master slave FF
Figure: 3(b) Elastic buffer
Figure: 3(c) FSM of EB Control Logic
Figure: 3(c) shows the expanded view of the EB control logic as a FSM for two-slot EBs.Elastic
buffer works on the phenomenon of handshaking. EB channels feature provides multiple EBs to
form a distributed FIFO.
4.1. Comparative Analysis
The comparison between the two routers is compared on the basis of parameters. The
comparative table shown below in Table: 1
D Q
Master Latch
EN
D Q
Master Latch
EN
Clock
Data
D Q
Master Latch
EN
D Q
Master Latch
EN
Data
EB Control Logic
ENM ENS
R_OUT
V_OUT
R_IN
V_IN
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
79
Table: 1 Comparison table between the baseline router and proposed router.
Parameters Baseline Router Proposed
multicrossbar Router
Buffered Buffered Both buffered and
buffer less
Number of
crossbar used
One Four
Type of Buffer Virtual Channel Elastic buffer
Handshaking No Yes
Probability of
data lost
High Negligible
Speed Slow Fast
5. SIMULATION AND RESULTS
Implementation is done in cadence virtuoso at 180nm.All the parameters are set at the time of
simulation .The delay and average power is calculation is done. Delay of proposed router as
compare to base line router is reduced to 51.37% % at the cost minimal increase in power as
shown in Table 2 .This minimal increase in power is due to multicrossbar switches. The overall
performance gets increases due to the reduction of PDP by 37. 91%.
Table 2 shows the comparison based on the delay and total average power and PDP.
Router Design Delay(nsec) Total average
power(µW)
Power delay
product(Femto watt sec)
Baseline Router 4.117 194.6 801.16
Proposed elastic
buffer
multicrossbar router
2.002 290.2 580.98
Figure: 4 Implemented Circuit of Proposed Router in Cadence
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Figure: 5 Simulation of Proposed Router
Figure: 6 Total power calculation of Proposed Router
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
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Figure: 7 Delay calculation of Proposed Router
6. CONCLUSION
In this paper we evaluate the performance of crossbar organization using multi cross bar router
design using elastic buffer with an objective of reducing delay. The proposed design shows the
power delay product reduction by 37.91% and delay reduction of 51.37% compare to baseline
router design result in increase in performance. With the proposed design we conclude that the
advantage of both buffered and buffer less is achieved. At low traffic flit traverse from the first
multicrossbar and at high traffic flit traverse using elastic buffer via secondary multi-crossbar .In
multi-crossbar configuration due to split of crossbars ,delay is reduced. Higher throughput is
achieved due to selective merging of different output ports. Elastic buffer is enough to store a
number of flit on each port with accuracy as it works on handshaking principle. It is concluded
from the above discussion that proposed router design using multicrossbar provide better
performance as compared to baseline router design.
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Authors Biography
Bhavana Prakash Shrivatava received her degree in Electronics and
Communication Engineering in 2003, M.Tech. degree in Digital
Communication Systems in2007.Now she is persuing her Ph.D degree in VLSI
design under the guidance of Dr.Kavita Khare. She is working as Assistant
Professor in Electronics and Communication Engineering in MANIT, Bhopal.
Her fields of interest are VLSI design and Communication Systems and
networking.She is fellow of IEEE (India).
Kavita Khare received her B.Tech degree in Electronics and Communication
Engineering in 1989, M.Tech. degree in Digital Communication Systems in
1993 and Ph.D. degree in the field of VLSI Design in 2005. She has nearly
100 publications in various international conferences and journals. Currently,
she is working as Professor of Electronics and Communication Engineering in
MANIT, Bhopal. Her fields of interest are VLSI design and Communication
Systems. Her research mainly includes design of arithmetic circuits and
various communication algorithms related to synchronization, estimation and
routing. Dr. Khare is a Fellow IETE (India) and Life Member ISTE.