This document summarizes an article from the International Journal of Electronics and Communication Engineering & Technology that proposes a design for an efficient AXI2.0 to APB bridge. It begins with introductions to the AXI2.0 and APB protocols. It then describes the proposed bridge design, which uses asynchronous FIFOs to connect the different clock domains and resolve protocol mismatches. The design is implemented in VHDL and synthesized on a Xilinx Virtex 4 FPGA. Simulation results and the synthesis report are presented, showing the bridge utilizes a small amount of device resources.