in these slides you will find basic concept of combinational and sequenstional logic. these ppts are designed for students of electrical engineering, and covers all the necessary topic of their interest.

1. UNIT-4
Mohammad Asif Iqbal
Assistant Professor,
Deptt of ECE,
JETGI, Barabanki

2. Multiplexers
 A multiplexer has
 N control inputs
 2N
data inputs
 1 output
 A multiplexer routes (or connects) the selected data
input to the output.
 The value of the control inputs determines the data input that
is selected.

3. Multiplexers
Z = A′.I0 + A.I1
Data
inputs
Control
input

4. Multiplexers
Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3
A B F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MSB LSB

5. Multiplexers
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
MSB LSB
A B C F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

6. Multiplexers

7. Encoder/Decoder Vocabulary
ENCODER- a digital circuit that produces a binary output code
depending on which of its inputs are activated.
DECODER- a digital circuit that converts an input binary code
into a single numeric output.

8. ENCODERS AND DECODERS
A0
A1
A2
A3
A4
A5
A6
A7
ENCODER
O0
O1
O2
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7
DECODER
ONLY ONE INPUT ACTIVATED
AT A TIME
BINARY CODE OUTPUT
BINARY CODE INPUT
ONLY ONE OUTPUT
ACTIVATED AT A TIME

9. THE 8421 BCD CODE
• BCD stands for Binary-Coded Decimal.
• A BCD number is a four-bit binary group that represents one of
the ten decimal digits 0 through 9.
Example:
Decimal number 4926 4 9 2 6
8421 BCD coded number 0100 1001 0010 0110

10. ELECTRONIC ENCODER-DECIMAL TO BCD
0
Decimal
to
BCD
Encoder
BCD output
Decimal input
0 0 0 0
5
0 1 0 1
7
0 1 1 1
3
0 0 1 1
• Encoders are available in IC form.
• This encoder translates from decimal input to
BCD output.

11. 10 line to 4 line Encoder

13. ENCODER
1248
DECIMAL BINARY (BCD)
9 5V
8 5V
7 5V
6 5V
5 5V
4 5V
3 5V
2 5V
1 5V
74147
I9
I8
I7
I6
I5
I4
I3
I2
I1
A0
A1
A2
A3
10 line to 4 line Encoder

15. 0
1
2
3
4
5
6
7
8
9
DECODER
BINARY (BCD)
DECIMAL
1 0V
2 0V
4 0V
8 0V
74LS42
A3
A2
A1
A0
9
8
7
6
5
4
3
2
1
0
4 line to 10 line Decoder

16. BCD-to-
7-Segment
Decoder/
Driver
DECODERS: BCD TO 7-SEGMENT DECODER/DRIVER
BCD input
0 0 0 0
Decimal output
LED
0 0 0 10 0 1 00 0 1 10 1 0 0
• Electronic decoders are available in IC form.
• This decoder translates from BCD to decimal.
• Decimals are shown on an 7-segment LED display.
• This IC also drives the 7-segment LED display.

18. BEFORE STARTING LET’S RECALL NAND GATE
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

19. BASIC STORAGE ELEMENT
0
1
1
0
1
LATCH

20. FLIP-FLOP
CLOCK
S
R
Q
Q’
=1
=0
0
1
=1
=0
0
0
1
0
0 0 1 0

21. FLIP-FLOP
CLOCK
S
R
Q
Q’
=0
=1
1
0
=0
=1
0
0
0
1
0 0 1 0
0 1 0 1
0 0 0 1

22. FLIP-FLOP
INPUT OUTPUT
S R Q Q’
0 0 NO CHANGE
0 1 0 1
1 0 1 0
1 1 ? ?
S
R
CLOCK
Q’
Q SET
RSET
=1
=1
0
0
=1
=1
INDETERMINANT
CHARACTERISTIC
TABLE

23. BLOCK DIAGRAM REPRESENTATION
S
R
Q’
Q
CLOCK
D
D Q Q’
0 0 1
1 1 0
Q Q(n+1) D
0 0 1
1 1 0
Q(n) D Q(n+!)
0 0 1
1 1 0

24. D FLIP-FLOP
D Q Q’
0 0 1
1 1 0
Q Q(n+1) D
0 0 1
1 1 0
Q(n) D Q(n+!)
0 0 1
1 1 0
CHARACTERIS
TIC TABLE
TRUTH TABLE
EXCITATION
TABLE

25. J K FLIP-FLOP
J
K
CLOCK
Q
Q’
=1
=0
1
0
=1
=1
=1
=0=0
=1 =0
=1

26. WAVE FORM REPRESENTATION
(t)
T 2T
CLOCK
Q
0
1
NOW, changes at I/P
will affect O/PAny change at I/P
will not effect O/P
0
1
RACE
AROUND
CONDITION

27. SOLUTION OF RACE AROUND CONDITION
(t)
T 2T
CLOCK
Q
0
1
0
1
T F
PROPAGATION DELAY

28. FINAL SOLUTION……
(t)
T 2T
CLOCK
Q
0
1
0
1

29. JK FLIP-FLOP
CHARACTERIS
TIC TABLE
TRUTH TABLE
EXCITATION
TABLE

30. PROBLEMS
Q:- Determine the output of PGT
clocked SR flip flop which Q
initially 0 for the given input
waveforms
Q
Q’
Q:- Determine the output of PGT
clocked SR flip flop which Q
initially 1 for the given input
waveforms.

31. Master Slave Flip Flop
K
J
Q
Q’=0
=1
0 0 1 1
=1
=1
1
0
=1
=0 =1
=0=0
=1

32. Analysis of clocked sequential circuits
X’
B
BX’
B

33. Definition
• A register is a digital circuit with two basic functions:
Data Storage and Data Movement
• A shift register provides the data movement function
• A shift register “shifts” its output once every clock cycle
• A shift register is a group of flip-flops set up in a linear
fashion with their inputs and outputs connected
together in such a way that the data is shifted from one
device to another when the circuit is active

34. Shift Register Applications
• converting between serial
data and parallel data
• temporary storage in a
processor
• scratch-pad memories
• some arithmetic
operations
• multiply, divide
• communications
• UART
• some counter applications
• ring counter
• Johnson counter
• Linear Feedback Shift Register
(LFSR) counters
• time delay devices
• more …

35. Shift Register Characteristics
• Types
• Serial-in, Serial-out
• Serial-in, Parallel-out
• Parallel-in, Serial-out
• Parallel-in, Parallel-out
• Universal
• Direction
• Left shift
• Right shift
• Rotate (right or left)
• Bidirectional
n-bit shift
register

36. Data Movement
• The bits in a shift register can move in any of the following manners

37. n-bit shift
register
n-bit shift
register
Data Movement
• Block diagrams for shift registers with various input/output
options:
n-bit shift
register
n-bit shift
register

38. n-bit shift
register
Serial-In Serial-Out
• Data bits come in one at a time and
leave one at a time
• One Flip-Flop for each bit to be
handled
• Movement can be left or right, but is
usually only in a single direction in
a given register
• Asynchronous preset and clear
inputs are used to set initial values

39. Serial-In Serial-Out
• The logic circuit diagram below shows a generalized
serial-in serial-out shift register
• SR Flip-Flops are shown
• Connected to behave as D Flip-Flops
• Input values moved to outputs of each Flip-Flop with the clock (shift) pulse
N-Bit Shift Register
0N 1

40. Shift Registers
• The simplest shift register is one that uses only Flip-Flops
• The output of a given Flip-Flop is connected to the D input of the Flip-Flop at its
right.
• Each clock pulse shifts the contents of the register one bit position to the right.
• The Serial input (SI) determines what goes into the leftmost Flip-Flop during the
shift. The Serial output (SO) is taken from the output of the rightmost Flip-Flop.
Q Q QQ

41. Serial-In Serial-Out
• A simple way of looking at
the serial shifting operation,
with a focus on the data bits,
is illustrated at right
• The 4-bit data word “1011”
is to be shifted into a 4-bit
shift register
• One shift per clock pulse
• Data is shown entering at
left and shifting right
41
1
2
3
4
5

42. Serial-In Serial-Out
• The diagram at right
shows the 4-bit sequence
“1010” being loaded into
the 4-bit serial-in serial-
out shift register
• Each bit moves one
position to the right each
time the clock’s leading
edge occurs
• Four clock pulses loads
the register
42

43. Serial-In Serial-Out
• This diagram shows the 4-
bit sequence “1010” as it
is unloaded from the 4-
bit serial-in serial-out
shift register
• Each bit moves one
position to the right each
time the clock’s leading
edge occurs
• Four clock pulses unloads
the register
43

44. Serial-In Serial-Out
• Serial-in, serial-out
shift registers are often
used for data
communications
• such as RS-232
• modem transmission and
reception
• Ethernet links
• SONET
• etc.

45. Serial-to-Parallel Conversion
• We often need to convert from serial
to parallel
• e.g., after receiving a series transmission
• The diagrams at the right illustrate a
4-bit serial-in parallel-out shift
register
• Note that we could also use the Q of
the right-most Flip-Flop as a serial-
out output
n-bit shift
register

46. Serial-to-Parallel Conversion
• We would use a serial-in
parallel-out
shift register of
arbitrary length N to
convert an N-bit word
from serial to parallel
• It would require N clock
pulses to LOAD and one
clock pulse to UNLOAD

47. Serial-to-Parallel Conversion
• These two shift
registers are used to
convert serial data to
parallel data
• The upper shift
register would “grab”
the data once it was
shifted into the lower
register

48. Parallel-to-Serial Conversion
• We use a Parallel-in Serial-out Shift
Register
• The DATA is applied in parallel form to the
parallel input pins PA to PD of the register
• It is then read out sequentially from the
register one bit at a time from PA to PD on
each clock cycle in a serial format
• One clock pulse to load
• Four pulses to unload
n-bit shift
register

49. Parallel-to-Serial Conversion
• Logic circuit for a parallel-in, serial-out shift register
Mux-like
0
0
1
0
1
1

50. Parallel-In Parallel-Out
• Parallel-in Parallel-out Shift
Registers can serve as a temporary
storage device or as a time delay
device
• The DATA is presented in a parallel
format to the parallel input pins PA
to PD and then shifted to the
corresponding output pins QA to
QD when the registers are clocked
• One clock pulse to load
• One pulse to unload
50

51. n-bit shift
register
Universal Shift Register
• Universal shift register
• Can do any combination of parallel
and serial input/output operations
• Requires additional inputs to
specify desired function
• Uses a Mux-like input gating
L/SL/S
A
B
A
B
F
1
0
1
0

52. Universal Shift Register
• Parallel-in, parallel-out shift register
Mux-like
0
0
1
0
1
1

53. Universal Shift Register
• Parallel shift register (can serve as converting
parallel-in to serial-out shifter):

54. Registers summary
• A register is a special state machine that stores multiple bits
of data
• Several variations are possible:
• Parallel loading to store data into the register
• Shifting the register contents either left or right
• Counters are considered a type of register too!
• One application of shift registers is converting between serial
and parallel data
• Most programs need more storage space than registers provide
• We’ll introduce RAM to address this problem
• Registers are a central part of modern processors

55. Introducing counters
• Counters are a specific type of sequential circuit
• The state serves as the “output” (Moore)
• A counter that follows the binary number sequence is called a binary
counter
• n-bit binary counter: n flip-flops, count in binary from 0 to 2ⁿ-1
• Counters are available in two types:
• Synchronous Counters
• Ripple Counters
• Synchronous Counters:
• A common clock signal is connected to the C input of each flip-flop

56. Synchronous Binary Up Counter
• The output value increases by one on each clock cycle
• After the largest value, the output “wraps around” back to 0
• Using two bits, we’d get something like this:
Present State Next State
A B A B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
00 01
1011

57. Synchronous Binary Up Counter
Present State Next State
A B A B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
D1= A’B + AB’
D0= B’
clock
A
B

58. What good are counters?
• Counters can act as simple clocks to keep track of “time”
• You may need to record how many times something has happened
• How many bits have been sent or received?
• How many steps have been performed in some computation?
• All processors contain a program counter, or PC
• Programs consist of a list of instructions that are to be executed
one after another (for the most part)
• The PC keeps track of the instruction currently being executed
• The PC increments once on each clock cycle, and the next program
instruction is then executed.

59. Synch Binary Up/Down Counter
• 2-bit Up/Down counter
• Counter outputs will be 00, 01, 10 and 11
• There is a single input, X.
> X= 0, the counter counts up
> X= 1, the counter counts down
• We’ll need two flip-flops again. Here are the four possible states:
00 01
1011

60. The complete state diagram and table
00 01
1011
0
0
0
10 1
1
1
Present State Inputs Next State
Q1 Q0 X Q1 Q0
0 0 0 0 1
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 0
• Here’s the complete state diagram and state table for this circuit

61. D flip-flop inputs
• If we use D flip-flops, then the D inputs will just be the same as the desired next
states
• Equations for the D flip-flop inputs are shown at the right
• Why does D0 = Q0’ make sense?
Present State Inputs Next State
Q1 Q0 X Q1 Q0
0 0 0 0 1
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 0
Q0
0 1 0 1
Q1 1 0 1 0
X
Q0
1 1 0 0
Q1 1 1 0 0
X
D1 = Q1  Q0  X
D0 = Q0’

62. Synchronous Binary Up/Down Counter
clock
X Q1
Q0

63. Unused states
• The examples shown so far have all had 2n
states, and used n flip-flops. But
sometimes you may have unused, leftover states
• For example, here is a state table and diagram for a counter that repeatedly
counts from 0 (000) to 5 (101)
• What should we put in the table for the two unused states?
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0
1 1 0 ? ? ?
1 1 1 ? ? ?
001
010
011
100
101
000

64. Unused states can be don’t cares…
• To get the simplest possible circuit, you can fill in don’t cares for the
next states. This will also result in don’t cares for the flip-flop inputs,
which can simplify the hardware
• If the circuit somehow ends up in one of the unused states (110 or 111),
its behavior will depend on exactly what the don’t cares were filled in with
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0
1 1 0 x x x
1 1 1 x x x
001
010
011
100
101
000

65. 65
…or maybe you do care
• To get the safest possible circuit, you can explicitly fill in next states
for the unused states 110 and 111
• This guarantees that even if the circuit somehow enters an unused state,
it will eventually end up in a valid state
• This is called a self-starting counter
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 0 0 0
001
010
011
100
101
000
111110

66. More complex counters
• It can increment or decrement, by setting the UP input to 1 or 0
• You can immediately (asynchronously) clear the counter to 0000
by setting CLR = 1
• You can specify the counter’s next output by setting D3-D0 to any
four-bit value and clearing LD
• The active-low EN input enables or disables the counter
• When the counter is disabled, it continues to output the same
value without incrementing, decrementing, loading, or clearing
• The “counter out” CO is normally 1, but becomes 0
when the counter reaches its maximum value, 1111

67. 2-bit Complex Binary Counter
R
Q1
Q0
CO
R
EN
LD
D1
CLK
D0
UP
CLR

68. An 8-bit counter
• As you might expect by now, we can use
these general counters to build other
counters
• Here is an 8-bit counter made from two 4-bit
counters
• The bottom device represents the least significant four
bits, while the top counter represents the most significant
four bits
• When the bottom counter reaches 1111 (i.e., when CO =
0), it enables the top counter for one cycle
• Other implementation notes:
• The counters share clock and clear signals
• Hex displays are used here

69. A restricted 4-bit counter
• We can also make a counter that “starts” at some value besides 0000
• In the diagram below, when CO=0 the LD signal forces the next state
to be loaded from D3-D0
• The result is this counter wraps from 1111 to 0110 (instead of 0000)

70. Another restricted counter
• We can also make a circuit that counts up to only 1100, instead of 1111
• Here, when the counter value reaches 1100, the NAND gate forces
the counter to load, so the next state becomes 0000

71. Ripple Counter
Simple, yet asynchronous circuits !!!

72. Summary
• Counters serve many purposes in sequential logic design
• There are lots of variations on the basic counter
• Some can increment or decrement
• An enable signal can be added
• The counter’s value may be explicitly set
• There are also several ways to make counters
• You can follow the sequential design principles to build counters
from scratch
• You could also modify or combine existing counter devices

73. THANK YOU!