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CS-121: Digital Logic and Design
Lecture # 15
Registers
Instructor: Alina Maryum
1
Registers
• A register is a group of binary storage cells suitable for holding binary information.
• A group of flip-flops constitutes a register, since each flip-flop is a binary cell capable
of storing 1-bit of information.
• An n-bit register has a group of n flip-flops and is capable of storing any binary
information containing n bits.
• In addition to the flip-flops, a register may have combinational gates that perform
certain data-processing tasks.
• In its broader definition, a register consists of a group of flip-flops and gates that
effect their transition.
• The flip-flops hold binary information and the gates control when and how new
information is transferred into the register.
Registers (Cont..)
• Various types of registers are available but the simplest possible being
the one that consists of only flip flops without any external gates as
shown in figure 7-1
• 4 D-Flip Flops
• Common clock
• 4-bit register
Parallel Load
• The transfer of new information into a register is referred to as
loading/ updating the register.
• If all the bits of the register are loaded simultaneously with a single
clock pulse, it is said that loading is done in parallel.
• Parallel Load
Serial Transfer/ Parallel Transfer
• If all the bits of the register are loaded simultaneously with a single
clock pulse, it is said that loading is done in parallel.
• Parallel Transfer
• If only a single bit of the register is transferred with a single clock
pulse, it is said that loading is done in serial.
• Serial Transfer
Shift Registers
• A register capable of shifting its binary information either to the right
or to the left.
• Configuration:
• A chain of a Flip flops connected in cascade
• Output of one FF connected to the input of the next.
• Common clock causes shift from one stage to the other.
Shift Register
• The simplest possible shift register is one that uses only flip-flops (Fig. 7-7)
• The Q output of a flip-flop is connected to the D input of the flip-flop at its right.
• Each clock pulse shifts the contents of the register one bit position to the right.
• The serial input determines what goes into the leftmost flip-flop during the shift.
• The serial output is taken from the output of the right most flip-flop prior to the
application of a pulse.
Types of Shift Register
1. Serial In - Serial Out (SISO)
Types of Shift Register
2. Serial In - Parallel Out (SIPO)
Types of Shift Register (Cont..)
3. Parallel In - Serial Out (PISO)
Types of Shift Register (Cont..)
4. Parallel In - Parallel Out (PIPO)
Serial Transfer
A digital system is said to operate in serial mode when information is
transferred and manipulated one bit at a time.
The contents of register is transferred to another by shifting the bits
from one register to the other.
Serial Transfer (Example)
• The serial transfer of information from register A to register B is done with shift
registers As shown in the block diagram of Fig. 7-8 (a).
• The Serial Output (SO) of register A goes to the Serial Input (SI) of register B.
• To prevent the loss of information stored in source register, register A is made
to circulate its information by connecting the serial output to its serial input
terminal.
Serial Transfer (Example)
• The initial contents of B is shifted through its serial output and is lost unless it is
transferred to a third shift register.
• The shift control input determines when and by how many times the registers
are shifted (done by using AND gate)
Serial Transfer (Example)
• Suppose the shift registers A and B both have 4 bits each where;
• A = 1011 and B = 0010
• After 4 clock pulse:
• A = 1011 (Retain) and B = 1011 (Contents of A will be shifted to B)
Example 2-Timing Diagram
Example-2 (Cont..)
• Input: 1101
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Example-2 (Cont..)
t=0 t=1 t=2 t=3 t=4 t=5 t=6
Clk
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Reference
• Digital Logic and Design by M Morris Mano, 5th Edition, Chapter 7

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lecture .pptx

  • 1. CS-121: Digital Logic and Design Lecture # 15 Registers Instructor: Alina Maryum 1
  • 2. Registers • A register is a group of binary storage cells suitable for holding binary information. • A group of flip-flops constitutes a register, since each flip-flop is a binary cell capable of storing 1-bit of information. • An n-bit register has a group of n flip-flops and is capable of storing any binary information containing n bits. • In addition to the flip-flops, a register may have combinational gates that perform certain data-processing tasks. • In its broader definition, a register consists of a group of flip-flops and gates that effect their transition. • The flip-flops hold binary information and the gates control when and how new information is transferred into the register.
  • 3. Registers (Cont..) • Various types of registers are available but the simplest possible being the one that consists of only flip flops without any external gates as shown in figure 7-1 • 4 D-Flip Flops • Common clock • 4-bit register
  • 4. Parallel Load • The transfer of new information into a register is referred to as loading/ updating the register. • If all the bits of the register are loaded simultaneously with a single clock pulse, it is said that loading is done in parallel. • Parallel Load
  • 5. Serial Transfer/ Parallel Transfer • If all the bits of the register are loaded simultaneously with a single clock pulse, it is said that loading is done in parallel. • Parallel Transfer • If only a single bit of the register is transferred with a single clock pulse, it is said that loading is done in serial. • Serial Transfer
  • 6. Shift Registers • A register capable of shifting its binary information either to the right or to the left. • Configuration: • A chain of a Flip flops connected in cascade • Output of one FF connected to the input of the next. • Common clock causes shift from one stage to the other.
  • 7. Shift Register • The simplest possible shift register is one that uses only flip-flops (Fig. 7-7) • The Q output of a flip-flop is connected to the D input of the flip-flop at its right. • Each clock pulse shifts the contents of the register one bit position to the right. • The serial input determines what goes into the leftmost flip-flop during the shift. • The serial output is taken from the output of the right most flip-flop prior to the application of a pulse.
  • 8. Types of Shift Register 1. Serial In - Serial Out (SISO)
  • 9. Types of Shift Register 2. Serial In - Parallel Out (SIPO)
  • 10. Types of Shift Register (Cont..) 3. Parallel In - Serial Out (PISO)
  • 11. Types of Shift Register (Cont..) 4. Parallel In - Parallel Out (PIPO)
  • 12. Serial Transfer A digital system is said to operate in serial mode when information is transferred and manipulated one bit at a time. The contents of register is transferred to another by shifting the bits from one register to the other.
  • 13. Serial Transfer (Example) • The serial transfer of information from register A to register B is done with shift registers As shown in the block diagram of Fig. 7-8 (a). • The Serial Output (SO) of register A goes to the Serial Input (SI) of register B. • To prevent the loss of information stored in source register, register A is made to circulate its information by connecting the serial output to its serial input terminal.
  • 14. Serial Transfer (Example) • The initial contents of B is shifted through its serial output and is lost unless it is transferred to a third shift register. • The shift control input determines when and by how many times the registers are shifted (done by using AND gate)
  • 15. Serial Transfer (Example) • Suppose the shift registers A and B both have 4 bits each where; • A = 1011 and B = 0010 • After 4 clock pulse: • A = 1011 (Retain) and B = 1011 (Contents of A will be shifted to B)
  • 18. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 19. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 20. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 21. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 22. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 23. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 24. Example-2 (Cont..) t=0 t=1 t=2 t=3 t=4 t=5 t=6 Clk D3 D2 D1 D0 Q3 Q2 Q1 Q0
  • 25. Reference • Digital Logic and Design by M Morris Mano, 5th Edition, Chapter 7