The document discusses implementing convolution on an FPGA. It begins by introducing convolution and its applications in image processing. It then discusses the scope and technical approach of implementing discrete linear convolution on FPGA kits in order to perform convolution on images in real-time. The document outlines the structure of FPGAs, including configurable logic blocks and wiring tracks. It also discusses software requirements and provides an organization plan for subsequent chapters on linear convolution, FPGA technology, and a literature survey.

1. CHAPTER 1
CONVOLUTION IMPLEMENTED ON FPGA
1.1 Introduction
The main aim of implementing convolution on FPGA is to design hardware that can reduce the
convolution processing time and implement the discrete convolution of two finite length
sequences (NXN). Many image processing operations such as scaling and rotation require
resampling or convolution filtering for each pixel in image. Convolutions on digital images are
important since they represent operations more general than the operations that can be performed
on analog images. Filtering of signals is very important in order to determine which one to
accept and which one to reject, and all of this is done by convolution.
1.2 Scope
Implementation of discrete linear convolution for finite length sequences on FPGA kit, the
purpose to prove the feasibility of an FPGA that performs a convolution on an acquired image in
real time. is used in DSP applications. For example, it is used in image compression. The image
compression takes place in 3 steps. Image consists of number of pixels. Each pixel is encoded in
the first step. In the second step this encoded data will be transferred to the DWT (Discrete
Wavelet Transform). The function of this DWT is to analyze the image means it tells how many
lower order pixels and how many higher order pixels in the image. Compared to DFT, FFT,
DWT having more accuracy. DWT consists of filters. Pixels are analyzed by using these filters.
The DWT uses MAC unit. By using convolution, the operation of MAC unit is possible. In the
third step quantization will be done. By using this lower order pixels are quantized to zero. In
this way the image is compressed.
1.3 Technical Approach
Semicustom refers an integrated circuit that has been designed either by using existing blocks of
design elements or is made on an existing array of gates which are just connected together to
form a new circuit. Custom design means making for specific application. Pre-designed library
cells and routing and placing in semi custom technology. SPARTAN 2E FPGA kit having
XC2S100 device, TQ144 package with speed 5. SPARTAN2E having several features.
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2. Features of FPGA
The FPGA contains an on-board power supply and an on-board crystal oscillator for clock
pulses. The SPARTAN2E TQ144 package in FPGA has 15,000 to 100,000 gates. Some of the
features are ,On board reset software,20 user designable switches, four 7 segment displays,16
user definable LEDs, 4x4 keyboard, power indicator LED,I/O voltage configurability, user
hardware interface, slave serial/JTAG mode of configuration, compatible with all freely
available software’s
The proposed implementation uses a modified hierarchical design approach, Hardware
resources area significantly. The efficiency of the proposed convolution circuit is tested by
embedding it in a top level FPGA.
1.4 Literature Survey
The most important operation performed on signals is linear filtering, which can be performed by
convolution. The reason that linear filtering is so important to signal processing is that it solves
many problems and is relatively simple to describe mathematically. Convolution helps to
determine the effect a system has on an input signal. It can be shown that a linear, time-invariant
system is completely characterized by its impulse response. Using the sampling property of the
delta function for continuous time signals and the unit sample for discrete time signals
decompose a signal into an infinite sum / integral of scaled and shifted impulses.
By knowing how a system affects a single impulse, and by understanding the way a
signal is comprised of scaled and summed impulses, it seems reasonable that it should be
possible to scale and sum the impulse responses of a system in order to determine what output
signal will results from a particular input. This is precisely what convolution does - convolution
determines the system's output from knowledge of the input and the system's impulse response.
The presented circuit uses less power consumption and delay from input to output. It also
provides the necessary modularity, expandability, and regularity to form different convolutions
for any number of bits.
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3. 1.5 Software Requirements
Simulation purpose the modelsim software and for the synthesize purpose the Xilinx ISE 10.1
software are used. Simulation means compilation and verification of code will be done.
Synthesize means it will generate the gate level net list for the given code. For these software’s
we are using the VHDL language. A hardware description language is a language that describes
the hardware of digital systems in a textual form. It resembles a programming language, but is
specifically oriented to describing hardware structures and behavior. It can be used to represent
logic diagrams, boolean expressions, and other more complex digital circuits. HDL is used to
represent document digital systems in a form that can be ready by both humans and computers
and is suitable as an exchange language between designers.
There are two applications of HDL processing.
1. Simulation
2. Synthesis.
Logic simulation is the representation of the structure and behavior of a digital logic
system through the use of a computer. A simulator interprets the HDL description and produces
readable output, such as a timing diagram, that predicts how the hardware will behave before it is
actually fabricated, simulation allows the detection of functional errors in a design without having
to physically create the circuit. Errors that are detected during simulation can be created by
modifying the appropriate HDL statements.
Logic synthesis is the process of deriving a list of components and their interconnection
from the model of a digital system describing in HDL. The gate level net list can be used to
fabricate an integrated circuit. Logic synthesis is simulation to compiling a program in a
conventional high level language. Logic synthesis is based on formal exact procedures that
implement digital circuits and consists of that part of a digital design that can be automated with
computer software. In this project we used Xilinx ISE 10.1version for the synthesis purpose.
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4. 1.6 Organization of Thesis
To design and implement the linear convolution on FPGA kit requires some hardware modules.
This can be explained in chapter2.
The linear convolution. Basically what is convolution and brief explanation of
convolution can be explained in chapter3.
For implementing linear convolution FPGA kit used. The FPGA technology can be
explained in chapter4. For simulation and synthesis some software’s must be used.
4

5. CHAPTER 2
FPGA TECHNOLOGY
2.1 Introduction
Fixed-Logic Devices are the circuits in a fixed logic device are permanent, they perform one
function or set of functions - once manufactured, they cannot be changed. The time required to a
final manufacturing run can take from several months to more than a year, depending on the
complexity of the device. Programmable logic devices (PLDs) are standard that offer customers
a wide range of logic capacity, features, speed and these devices can be changed at any time to
perform any number of functions. During the design phase customers can change the circuitry as
often as they want until the design operates to their satisfaction.
SPLD (Simple PLD) is a programmable logic device that provides a small logic block
that can be programmed. The logic block typically contains a handful of macrocells, which have
multiple inputs and the ability to perform a limited amount of logic. Complex PLD consists of an
arrangement of multiple SPLD-like blocks on a single chip. These devices contain 10-1000
macrocells. Each macro cell is equivalent to around 20 gates support up to 200 I/O pins. CPLDs
provide logic capacity up to the equivalent of about 50 typical SPLD devices, but it is somewhat
difficult to extend these architectures to higher densities. For the very high logic capacity, a
different approach is needed that is FPGA (Field Programmable Gate Array).
FPGA is an integrated circuit that contains many identical logic cells that can be viewed
as standard components. Individual cells are interconnected by a matrix of wires and
programmable switches. Field programmable means that the FPGA’s function is defined by a
user’s program rather than by the manufacturer of the device or its function is defined by a
program written by someone other than the device manufacturer.
FPGA is fully programmable alternative to a customized chip. It is also called as
reconfigurable processing unit. FPGAs are great for more complex applications. It is a RAM-
based digital logic chip.
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6. 2.2 Structure of FPGA
A Field-programmable Gate Array(FPGA) is an integrated circuit designed to be configured by
the customer or designer after manufacturing—hence “field programmable".
Figure 2.1 Structure of FPGA.
The general structure of an FPGA is illustrated in above figure 2.1. The figure depicts the
essential elements of an FPGA organized as a 2-D array of cells. An FPGA consists of the
following main types of resources.
1. Rectangular array of configurable logic blocks (CLBs) capable of implementing a variety
of logic functions.
2. Wiring tracks to route signals between the cells.
3. Crossbar switches to connect horizontal and vertical wires, and
4. Input/Output pads for signal conditioning at the chip input and output pins.
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7. 2.2.1 Configurable Logic Blocks (CLBs)
A major consideration in the selection of logic blocks is generality. The logic blocks are
generally arranged in a 2-D array.
Each logic block in a FPGA typically has a small number of inputs and one output. A
number of FPGA products are on a market, featuring different types of logic blocks. The most
commonly used logic block is a lookup table(LUT), which contains storage cells that are used to
implement a small logic function. Each cell is capable of holding a single logic value, either 0 or
1. The stored value is produced as the output of the storage cell. LUTs of various sizes may be
created, where the size is defined by the number of inputs.
Figure 2.2 Circuit for a Two-input LUT.
The above figure 2.2 has two inputs, x1 and x2, and one output f. It is capable of implementing
any logic function of two variables. Because a two-variable truth table has four rows, this LUT
has four storage cells. One cell corresponds to the output value in each row of the truth table. The
input variables x1 and x2 are used as the select inputs of the three multiplexers, which depends
7

8. on the valuation of x1 and x2. Select the content of one of the four storage cells as the output of
the LUT.
2.2.2 Interconnects
The interconnection problem essentially consists of connection of two conductors together. All
internal connections are composed of metal segments with programmable switching points to
implement device routing. CLBs and I/Os are distributed on four sides of the blocks providing
additional routing flexibility.
These are three types. They are
1. Single length lines.
2. Double length lines.
3. Long lines.
1. Single length lines:
These are the grid of horizontal and vertical lines that intersects at a switch matrix between each
block. Its surrounds are CLBs in the array. Each switch matrix consists of programmable n-
channel pass transistors, used to establish the connection between the single length lines.
2. Double length lines:
These lines consist of a grid of metal segments twice as long as single length lines. These are
grouped in pair with the switch matrix.
3. Long lines:
The long lines form a grid of metal of interconnect segment that run the entire length or width of
the array.
2.2.3 Input/ Output Blocks
The input/output blocks provide the interface between external package pins and internal logic.
Each IOB controls are package pins and can be defined to I/O or bidirectional signals I/O are
programmable registers. Input signals are sent to the registers, output signals are passed directly
to the pad or be stored in an edge triggered flip-flop. Programmable pull up/pull down transistors
are useful for tying unwanted pins to Vcc and GND to minimize power consumption. Separate
input clock signals are provided for input and output registers.
8

9. 2.3 FPGA Flow
The basic implementation of design on FPGA has the following steps.
 Design Entry
 Logic Optimization
 Technology Mapping
 Placement
 Routing
 Programming Unit
 Configured FPGA
Above shows the basic steps involved in implementation. The initial design entry of may
be VHDL, schematic or Boolean expression. The optimization of the Boolean expression will be
carried out by considering area or speed.
In technology mapping, the transformation of optimized Boolean expression to FPGA
logic blocks, that is said to be as Slices. Here area and delay optimization will be taken place.
During placement the algorithms are used to place each block in FPGA array. Assigning the
FPGA wire segments, which are programmable, to establish connections among FPGA blocks
through routing. The configuration of final chip is made in programming unit.
2.4 Advantages
The following are the advantages of the FPGA technology.
 Reduced time to market.
 Lower non-recurring engineering costs.
 Reprogrammable.
9

10. 2.5 Applications
The following are the applications of the FPGA technology.
 FPGA can be applied to a very wide range of applications including: random logic,
integrating multiple SPLDs, device controllers, communication encoding and filtering,
small to medium sized with SRAM blocks.
 Prototyping of designs later to be implemented in gate arrays. Prototyping might be
possible using only a single large FPGA (which corresponds to a small gate array in
terms of capacity).
 Emulation of entire hardware systems.
2.6 Future Scope
In this the 4x4 convolution and the data width is 4 bits shown. The convolution can be
done for NXN and the width can be extended to N bits.
2.7 Conclusion
In this chapter the basics of FPGA, structure of FPGA, advantages and applications of FPGA
are illestrated. The convolution process is explained in the next chapter 3.
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11. CHAPTER 3
CONVOLUTION
3.1 Introduction
Convolution provides the mathematical framework for DSP. It is the single most important
technique in Digital Signal Processing. Convolution is a mathematical way of combining two
signals to form a third signal. Using the strategy of impulse decomposition, systems are
described by a signal called the impulse response. In signal processing, the impulse response, or
impulse response function (IRF), of a dynamic system is its output when presented with a brief
input signal, called an impulse. More generally, an impulse response refers to the reaction of any
dynamic system in response to some external change. It has applications that include statistics,
computer vision, image and signal processing, electrical engineering, and differential equations.
One of the most important concepts in Fourier theory, and in crystallography, is that of a
convolution.. Because of a mathematical property of the Fourier transform, referred to as the
convolution theorem, it is convenient to carry out calculations involving convolutions.
3.2 Convolution Definition
The convolution of ƒ and g is written ƒ∗g, using an asterisk or star. It is defined as the integral of
the product of the two functions after one is reversed and shifted. As such, it is a particular kind
of integral transform.
While the symbol t is used above, it need not represent the time domain. But in that context, the
convolution formula can be described as a weighted average of the function ƒ(τ) at the moment t
where the weighting is given by g(−τ) simply shifted by amount t. As t changes, the weighting
function emphasizes different parts of the input function.
11

12. More generally, if f and g are complex-valued functions on Rd, then their convolution
may be defined as the integral:
3.3 Convolution in Discrete Time
The idea of discrete-time convolution is exactly the same as that of continuous-time convolution.
For this reason, it may be useful to look at both versions to help your understanding of this
extremely important concept. Convolution is a very powerful tool in determining a system's
output from knowledge of an arbitrary input and the system's impulse response.
Any discrete-time signal can be represented by a summation of scaled and shifted discrete-time
impulses. Since the system to be linear and time-invariant, it would seem to reason that an input
signal comprised of the sum of scaled and shifted impulses would give rise to an output
comprised of a sum of scaled and shifted impulse responses. This is exactly what occurs in
convolution.
For discrete time signals x(n) and h(n), the convolution equation is given by
Graphical Interpretation
Reflection of h(k) resulting in h(-k)
Shifting of h(-k) resulting in h(n-k)
Element-wise multiplication of the sequences x(k) and h(n-k)
Summation of the product sequence x(k)h(n-k) resulting in the convolution value for
y(n)
12

13. Graphical illustration of convolution properties (Discrete - time)
A quick graphical example may help in demonstrating how convolution works.
Step1: A single impulse input yields the system's impulse response.
Step2: A scaled impulse input yields a scaled response, due to the scaling property of the
System’s linearity.
Step3: Now use the time-invariance property of the system to show that a delayed input results
in an output of the same shape, only delayed by the same amount as the input.
13

14. Step4: Now use the additively portion of the linearity property of the system to complete the
picture. Since any discrete-time signal is just a sum of scaled and shifted discrete-time impulses
and find the output from knowing the input and the impulse response
.3.4 Convolution in Continuous Time
In this module examines convolution for continuous time signals. This will result in the
convolution integral and its properties. These concepts are very important in Engineering and
will make any engineer's life a lot easier if the time is spent now to truly understand what is
going on.
14

15. Derivation of the convolution integral
To begin this, it is necessary to state the assumptions will be making. In this instance, the only
constraints on our system are that it be linear and time-invariant.
Brief Overview of Derivation Steps
1. An impulse input leads to an impulse response output.
2. A shifted impulse input leads to a shifted impulse response output. This is due to the time-
invariance of the system.
3. Now scale the impulse input to get a scaled impulse output. This is using the scalar
multiplication property of linearity.
4. Now "sum up" an infinite number of these scaled impulses to get a sum of an infinite
number of scaled impulse responses. This is using the additively attribute of linearity.
5. Now recognize that this infinite sum is nothing more than an integral, so convert both
sides into integrals.
6. Recognizing that the input is the function f(t), also recognize that the output is exactly the
convolution integral.
Step1: Begin with a system defined by its impulse response, h(t).
Step2: Then consider a shifted version of the input impulse. Due to the time invariance of the
system, obtain a shifted version of the output impulse response
15

16. Step3: Now use the scaling part of linearity by scaling the system by a value, f(τ), that is
constant with respect to the system variable, t.
.
Step4: Now use the additively aspect of linearity to add an infinite number of these, one for each
possible τ.
Since an infinite sum is exactly an integral, end up with the integration known as the
Convolution Integral. Using the sampling property, recognize the left-hand side simply as the
input f(t).
Convolution Integral
As mentioned above, the convolution integral provides an easy mathematical way to express the
output of an LTI system based on an arbitrary signal, x (t), and the system's impulse response,
h(t) . The convolution integral is expressed as
Convolution is such an important tool that it is represented by the symbol *, and can be written
as
y (t) = x(t) * h(t)
16

17. By making a simple change of variables into the convolution integral, τ = t−τ, can easily shows
that convolution is commutative:
x (t) * h(t) = h(t) * x(t)
Implementation of Convolution
Taking a closer look at the convolution integral, that multiplying the input signal by the time-
reversed impulse response and integrating. This will give us the value of the output at one given
value of t. If the shift time-reversed impulse response by a small amount and gets the output for
another value of t. Repeating this for every possible value of t, yields the total output function.
That are essentially reversing the impulse response function and sliding it across the input
function, integrating as go. This method, referred to as the graphical method, provides us with a
much simpler way to solve for the output for simple (contrived) signals, while improving our
intuition for the more complex cases where the rely on computers. In fact Texas Instruments
develops Digital Signal Processors which have special instruction sets for computations such as
convolution.
3.5 Symmetric Convolution
In mathematics, symmetric convolution is a special subset of convolution operations in which the
convolution kernel is symmetric across its zero point. Many common convolution-based
processes such as Gaussian blur and taking the derivative of a signal in frequency-space are
symmetric and this property can be exploited to make these convolutions easier to evaluate.
The convolution theorem states that a convolution in the real domain can be represented
as a point-wise multiplication across the frequency domain of a Fourier transform. Since sine and
cosine transforms are related transforms a modified version of the convolution theorem can be
applied, in which the concept of circular convolution is replaced with symmetric convolution.
Using these transforms to compute discrete symmetric convolutions is non-trivial since discrete
sine transforms (DSTs) and discrete cosine transforms (DCTs) can be counter-intuitively
incompatible for computing symmetric convolution, i.e. symmetric convolution can only be
computed between a fixed set of compatible transforms.
17

18. Advantages of Symmetric Convolution
There are a number of advantages to computing symmetric convolutions in DSTs and DCTs in
comparison with the more common circular convolution with the Fourier transform. Most
notably the implicit symmetry of the transforms involved is such that only data unable to be
inferred through symmetry is required. For instance using a DCT-II, a symmetric signal need
only have the positive half DCT-II transformed, since the frequency domain will implicitly
construct the mirrored data comprising the other half. This enables larger convolution kernels to
be used with the same cost as smaller kernels circularly convolved on the DFT. Also the
boundary conditions implicit in DSTs and DCTs create edge effects that are often more in
keeping with neighboring data than the periodic effects introduced by using the Fourier
transform.
3.6 Types of Convolution
There are two types of convolution. They are
 Linear convolution
 Circular convolution
3.6.1 Linear Convolution
Convolution is an integral concatenation of two signals. It has many applications in numerous
areas of signal processing. The convolution described above is nothing but linear convolution.
The most popular application is the determination of the output signal of a linear time-invariant
system by convolving the input signal with the impulse response of the system. Convolving two
signals is equivalent to multiplying the Fourier transform of the two signals.
MathematicalFormula
The linear convolution of two continuous time signals x(t) and h(t) is defined by
For discrete time signals x(n) and h(n) , the integration is replaced by a summation
18

19. 3.6.2 Circular Convolution
The circular convolution of two aperiodic functions occurs when one of them is convolved in the
normal way with a periodic summation of the other function. It occurs naturally in digital signal
processing when DTFTs and inverse DTFTs are replaced by DFTs and inverse DFTs.
Equivalently, the continuous frequency domain is replaced by a discrete one. (See Circular
convolution theorem.)
For a periodic function xT(t) , with period T, the convolution with another function, h(t), is also
periodic, and can be expressed in terms of integration over a finite interval as follows:
]
Where, to is an arbitrary parameter, and hT(t) is a periodic summation of h, defined by:
When xT(t) is expressed as the periodic summation of another function, x, this convolution is
sometimes referred to as a circular convolution of functions h and x.
3.7 Properties of Convolution
This section describes the properties of convolution. The properties of convolution are
 Commutative
 Associative
 Distributive
19

20. 3.7.1 Commutative Property
The commutative property for convolution is expressed in mathematical form
a[n] * b[n] = b[n] * a[n]
In words, the order in which two signals are convolved makes no difference, the results are
identical.
3.7.2 Associative Property
The associative property describes the way to convolve more than two signals. Convolve two of
the signals to produce an intermediate signal, then convolve the intermediate signal with the third
signal. The associative property provides that the order of the convolutions doesn't matter. As an
equation:
(a[n] * b[n] ) * c[n] = a[n] * ( b[n] * c[n] )
The associative property is used in system theory to describe how cascaded systems behave. Two
or more systems are said to be in a cascade if the output of one system is used as the input for the
next system. From the associative property, the order of the systems can be rearranged without
changing the overall response of the cascade. Further, any number of cascaded systems can be
replaced with a single system. The impulse response of the replacement system is found by
convolving the impulse responses of all of the original systems.
3.7.3 Distributive Property
In equation form, the distributive property is written as:
a[n] * b[n] + a[n] * c[n] = a[n] * (b[n] + c [n] )
The distributive property describes the operation of parallel systems with added outputs. Two or
more systems can share the same input, x[n] , and have their outputs added to produce y[n] . The
distributive property allows this combination of systems to be replaced with a single system,
having an impulse response equal to the sum of the impulse responses of the original systems.
20

21. 3.8 Convolution in Time Domain
When two signals convolution is carried out in time domain it is referred to as convolution in
time domain. In time domain also the convolution can be continuous or discrete. When the
convolution is in time domain is discrete then it is called as convolution in discrete time and
when the convolution is performed with respect to continuous time it is called as convolution as
convolution in continuous time. Convolution in discrete and continuous time is described in
previous chapter.
3.9 Convolution in Frequency Domain
When two signals are convolved in frequency domain then it is called as convolution in
frequency domain. It is proved that the convolution in time domain is equivalent to
multiplication in frequency domain.
Proof:
Let f, g belong to L1 (Rn). Let F be the Fourier transform of f and G be the Fourier transform of g:
Where the dot between x and ν indicates the inner product of Rn . Let h be the convolution of f
and g
Now notice that
Hence by Fubini's theorem we have that so its Fourier transform H is defined by
the integral formula
21

22. Observe that and hence by the argument
above may apply Fubini's theorem again:
Substitute y = z − x; then dy = dz, so:
These two integrals are the definitions of F(ν) and G(ν), so:
Hence, it is proved that the convolution in time domain is equivalent to multiplication in
frequency domain.
3.10 Applications of Convolution
Convolution and related operations are found in many applications of engineering and
mathematics. The following are the areas where convolution is being applied.
In statistics, as noted above, a weighted moving average is a convolution.
In probability theory, the probability distribution of the sum of two independent random
variables is the convolution of their individual distributions.
In optics, many kinds of "blur" are described by convolutions. A shadow (e.g. the shadow on
the table when you hold your hand between the table and a light source) is the convolution of
the shape of the light source that is casting the shadow and the object whose shadow is being
cast. An out-of-focus photograph is the convolution of the sharp image with the shape of the
iris diaphragm.
Similarly, in digital image processing, convolutional filtering plays an important role in many
important algorithms in edge detection and related processes.
In linear acoustics, an echo is the convolution of the original sound with a function
representing the various objects that are reflecting it.
22

23. In artificial reverberation (digital signal processing, pro audio), convolution is used to map
the impulse response of a real room on a digital audio signal (see previous and next point for
additional information).
In electrical engineering and other disciplines, the output (response) of a (stationary, or time-
or space-invariant) linear system is the convolution of the input (excitation) with the system's
response to an impulse or Dirac delta function. See LTI system theory and digital signal
processing.
In time-resolved fluorescence spectroscopy, the excitation signal can be treated as a chain of
delta pulses, and the measured fluorescence is a sum of exponential decays from each delta
pulse.
In physics, wherever there is a linear system with a "superposition principle", a convolution
operation makes an appearance.
In digital signal processing, frequency filtering can be simplified by convolving two
functions (data with a filter) in the time domain, which is analogous to multiplying the data
with a filter in the frequency domain
3.11 Conclusion
In this chapter how two signals are combined to form a resultant signal by using mathematical
formulaes. Applications of convolution are discussed in this chapter. This convolution is
implemented in FPGA kit. The convolution on FPGA is discussed in chpter4.
23

24. CHAPTER 4
HARDWARE COMPONENTS
4.1 Introduction
For implementing and design of linear convolution on FPGA kit require some hardware
modules. Those modules are two 4x1 multiplexers, two SIPO’s, one binary multiplier, one 8x1
multiplexer and register. In this report the implementation is carried out by first designed the
individual blocks and then these are combined to the final architecture. The individual blocks are
shown in block diagram given below.
4.2 Block Diagram
The block diagram of the proposed architecture is shown below.
Figure 4.1 Block Diagram
24

25. 4.3 Multiplexers 4x1 and 8x1
A multiplexer, sometimes referred to as a "multiplexor" or simply "mux", is a device that selects
between a number of input signals. In its simplest form, a multiplexer will have two signal
inputs, one control input, and one output.
A multiplexer is a device which selects any one of the inputs from 2n inputs and directed
to output depending on n-select lines. 4x1 multiplexer having two selection lines. Depending
upon the selection lines the output comes.
Figure 4.2 4x1 Multiplexer
Similarly, 8x1 multiplexer having three selection lines. Depending upon the selection
lines gets the output. The higher order multiplexers can be implemented using the lower order
multiplexers. The 4x1 multiplexer can be implemented using two 2x1 multiplexers and so on.
Similarly an 8x1 multiplexer can be implemented using two 4x1 multiplexers.
Figure 4.3 8x1 Multiplexer
25

26. 4.4 Serial In Parallel Out Block (SIPO)
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it
shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is
different in that it makes all the internal stages available as outputs. Therefore, a serial-
in/parallel-out shift register converts data from serial format to parallel format. If four data bits
are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available
simultaneously on the four Outputs QA to QD after the fourth clock pulse.
Figure 4.4 Serial Input Parallel Output
.
The practical application of the serial-in/parallel-out shift register is to convert data from serial
format on a single wire to parallel format on multiple wires.
26

27. Perhaps, illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC
QD ).
Figure 4.5 Serial-in/ Parallel-out Shift Register
The above details of the serial-in/parallel-out shift register are fairly simple. It looks like
a serial-in/ serial-out shift register with taps added to each stage output. Serial data shifts in at SI
(Serial Input). After a number of clocks equal to the number of stages, the first data bit in appears
at SO (QD) in the above figure. In general, there is no SO pin. The last stage (QD above) serves as
SO and is cascaded to the next package if it exists.
Figure 4.6 Serial-in/ Parallel-out Waveforms
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28. The shift register has been cleared prior to any data by CLR', an active low signal, which
clears all type D Flip-Flops within the shift register. Note the serial data 1011 pattern presented
at the SI input. This data is synchronized with the clock CLK. This would be the case if it is
being shifted in from something like another shift register, for example, a parallel-in/ serial-out
shift register. On the first clock at t1, the data 1 at SI is shifted from D to Q of the first shift
register stage. After t2 this first data bit is at QB. After t3 it is at QC. After t4 it is at QD.
Four clock pulses have shifted the first data bit all the way to the last stage QD. The
second data bit a 0 is at QC after the 4th clock. The third data bit a 1 is at QB. The fourth data bit
another 1 is at QA. Thus, the serial data input pattern 1011 is contained in (QD QC QB QA). It is
now available on the four outputs. It will available on the four outputs from just after clock t4 to
just before t5. This parallel data must be used or stored between these two times, or it will be lost
due to shifting out the QD stage on following clocks t5 to t8 as shown above.
4.5 Binary Multiplier
The binary multiplier used here is a 4-bit multiplier which takes two four bit inputs and
gives an 8-bit output.
Figure 4.7 Binary Multiplier
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29. The binary multiplier which is employed in convolution has a special characteristic that
the internal carry will not be forwarded to next stage. So the number of outputs obtained here is
seven only because in binary multiplier the MSB part is nothing but the carry obtained from the
second MSB so as carry is not forwarded only seven bits will be obtained as output.
4.6 Register
A circuit with flip-flops is considered a sequential circuit even in the absence of Combinational
logic. Circuits that include flip-flops are usually classified by the function they perform. Two
such circuits are registers and counters.
A Register is a group of flip-flops. Its basic function is to hold information within a
digital system so as to make it available to the logic units during the computing process.
However, a register may also have additional capabilities associated with it. It may have
combinational gates that perform certain data-processing tasks.
Figure 4.8 A 8-bit Register
Various types of registers are available on the market. A simple 4-bit register is shown
below. The common clock input triggers all flip-flops and the binary data available at the four
inputs are transferred into the register. The clear input is useful for clearing the register to all
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30. 0’s output. Registers capable of shifting their binary contents in one or both directions. A
unidirectional 4-bit shift register that uses only flip-flops is as follows.
Figure 4.9 Shift Register
4.7 Conclusion
In this chapter a description of the modules interconnected in FPGA is given. These modules
typically are use to implement the linear convolution. The implementation of convolution on
FPGA is shown in this chapter.
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31. CHAPTER 5
CONCLUSION
5.1 Conclusion
In this chapter an optimized implementation of convolution. This particular model has the
advantage of being fine tuned for signal processing, this implementation has the advantage of
being optimized based on operation, power and area. To accurately analyze the proposed system,
coded the design using the verilog hardware description language and have synthesized using
Xilinx.
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32. REFERENCES
Implementation of Data Convolution Algorithms in FPGAs
- Thomas Oelsner
Low-cost Fast VLSI Algorithm For Discrete Fourier Transform
- Chao Cheng
Handbook for Real-Time Fast Fourier Transforms
- W. W. Smith
- J. M. Smith
Websites:
www.google.com
www.wikepedia.com
www.atmel.com
www.howstuffworks.com
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