This document provides a summary of Kumar Chandan and Mayank Kumar's summer internship report on RTL design, Verilog, and FPGA programming at Tevatron Technology in Noida, India. It includes an acknowledgements section thanking their mentor and institution for supporting the project. The abstract indicates that the main objective was to study digital circuit behavior and design using Xilinx software. An introduction is provided on topics like VLSI, HDLs, Verilog, modeling styles in Verilog, and system tasks.

1. RTL DESIGN ,VERILOG AND FPGA
PROGRAMMING
(FROM TEVATRONTECHNOLOGY)
A SUMMER INTERN REPORT
Submitted by
KUMAR CHANDAN(00814802813)
MAYANK KUMAR(00614802813)
in partial fulfillment of summer internship for award of the degree
of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
MAHARAJA AGRASEN INSTITUTE OF TECHNOLOGY
GURU GOVIND SINGH INDRAPRASATHA UNIVERSITY, DELHI
2013- 2017

2. To whom it may concern
We, Kumar Chandan, Mayank KumarEnrollment no.-00814802813, 00514802813
respectively, from student of bachelor of technology (ECE), a batch of 2013-2017, Maharaja
AgrasenInstitute of Technology Delhi, here by declared that the summer intern entitles RTL
Design ,Verilog AND FPGA ProgrammingatTevatronTechnology,Noida sec-3 is an
original work and the same has not been submitted for the award of any other degree.

3. ACKNOWLEDGEMENT
We have immense pleasure in successful completion of this work titled:
RTL DESIGN ,VERILOG AND FPGA PROGRAMMING
The special environment at TEVATRON TECHNOLOGY, NOIDA SEC-3that always
supports educational activities, facilitated our work on this summer training.
We greatly appreciate the motivation and understanding extended for the project work, by,
Mr.UjjawalKaushik who responded promptly and enthusiastically to our requests for frank
comments, despite their congested schedules. We are indebted to all of them, who did their
best to bring improvements through their suggestions.
We are also thankful to our college’ Maharaja Agrasen Institute of
Technology, who directly or indirectly have been helpful in some or the other way.
We thank our Dearest Parents, who encouraged me to extend our reach. With their
help and support, We have been able to complete this work

4. ABSTRACT
Since we have a keen interest in knowing new things especially related to the area of VLSI.
We selected a topic related to the area of this field.
As we want to enhance our career from the VLSI design which is also our core subject, the
research made by us to complete this project will prove to be very helpful.
The main objective of our project on the topic “RTL DESIGN , VERILOG AND FPGA
programming” is to study the depth knowledge about the behaviour and designing of
different digital circuits. With the use of XILINX software, designing of practical electronic
devices has become much easier than before.
So, we would like to clearly mention that, our project purely involves the basic concepts of
RTL Design and their designing using XILINX .

5. INTRODUCTION
VLSI
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were being developed. The
microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a
limited set of functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
Developments:
The first semiconductor chips held two transistors each. Subsequent advances added more
transistors, and as a consequence, more individual functions or systems were integrated over
time. The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on
a single device. Now known retrospectively as small-scale integration (SSI), improvements in
technique led to devices with hundreds of logic gates, known as medium-scale integration
(MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a
thousand logic gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration
above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number
of gates and transistors available on common devices has rendered such fine distinctions
moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread
use.
As of early 2008, billion-transistor processors are commercially available. This became more
commonplace as semiconductor fabrication advanced from the then-current generation of 65
nm processes. Current designs, unlike the earliest devices, use extensive design automation
and automated logic synthesis to lay out the transistors, enabling higher levels of complexity
in the resulting logic functionality. Certain high-performance logic blocks like the SRAM
(static random-access memory) cell, are still designed by hand to ensure the highest
efficiency.

6. HDL (hardware description language)
In electronics, a hardware description language (HDL) is a specialized computer language
used to program the structure, design and operation of electronic circuits, and most
commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit
that allows for the automated analysis, simulation, and simulated testing of an electronic
circuit. It also allows for the compilation of an HDL program into a lower level specification
of physical electronic components, such as the set of masks used to create an integrated
circuit.
A hardware description language looks much like a programming language such as C; it is a
textual description consisting of expressions, statements and control structures. One
important difference between most programming languages and HDLs is that HDLs
explicitly include the notion of time. HDLs form an integral part of electronic design
automation (EDA) systems, especially for complex circuits, such as microprocessors.

7. VERILOG
INTRODUCTION
Verilog is a Hardware Description Language; a textual format for describing electronic
circuits and systems. Applied to electronic design, Verilog is intended to be used for
verification through simulation, for timing analysis, for test analysis (testability analysis and
fault grading) and for logic synthesis.
The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard
for Verilog was published in 1995. A revised version was published in 2001; this is the
version used by most Verilog users. The IEEE Verilog standard document is known as the
Language Reference Manual, or LRM. This is the complete authoritative definition of the
Verilog HDL.
A further revision of the Verilog standard was published in 2005, though it has little extra
compared to the 2001 standard. System Verilog is a huge set of extensions to Verilog, and
was first published as an IEEE standard in 2005. See the appropriate Knowhow section for
more details about System Verilog.
IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection
of software routines which permit a bidirectional interface between Verilog and other
languages (usually C).
Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two
different HDLs. They have more similarities than differences, however.
Verilog was started initially as a proprietary hardware modeling language by Gateway Design
Automation Inc. around 1984. It is rumored that the original language was designed by taking
features from the most popular HDL language of the time, called Hilo, as well as from
traditional computer languages such as C. At that time, Verilog was not standardized and the
language modified itself in almost all the revisions that came out within 1984 to 1990.Verilog
simulator was first used beginning in 1985 and was extended substantially through 1987. The
implementation was the Verilog simulator sold by Gateway. The first major extension was
Verilog-XL, which added a few features and implemented the infamous "XL algorithm"
which was a very efficient method for doing gate-level simulation .The time was late 1990.
Cadence Design System, whose primary product at that time included thin film process
simulator, decided to acquire Gateway Automation System. Along with other Gateway
products, Cadence now became the owner of the Verilog language, and continued to market

8. Verilog as both a language and a simulator. At the same time, Synopsys was marketing the
top-down design methodology, using Verilog. This was a powerful combination.
VHDL/Verilog compared & contrasted
This section compares and contrasts individual aspects of the two languages; they
are listed in alphabetical order.
Capability
Hardware structure can be modeled equally effectively in both VHDL and Verilog.
When modeling abstract hardware, the capability of VHDL can sometimes only be
achieved in Verilog when using the PLI. The choice of which to use is not
therefore based solely on technical capability but on:
 personal preferences
 EDA tool availability
 commercial, business and marketing issues
The modeling constructs of VHDL and Verilog cover a slightly different spectrum
across the levels of behavioral abstraction; see Figure 1.
Figure 1. HDL modeling capability
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same
system file, may be separately compiled if so desired. However, it is good design
practice to keep each design unit in it's own system file in which case separate
compilation should not be an issue.
Verilog. The Verilog language is still rooted in it's native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the original

9. nature of the language. As a result care must be taken with both the compilation
order of code written in a single file and the compilation order of multiple files.
Simulation results can change by simply changing the order of compilation.
Data types
VHDL. A multitude of language or user defined data types can be used. This may
m ean dedicated conversion functions are needed to convert objects from one type
to another. The choice of which data types to use should be considered wisely,
especially enumerated (abstract) data types. This will make models easier to write,
clearer to read and avoid unnecessary conversion functions that can clutter the
code. VHDL may be preferred because it allows a multitude of language or user
defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and
very much geared towards modeling hardware structure as opposed to abstract
hardware modeling. Unlike VHDL, all data types used in a Verilog model are
defined by the Verilog language and not by the user. There are net data types, for
example wire, and a register data type called reg. A model with a signal whose
type is one of the net data types has a corresponding electrical wire in the implied
modeled circuit. Objects, that is signals, of type reg hold their value over
simulation delta cycles and should not be confused with the modeling of a
hardware register. Verilog may be preferred because of it's simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail
able to any design-unit that wishes to use them.
Verilog. There is no concept of packages in Verilog. Functions and procedures
used within a model must be defined in the module. To make functions and
procedures generally accessible from different module statements the functions and
procedures must be placed in a separate system file and included using the `include
compiler directive.
Easiest to Learn
Starting with zero knowledge of either language, Verilog is probably the easiest to
grasp and understand. This assumes the Verilog compiler directive language for
simulation and the PLI language is not included. If these languages are included
they can be looked upon as two additional languages that need to be learned.
VHDL may seem less intuitive at first for two primary reasons. First, it is very
strongly typed; a feature that makes it robust and powerful for the advanced user
after a longer learning phase. Second, there are many ways to model the same
circuit, specially those with large hierarchical structures.

10. Modeling Styles in Verilog HDL -
Modeling Style means, that how we Design our Digital IC's in Electronics. With the help of
modeling style we describe the Design of our Electronics.
Normally we use Three type of Modeling Style in Verilog HDL -
1. Data Flow Modeling Style.
2. Gate Modeling Style.
3. Behavior Modeling Style.
1. Data Flow Modeling Style - Data Flow Modeling Style Shows that how the data /
signal flows from input toouput threw the registers / Components. Data Flow Modeling Style
works on Concurrent Execution.
2. Gate Modeling Style :
Gate Modeling Style shows the Graphical Representation of modules/ instances /
components with their Interconnection. In Gate Modeling Style We defines that how our
Components / Registers / Modules are Connected to each other using Nets/ Wires. Gatel
Modeling Style works on Concurrent Execution.
3.Behavior Modeling Style -
Behavior Modeling Style shows that how our system performs according to current input
values.
In behavorModeling, we defines that what value we get at the output corresponding to input
values.
We Defines the function / Behavior of our Digital Systems in Behavior Modeling Style.
Behavior Modeling Style works on Sequential Execution.

11. System task:
There are tasks and functions that are used to generate input and output during simulation.
Their names begin with a dollar sign ($). The synthesis tools parse and ignore system
functions, and hence can be included even in synthesizable models.

12. FORK JOIN
The fork...join construct enables the creation of concurrent processes from each of its parallel
statements. SyntemVerilog provides following version's of fork-join.fork -join is same as one
in Verilog. i.e. is join all. fork - join_none, does not wait for any forked process is complete
and thus starts execution statements after the join_none statement without waiting for forked
process.

13. serial input serial output register (SISO)
Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store
a bit of data for each register. A serial-in, serial-out shift register may be one to 64 bits in
length, longer if registers or packages are cascade.

15. Priority Encoder
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a
smaller number of outputs. The output of a priority encoder is the binary representation of the
original number starting from zero of the most significant input bit. They are often used to
control interrupt requests by acting on the highest priority encoder.

16. Dual port ram
Dual-ported RAM (DPRAM) is a type of random-access memory that allows multiple
reads or writes to occur at the same time, or nearly the same time, unlike single-ported
RAM which only allows one access at a time.Video RAM or VRAM is a common
form of dual-ported dynamic RAM mostly used for video memory, allowing the CPU
to draw the image at the same time the video hardware is reading it out to the
screen.Apart from VRAM, most other types of dual-ported RAM are based on static
RAM technology.Most CPUs implement the processor registers as a small dual-ported
or multi-ported RAM.

17. dualportram
data_in(7:0) data_out(7:0)
rd_addr(3:0)
wr_addr(3:0)
clk
we
rd
rst

18. SERIAL IN PARRALEL OUT REGISTER
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it
shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It
is different in that it makes all the internal stages available as outputs. Therefore, a serial-
in/parallel-out shift register converts data from serial format to parallel format. If four data
bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes
available simultaneously on the four Outputs QA to QD after the fourth clock pulse.

20. MULTIPLEXER
In electronics, a multiplexer (or mux) is a device that selects one of
several analog or digital input signals and forwards the selected input into a single line.[1] A
multiplexer of 2n inputs has n select lines, which are used to select which input line to send to
the output. Multiplexers are mainly used to increase the amount of data that can be sent over
the network within a certain amount of time and bandwidth. A multiplexer is also called
a data selector. Multiplexers can also be used to implement Boolean functions of multiple
variables.

21. What is an FPGA?
Field Programmable Gate Array (FPGA)
FPGAs are programmable semiconductor devices that are based around a matrix of
Configurable Logic Blocks (CLBs) connected through programmable interconnects. As
opposed to Application Specific Integrated Circuits (ASICs), where the device is custom built
for the particular design, FPGAs can be programmed to the desired application or
functionality requirements. Although One-Time Programmable (OTP) FPGAs are available,
the dominant type are SRAM-based which can be reprogrammed as the design evolves.
FPGAs allow designers to change their designs very late in the design cycle– even after the
end product has been manufactured and deployed in the field. In addition, Xilinx FPGAs
allow for field upgrades to be completed remotely, eliminating the costs associated with re-
designing or manually updating electronic systems.
Fig. 10.1 FPGA block structure

22. FPGA Applications
Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the
industry leader, Xilinx provides comprehensive solutions consisting of FPGA devices,
advanced software, and configurable, ready-to-use IP cores for market and applications such
as:
By Market By Technology
Aerospace and Defense Industrial Audio
Automotive Medical Security
Broadcast Wireless Communications Video and Imaging
Consumer Electronics Wired Communications
High Performance Computing
FPGA vs. ASIC
What is the Difference between a FPGAand an ASIC?
Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits
(ASICs) provide different values to designers, and they must be carefully evaluated before
choosing any one over the other. Information abounds that compares the two technologies.
While FPGAs used to be selected for lower speed/complexity/volume designs in the past,
today’s FPGAs easily push the 500MHz performance barrier. With unprecedented logic
density increases and a host of other features, such as embedded processors, DSP blocks,
clocking, and high-speed serial at ever lower price points, FPGAs are a compelling
proposition for almost any type of design.

23. FPGA vs. ASIC Design Advantages
FPGA Design
Advantage Benefit
Faster time-to-market No layout, masks or other manufacturing steps are
needed
No upfront non-recurring expenses
(NRE)
Costs typically associated with an ASIC design
Simpler design cycle Due to software that handles much of the routing,
placement, and timing
More predictable project cycle Due to elimination of potential re-spins, wafer capacities,
etc.
Field reprogramability A new bitstream can be uploaded remotely
ASIC Design
Advantage Benefit
Full custom capability For design since device is manufactured to design specs
Lower unit costs For very high volume designs
Smaller form factor Since device is manufactured to design specs
FPGA vs. ASIC Design Flow
The FPGA design flow eliminates the complex and time-consuming floor planning, place and
route, timing analysis, and mask / re-spin stages of the project since the design logic is
already synthesized to be placed onto an already verified, characterized FPGA device.

24. Conclusion
On doing this internship on RTL design ,Verilog and FPGA pogramming , we came across
many interesting facts and figures about electronic circuits. While doing simulation of these
digital circuits, we came across the importance of software analysis of circuit before start
using components to construct our required devices. If we construct our devices before doing
software analysis, it would be cumbersome and tough for us to use accurately measured
devices.

25. References
Books
Verilog HDL : A guide to digital design and synthesis. By Samir Plantikar
Websites
Wikipedia for detailed knowledge of characteristics, advantage, disadvantages of various
electronic devices.
.http://www.xilinx.com/
http://verilogbynaresh.blogspot.in