3. DECLARATION
We certify that
a. the work contained in this report is original and has been done by me under the
guidance of my supervisor(s).
b. the work has not been submitted to any other Institute for any degree or diploma.
c. I have followed the guidelines provided by the Institute in preparing the report.
d. I have conformed to the norms and guidelines given in the Ethical Code of Conduct
of the Institute.
e. whenever I have used materials (data, theoretical analysis, figures, and text) from
other sources, I have given due credit to them by citing them in the text of the report
and giving their details in the references. Further, I have taken permission from the
copyright owners of the sources, whenever necessary. Signature of the Student
Signature of the Student
……………………………….
……………………………….
……………………………….
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4. ACKNOWLEDGEMENT
It gives us immense pleasure to express our heartfelt gratitude and sincere thanks to our
project mentor Shri. Manoj Kumar (Assistant Professor, Electronics And Communication
Engineering) for his timeless and valuable contribution, suggestion and encouragement for
the completion of this project. His continuous guidance had led us to execute our project
titled “DESIGN AND IMPLEMENTATION OF 32-BIT ALU USING VERILOG”.
We are deeply indebted to you Sir.
A. ATHIHRII(12UEC001)
M. STEPHEN (12UEC016)
SANJAY KUMAR(12UEC020)
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5. ABSTRACT
In this fast growing booming technology, the need for high-tech and superfast technology is
on high demand. Hence through the use of FPGA (Field Programmable Gate Array) we can
design superfast technology especially in the field of embedded system.
Verilog standardized as IEEE 1364 is a hardware description language(HDL), a textual
format for describing electronics design and circuits. Applied to electronic design, verilog is
intended to used for verification through simulation, for timing analysis, for test analysis
(testability analysis and fault grading) and for logic synthesis.
An Arithmetic Logic Unit (ALU) is a digital electronic circuits that performs arithmetic and
bitwise logical operations on integer binary numbers. This is in contrast to FPU(Floating
point unit )which operates on floating point numbers. ALU is a fundamental building block of
many type of computing circuits including the central processing unit (CPU), FPU and GPU
(Graphics Processing Unit).A single CP, FPU and GPU may contain multiple ALUs.
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6. CONTENTS
TITLE Page NO.
Title page i
Certificate iii
Certificate iv
Declaration v
Acknowledgement vi
Abstract vii
Contents viii
List of Figures xi
List of table xii
CHAPTER-1 INTRODUCTION AND LITERATURE REVIEW 1 - 5
1.1 HDL (Hardware Description language) 1
1.2 Typical Design Flow 3
1.3 Literature review 4
CHAPTER-2 INTRODUCTION TO VERILOG AND XILINX 6 - 10
2.1 Verilog 6
2.2 Xilinx 8
2.2.1 Procedure to Operate Xilinx (ISE 14.7) 9
2.3 Tools and Enviroment Used 10
2.3.1 Minimum Hardware Requirement 10
2.3.2 Minimum Software Requirement 10
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7. CHAPTER-3 DESIGN OF ALU 11-19
3.1 Arithmetic Unit 11
3.2 Logic Unit 14
3.3 Shift unit 15
3.3.1 Left Shift 15
3.3.2 Right Shift 16
3.4 Arithmetic Logic Unit 17
CHAPTER-4 VERILOG CODING AND WAVEFORM 20 – 47
4.1 Selection MUX 4 to 1 (1 bit I/O) 20
4.2 Selection MUX 4 to 1 (32-bit I/O) 21
4.3 Selection MUX 2 to 1 (32-bit I/O) 21
4.4 Full adder 22
4.5 4-bit Adder 22
4.6 32-bit Adder 23
4.7 32-bit AND 23
4.8 32-bit OR 23
4.9 32-bit XOR 24
4.10 32-bit NOT 24
4.11 Right shift 24
4.12 Left shift 25
4.13 Shift unit 25
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8. 4.14 Arithmetic unit 26
4.15 Logic unit 30
4.16 32-bit ALU 32
4.17 Test Bench for 32-bit ALU 40
CHAPTER-5 ADVANTAGE AND CONCLUSION 48 - 52
5.1 Importance of HDL 48
5.2 Advantage of Verilog HDL 48
5.3 Conclusion 49
5.4 Future scope of Verilog 50
5.4.1 Design process 50
5.4.2 System Level 51
5.4.3 Digital 51
5.4.4 Analog 51
5.4.5 Debugging 52
REFERENCES 53
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9. LIST OF FIGURES
1.1 TYPICAL DESIGN FLOW 3
2.2 Xilinx ISE Interface 9
3.1 32-bit Arithmetic unit 13
3.2 32-bit Logic unit 14
3.3.1 (a) 32-bit before Left Shift 15
(b) 32-bit after Left Shift 16
3.3.2 (a) 32-bit before Right Shift 16
(b) 32-bit after Right 16
3.3.3 32-bit Shift unit 17
3.4 Arithmetic Logic Unit 19
4.1 RTL of 32-bit ALU 44
4.2 4 to 1 32-bit Waveform 45
4.3 32-bit Arithmetic Unit Waveform 45
4.4 32-bit Logic Unit waveform 46
4.5 32-bit Shift unit Waveform 46
4.6 32-bit Arithmetic Logic unit Waveform 47
5.4.1 Design process 50
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10. LIST OF TABLE
Table 1. Table of 32-bit Arithmetic unit 12
Table 2. Table of 32-bit Logic uni 15
Table 3. Table of 32-bit Shift unit 17
Table 4. Table of 32-bit Arithmetic Logic unit 19
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11. This is to certify that the dissertation entitled
“Design and Implementation of 32-bit ALU using Verilog”
to the National Institute of Technology Manipur, India, is a record of
bonafied project work carried out under my supervision and guidance and is
worthy of consideration for the award of the degree of Bachelor of
Technology in Electronics and Communication Engineering of the Institute.
Signature of Guide
(Shri.Manoj Kumar)
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12. Department of Electronics and Communication Engineering
Takyelpat, Imphal- 795001, Ph.:0385-2445812, email:
Ref no.: NITMN/ECE:4/B.TECH/ ...... Dated.........
This is to certify that the Dissertation Report entitled,
submitted by Mr.“A.Athihrii,
M. Stephen, Sanjay Kumar” to National Institute of Technology Manpur,
India, is a record of bonafide Project work carried out by them under the
supervision and guidance of Shri. Manoj Kumar (Assistant Professor, NIT
Manipur) and is worthy of consideration for the award of the degree of Bachelor
of Technology in Electronics and Communication Engineering of the Institute.
HOD, ECE Department
NIT MANIPUR
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