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Module 5: Digital Techniques and
Electronic Instrument Systems
5.8 Integrated Circuits
An example of an digital integrated circuit
Half Adder
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adder
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Parallel Adder
 Can be extended
to add more bits.
Subtraction
Flip-Flops
 R-S Flip-Flops
 D Flip-Flops
 J-K Flip-Flops
 Temporary data storage.
 Counters.
 Multiplication and division.
R-S Flip-Flop
S R Q Q΄ Condition
0 0 * *
Latched (keeps
previous condition)
0 1 0 1 Reset
1 0 1 0 Set
1 1 ? ? Jammed
* previous condition
R-S Flip Flop design
 S: 1, R: 0  NAND 1
Q = 1 and Q΄= 0.
 S: 0, R: 1  NAND 2 
Q΄ = 1 and Q = 1.
 S: 0, R: 0  previous Q and
Q΄affect next Q and Q΄.
S R Q Q΄ Condition
0 0 * * Latched (keeps previous condition)
0 1 0 1 Reset
1 0 1 0 Set
1 1 ? ? Jammed
D Flip-Flop
 Changes are made only when clock moves from low
to high.
 Also called “delay flip-flop”.
Clk D
Qn
ext
Q΄ Condition
1 1 1 0 Store 1
0 X * * No change
1 0 0 1 Store 0
• *: previous condition
• X: irrelevant
J-K Flip Flop
Clk J K Q Q΄
1 0 0 * *
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle Toggle
QKQJQnext
• *: previous condition
Asynchronous Counter
 Ripple Counter.
 The output of each J-K flip flop is connected to the clock of the next one.
 Is an asynchronous counter. Events occur one after the other. However, high
speed clocks can cause erroneous indications. .
Synchronous counter
 Synchronous
counter: All
events occur at
the same time.
Ring Counter
 Only one output is
high each time.
 AND gates set
only one flip-flop
each time.
Parallel Register
 READ IN: flip-flops
can be set only
when Read-in is
“1”.
 READ OUT:
output is obtained
only when Read-
out is “1”.
 If Read-in and
Read-out is “0”
S=R=0 and flip-
flops keep their
previous condition.
Serial to Parallel Shift Register
 Data in bits shift right each time the clock ticks.
 Useful for implementing:
 serial to parallel data transfer
 division
Parallel to Serial Shift Register
 Input: D1- D4.
 When shift operation is set, each time the clock ticks
data are forwarded to the output.
Decoder
 Detect a specific bit combination.
 Each Y becomes “1”,
only when a specific
input combination is
applied.
Binary to decimal decoder
 A 3-bit binary to
decimal decoder
(from 0 to 7).
 Only one output can
be high each time.
Encoder
 Accepts an input and converts
it to a shorter representation
(e.g. binary).
 Decimal to binary converter
from 1 to 9.
Logic Families
74F04PC

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5.8 Integrated circuits

  • 1. Module 5: Digital Techniques and Electronic Instrument Systems 5.8 Integrated Circuits
  • 2. An example of an digital integrated circuit
  • 3. Half Adder A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
  • 4. Full Adder A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
  • 5. Parallel Adder  Can be extended to add more bits.
  • 7. Flip-Flops  R-S Flip-Flops  D Flip-Flops  J-K Flip-Flops  Temporary data storage.  Counters.  Multiplication and division.
  • 8. R-S Flip-Flop S R Q Q΄ Condition 0 0 * * Latched (keeps previous condition) 0 1 0 1 Reset 1 0 1 0 Set 1 1 ? ? Jammed * previous condition
  • 9. R-S Flip Flop design  S: 1, R: 0  NAND 1 Q = 1 and Q΄= 0.  S: 0, R: 1  NAND 2  Q΄ = 1 and Q = 1.  S: 0, R: 0  previous Q and Q΄affect next Q and Q΄. S R Q Q΄ Condition 0 0 * * Latched (keeps previous condition) 0 1 0 1 Reset 1 0 1 0 Set 1 1 ? ? Jammed
  • 10. D Flip-Flop  Changes are made only when clock moves from low to high.  Also called “delay flip-flop”. Clk D Qn ext Q΄ Condition 1 1 1 0 Store 1 0 X * * No change 1 0 0 1 Store 0 • *: previous condition • X: irrelevant
  • 11. J-K Flip Flop Clk J K Q Q΄ 1 0 0 * * 1 0 1 0 1 1 1 0 1 0 1 1 1 Toggle Toggle QKQJQnext • *: previous condition
  • 12. Asynchronous Counter  Ripple Counter.  The output of each J-K flip flop is connected to the clock of the next one.  Is an asynchronous counter. Events occur one after the other. However, high speed clocks can cause erroneous indications. .
  • 13. Synchronous counter  Synchronous counter: All events occur at the same time.
  • 14. Ring Counter  Only one output is high each time.  AND gates set only one flip-flop each time.
  • 15. Parallel Register  READ IN: flip-flops can be set only when Read-in is “1”.  READ OUT: output is obtained only when Read- out is “1”.  If Read-in and Read-out is “0” S=R=0 and flip- flops keep their previous condition.
  • 16. Serial to Parallel Shift Register  Data in bits shift right each time the clock ticks.  Useful for implementing:  serial to parallel data transfer  division
  • 17. Parallel to Serial Shift Register  Input: D1- D4.  When shift operation is set, each time the clock ticks data are forwarded to the output.
  • 18. Decoder  Detect a specific bit combination.  Each Y becomes “1”, only when a specific input combination is applied.
  • 19. Binary to decimal decoder  A 3-bit binary to decimal decoder (from 0 to 7).  Only one output can be high each time.
  • 20. Encoder  Accepts an input and converts it to a shorter representation (e.g. binary).  Decimal to binary converter from 1 to 9.