Clock divider by 3
•Download as PPTX, PDF•
1 like•7,745 views
The slide will explain how to realize circuit for clock divide by 3 with 50% duty cycle and with out 50% duty cycle.
Recommended
More Related Content
What's hot
What's hot (20)
Similar to Clock divider by 3
Similar to Clock divider by 3 (20)
Recently uploaded
Recently uploaded (20)
Clock divider by 3
- 1. Clock divider by 3 C Ashok Reddy
- 2. Clock divide by 3 I am going to explain how to design clock divide by 3 using digital logic element such as FF and universal gates. A divide by 3 clock requires a mod 3 counter. It can be constructed by using 2 FF(22 ) where the power of two represents the no of FF required for mod 3 counter. The no of states required for mod counter is three states 00, 01, 10 and the final state is xx. The output of the clock divide by three is not 50% duty cycle. The duty cycle will be 75% if the output is 1,1,0 C Ashok Reddy
- 3. Current state Next state Output Qb Qa Qb+ Qa+ 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 x x x x x • How to realize the micro architecture for the clock divide by3. • The table represents the current state, next state and output at each state. • How to realize the equations for the input of FFA, FFB and output is shown in the next slide Da’ Db’ C Ashok Reddy
- 4. 1 0 0 x Qa Qb 0 1 0 1 Da=Qa’Qb’ 0 0 1 x Qa Qb 0 1 0 1 Db=Qb 1 0 1 x Qa Qb 0 1 0 1 Out=Qa+Qb’ The K-Map realization for input FFA The K-Map realization for input FFB The K-Map realization for output of the FFB Clock divide by 3 C Ashok Reddy
- 5. The micro architecture of the clock divide by 3 is Clock divide by 3 DA QA QA ’ DB QB QB ’Clk Clk Da=Qa’Qb’ Db=Qb Out=Qa+Qb’ Reset Clock C Ashok Reddy
- 6. Input : Clock and reset Output : clk_out Clock divide by 3 Timing diagram for clock divide by 3 without 50% duty cycle C Ashok Reddy
- 7. To get 50% duty cycle the out of the FFB will as input to the negative edge trigger FF. The output of the third FF and the output of the second FF is given as input to the OR gate. Clock divide by 3 DA QA QA ’ DB QB QB ’Clk Clk DC QC QC ’Clk Reset Clock C Ashok Reddy
- 8. Input : Clock and reset Output : clk_out Clock divide by 3 Timing diagram for clock divide by 3 with 50% duty cycle In the same can implement other odd clock dividers such as clock divider 5, clock divider 7 and etc… C Ashok Reddy