Digital Electronics Unit_3.pptx

1. Unit 3

4. Memory element is latch

5. • Latch is an electronic device, which changes
its output immediately based on the applied
input.
• It is used to store either 1 or 0 at any specified
time.
• It consists of two inputs namely “SET” and
RESET and two outputs, which are
complement to each

7. • SR (Set-Reset) Latch – SR Latch is a circuit
with:
(i) 2 cross-coupled NOR gate or 2 cross-
coupled NAND gate.
(ii) 2 input S for SET and R for RESET.
(iii) 2 output Q, Q’.

10. SR-Latch Using NOR Gate

11. Case 1:
When S=0 and R=1 (Memory condition)
According to truth table of NOR gate, if any
input is 1 output is 0

12. Now if I remove the inputs S=0 and R=0 output
will not change because of memory condition
As we want to store data so we remove input and check
output if it is changing or not, as output is not changing so
data is stored.

13. Case 2:
S=1 and R=0
According to truth table of NOR gate, if any
input is 1 output is 0

14. Now if I remove the inputs S=0 and R=0 output
will not change because of memory condition

15. Case 3: (is not used)
S=1 and R=1 output Q= 0 and Q’=0 which is a
problem.

16. Truth Table

17. SR Latch using NOR Gate
• When output Q = 1 and Q’ = 0, the latch is
said to be in the set state.
• When Q = 0 and Q’ = 1, it is in the reset
state .
• Outputs Q and Q’ are normally the
complement of each other.
• However, when both inputs are equal to 1 at the
same time, a condition in which both outputs are
equal to 0 (rather than be mutually
complementary) occurs.
• If both inputs are then switched to 0
simultaneously, the device will enter an
unpredictable or undefined state

18. • The first condition (S = 1,R = 0) is the action
that must be taken by input
• S to bring the circuit to the set state. Removing
the active input from S leaves the circuit in the
same state.
• After both inputs return to 0, it is then possible to
shift to the reset state by momentary applying a 1
to the R input.
• The 1 can then be removed from R, whereupon
the circuit remains in the reset state.
• Thus, when both inputs S and R are equal to 0,
the latch can be in either the set or the reset
state, depending on which input was most
recently a 1.

20. The following is the RS Latch
with NAND gates:

25. Truth table of SR latch
with NAND Gate

28. R*=S’+En’ Output(Q and
Q’) or state will
not change until
En is 0 that is
why we called it
as SR latch
controlled input
Example of latch
Control
input
Circuit is
operational
when enable is
high

32. Clock is a signal which goes from low to high and again repeats
Low = 0
High =1

33. We don’t want our input to change randomly so we need clock
We can design Flip flop which will work or functional only when clock is
high or we can also design flip flop when clock goes from low to high or
high to low.
When clock is
high SR flip flop
will work

34. Memory element is latch

35. Types of Triggering
• Following are the two possible types of
triggering that are used in sequential
circuits.
1. Level triggering
2. Edge triggering

36. Level triggering
• There are two levels, namely logic High
and logic Low in clock signal.
• Following are the two types of level
triggering.
1. Positive level triggering
2. Negative level triggering

37. • If the sequential circuit is operated with
the clock signal when it is in Logic High,
then that type of triggering is known
as Positive level triggering.
• It is highlighted in below figure.

38. • If the sequential circuit is operated with
the clock signal when it is in Logic Low,
then that type of triggering is known
as Negative level triggering.
• It is highlighted in the following figure.

39. Edge triggering
• There are two types of transitions that
occur in clock signal.
• That means, the clock signal transitions
either from Logic Low to Logic High or
Logic High to Logic Low.
• Following are the two types of edge
triggering based on the transitions of
clock signal.
1. Positive edge triggering
2. Negative edge triggering

40. • If the sequential circuit is operated with
the clock signal that is transitioning from
Logic Low to Logic High, then that type of
triggering is known as Positive edge
triggering.
• It is also called as rising edge triggering.
• It is shown in the following figure.

41. • If the sequential circuit is operated with
the clock signal that is transitioning from
Logic High to Logic Low, then that type of
triggering is known as Negative edge
triggering.
• It is also called as falling edge triggering.
• It is shown in the following figure.

43. SR Flip-Flop
• SR flip-flop operates with only positive clock
transitions or negative clock transitions.
The circuit diagram of SR flip-flop is shown in
the following figure.

45. Positive Edge Triggered
Positive Edge Triggered

46. Negative Edge Triggered
Negative Edge Triggered

47. SR
latch
with
NAND
gate
SR FLIP FLOP using NAND

48. Truth table of SR latch
with NAND Gate

49. Truth Table of SR Flip-Flop

50. Explanation
• S*=S’+clk’
• R*=R’+clk’
• When Clock =0 stored value will not be
changed.
When Clock =1 than
S*=S’+1’ R*=R’+1’
S*=S’+0 R*=R’+0
S*=S’ R*=R’

51. Case 1: S=0 and R=0
S*=S’=0’=1
R*=R’=0’=1
Means memory(stored value will not change)
Case 2: S=0 and R=1
S*=S’=0’=1
R*=R’=1’=0
Check truth table of SR Latch NAND Gate
When S*=1 and R*=0
Output=0 1

52. Case 3: S=1 and R=0
S*=S’=1’=0
R*=R’=0’=1
Output= 1 0
Case 4: S=1 and R=1
S*=S’=1’=0
R*=R’=1’=0
Check truth table of SR Latch NAND Gate
When S*=1 and R*=0
Output=Not Used

54. characteristic table of SR flip-flop
Previous

55. Note
• Next state(Qt+1) is dependent on input which
is S and R and also on previous state Qt.

56. Excitation table of SR Flip Flop

57. Now to draw K map see the
characteristic table
Previous

59. 2019
• What is a D flip flop? Show how SR flip flop
can be converted to D flip flop?(3 marks)

60. D Flip-Flop
• The circuit diagram of D flip-flop is shown in
the following figure.
• To store data we use D flip flop

62. D means data. In this we give inputs,
store the data and remove the clock

64. SR To D flip flop

66. When D=0 and
CLK=1

67. Truth Table of D
Next state

68. Characteristic table
Previous

69. Note
• Next state(Qn+1) is dependent on input D and
also on previous state Qn.

70. From the previous table, we can directly write the
next state equation as
Qn+1 = D.Qn’+D.Qn=D(Q’n+Qn)=D
Qn+1=D (characteristics equations)
Next state of D flip-flop is always equal to data
input, D for every positive transition of the clock
signal.

71. Excitation table of D flip flop

72. Explanation
1. When Qn=0 and Qn+1=0 then D=1 (check
from characteristic table)
2. When Qn=0 and Qn+1=1 then D=1 (check
from characteristic table)
3. When Qn=1 and Qn+1=0 then D=0 (check
from characteristic table)
4. When Qn=1 and Qn+1=1 then D=1 (check
from characteristic table)

73. J-K Flip-Flop
• JK flip-flop is the modified version of SR flip-
flop.
• It operates with only positive clock transitions
or negative clock transitions.
• The circuit diagram of JK flip-flop is shown in
the following figure

78. Truth table of SR latch
with NAND Gate

81. • Case 1:
Clock =0 means memory
• Case 2:
Clock =1 and j=1,k=0 so output Q=1 and Q’=0
• Case 3:
Clock =1 and j=0,k=1 so output Q=0 and Q’=1
First 4 cases are same in J-K and S-R flip flop
Case 4:
Clock =1 and j=1,k=1
so output Q=01010101
And Q’=1010101010 so output keeps on
toggling

82. Truth table of SR latch
with NAND Gate

84. Characteristic table of JK flip flop
Previous

87. 2019
What is race condition and how it can be
eliminated in Master-Slave JK flip flop?(6.5
marks)
Master slave operation is same as negative edge
triggered flip flop

88. Race Around Condition In JK Flip-flop
• For J-K flip-flop, if J=K=1, and if clk=1 for a long
period of time, then Q output will toggle as
long as CLK is high, which makes the output of
the flip-flop unstable or uncertain.
• This problem is called race around condition
in J-K flip-flop.
• This problem (Race Around Condition) can be
avoided by ensuring that the clock input is at
logic “1” only for a very short time.
• This introduced the concept of Master Slave
JK flip flop.

89. Conditions
1. Condition 1 : J=1 and k=1
2. Condition 2: Clock we apply is level triggered
3. Condition 3: processing time of flip flop is
less than one clock pluse.

91. When J=1 and K=1 and clock =1 given to input than Qn=1 and
Qn’=0
SR NAND latch

92. Output keeps on toggling which causes race around
condition

93. Clock is positive level triggered.
When clock is high (high means positive level triggered)
output will be high and low many times till one clock pulse.
And again output is high and low for next clock pulse.
Race Condition In JK Flip-flop

94. Race Around Condition In JK Flip-flop
Clock diagram

95. 2015
Discuss and explain the working of master slave
JK flip flop. What are its advantages? (12.5
marks)
2018
Explain master slave flip flop (2 marks)

96. Methods to eliminate race around
condition
• Use of master-slave JK flip-flop

97. Master Slave JK flip flop
• The Master-Slave Flip-Flop is basically a
combination of two JK flip-flops connected
together in a series configuration.
• Out of these, one acts as the “master” and
the other as a “slave”.
• The output from the master flip flop is
connected to the two inputs of the slave flip
flop whose output is fed back to inputs of the
master flip flop.
• Master slave flip flop is same as negative
edge triggered flip flop

98. • In addition to these two flip-flops, the circuit
also includes an inverter.
• The inverter is connected to clock pulse in
such a way that the inverted clock pulse is
given to the slave flip-flop.
• In other words if CP=1 for a master flip-flop,
then CP=0 for a slave flip-flop.

100. Output changes ones in a clock cycle
Feedback from slave has no effect on master because
master flip flop is disabled because clock = 0
Clock =1 , j=1,k=1 than Qn+1=Q’n
SR flip
flop

101. Working of a master slave flip flop
• When the clock pulse goes to 1, the slave is
isolated; J and K inputs may affect the state of the
system.
• The slave flip-flop is isolated until the CP goes to
0.
• When the CP goes back to 0, information is
passed from the master flip-flop to the slave and
output is obtained.
• Firstly the master flip flop is positive level
triggered and the slave flip flop is negative level
triggered, so the master responds before the
slave.

102. Timing Diagram of a Master flip flop

103. • Thus toggling takes place for a clock cycle.
• When the clock pulse is high, the master is
operational but not the slave thus the output
of the slave remains low till the clock remains
high.
• When the clock is low, the slave becomes
operational and remains high until the clock
again becomes low.
• Toggling takes place during the whole process
since the output is changing once in a cycle.

104. • There are two types of memory elements
based on the type of triggering that is suitable
to operate it.
• Latches
• Flip-flops
• Latches operate with enable signal, which
is level sensitive.
• Whereas, flip-flops are edge sensitive.
• Now, let us discuss about SR Latch & D Latch
one by one.

105. T Flip-Flop
• T flip-flop is the simplified version of JK flip-
flop.
• It is obtained by connecting the same input ‘T’
to both inputs of JK flip-flop.
• It operates with only positive clock transitions
or negative clock transitions.
• The circuit diagram of T flip-flop is shown in
the following figure.

106. The block diagram of "T Flip Flop"
using "JK Flip Flop" is given below

108. Next Output

109. • This circuit has single input T and two outputs
Qt & Qt’.
• The operation of T flip-flop is same as that of
JK flip-flop.
• Here, we considered the inputs of JK flip-flop
as J = T and K = T in order to utilize the
modified JK flip-flop for 2 combinations of
inputs.
• So, we eliminated the other two combinations
of J & K, for which those two values are
complement to each other in T flip-flop.

110. Truth table of T flip flop

112. Characteristic table of T

114. Excitation Table of T flip flop
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

116. Flip Flop Conversion

117. SR Flip-Flop to other Flip-Flop
Conversions
• Following are the three possible conversions
of SR flip-flop to other flip-flops.
1. SR flip-flop to D flip-flop
2. SR flip-flop to JK flip-flop
3. SR flip-flop to T flip-flop

118. SR flip-flop to D flip-flop conversion

119. 1. Here, the given flip-flop is SR flip-flop and the
desired flip-flop is D flip-flop.
2. Therefore, consider the
following characteristic table of D flip-flop.
Previous

120. 3. Excitation Table Calculation Of SR
1. Truth Table of SR flip flop
2. Excitation Table
Sn Rn Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 X
Qn Qn+1 Sn Rn
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

121. We know that SR flip-flop has two inputs S & R.
So, write down the excitation values of SR flip-
flop for each combination of present state and
next state values.
The following table shows the characteristic
table of D flip-flop along with the excitation
inputs of SR flip-flop.

122. input output
Extended truth table
Truth Table of D
Extended Truth table of SR

123. 4. The desired signal S and R can be obtained as
functions of D and Q current FF state from the
Karnaugh maps:
So, we got S = D & R = D' after simplifying.

124. 5. circuit diagram

125. SR flip-flop to JK flip-flop conversion

126. 1. Here, the given flip-flop is SR flip-flop and the
desired flip-flop is JK flip-flop.
2. Therefore, consider the
following characteristic table of JK flip-flop.

128. 3. Excitation Table Calculation Of SR
1. Truth Table of SR flip flop
2. Excitation Table
Sn Rn Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 X
Qn Qn+1 Sn Rn
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

129. 3. We know that SR flip-flop has two inputs S &
R.
• So, write down the excitation values of SR
flip-flop for each combination of present state
and next state values.
• The following table shows the characteristic
table of JK flip-flop along with the excitation
inputs of SR flip-flop.

130. J K Qn Qn+1 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1
Qn Qn+1 Sn Rn
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Excitation Table of SR flip flop
For S and R values take
reference from excitation
table of SR flip flop given
below
Input for Kmap
Truth table of JK
Excitation table of
SR
Output for Kmap

131. 4. The desired signal S and R can be obtained as
functions of JK and Q current FF state from the
Karnaugh maps:

132. 5. circuit diagram

133. Flip Flop Conversion

134. D flip-flop to T flip-flop conversion

135. 1. Here, the given flip-flop is D flip-flop and the
desired flip-flop is T flip-flop.
2. Therefore, consider the
following characteristic table of T flip-flop.

136. 3. Excitation Table Calculation Of D
1. Truth Table of D flip flop
2. Excitation Table
Dn Qn Qn+1
0 X 0
1 X 1
Qn Qn+1 Dn
0 0 0
0 1 1
1 0 0
1 1 1
Copy and paste value of Qn+1 in Dn

137. 3. write down the excitation values of D flip-
flop for each combination of present state and
next state values.
• The following table shows the characteristic
table of T flip-flop along with the excitation
inputs of D flip-flop.

138. T Qn Qn+1 D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Input for Kmap Output for Kmap
Truth table of T
Excitation table of D

139. 4. K Map for D flip flop

140. 5. circuit diagram

141. JK Flip-Flop to other Flip-Flop
Conversions
• Following are the three possible conversions
of JK flip-flop to other flip-flops.
1. JK flip-flop to T flip-flop
2. JK flip-flop to D flip-flop
3. JK flip-flop to SR flip-flop

142. 2018
• Explain J-K Flip Flop can be converted to T
Flip flop(7.5 marks)

143. 1. Here, the given flip-flop is JK flip-flop and the
desired flip-flop is T flip-flop.
2. Therefore, consider the
following characteristic table of T flip-flop.

144. Characteristic table of T

145. 3. Excitation Table Calculation Of JK
1. Truth Table of JK flip flop

146. 3. Excitation Table Calculation Of JK
2. Excitation Table of JK

147. 3. write down the excitation values of JK flip-flop
for each combination of present state and
next state values.
The following table shows the characteristic
table of T flip-flop along with the excitation
inputs of JK flipflop.

148. Truth table of T
Excitation table of
JK flip flop

149. 4. We can use 2 variable K-Maps for getting
simplified expressions for these two inputs.
The k-Maps for J & K are shown below.
So, we got, J = T & K = T after simplifying.

150. 5. Circuit Diagram

151. Flip Flop Conversion

152. Conversion of J-K Flip-Flop into
D Flip-Flop

153. 1. Here, the given flip-flop is JK flip-flop and the
desired flip-flop is D flip-flop.
2. Therefore, consider the
following characteristic table of D flip-flop.

154. Characteristic table

155. 3. Excitation Table Calculation Of JK
1. Truth Table of JK flip flop

156. 3. Excitation Table Calculation Of JK
2. Excitation Table of JK

157. 3. write down the excitation values of JK flip-flop
for each combination of present state and
next state values.
The following table shows the characteristic
table of D flip-flop along with the excitation
inputs of JK flipflop.

158. Truth table of D
Excitation table of
JK flip flop

161. Conversion of J-K Flip-Flop into
SR Flip-Flop

162. 1. Here, the given flip-flop is JK flip-flop and the
desired flip-flop is SR flip-flop.
2. Therefore, consider the
following characteristic table of SR flip-flop.

163. characteristic table of SR flip-flop

164. 3. Excitation Table Calculation Of JK
1. Truth Table of JK flip flop

165. 3. Excitation Table Calculation Of JK
2. Excitation Table of JK

166. 3. write down the excitation values of JK flip-flop
for each combination of present state and
next state values.
The following table shows the characteristic
table of T flip-flop along with the excitation
inputs of JK flipflop.

167. Truth table of SR
Excitation table of
JK flip flop

170. Summary of all Excitation Table