digitL ELECTRONICS

1. Digital Electronics
1
Module 4 : Sequential Circuits
Prof. Mrityunjoy Sen
Department of Computer Sc. & Engg.
Institute of Engineering & Management, Kolkata

2. Topics for Digital Electronics: Module 4
2
Types of Digital Circuits
1
Sequential Circuits – An Introduction
2
Types of Sequential Circuits
3
Clock Signal and Types of Triggering
4
Latches: S-R (Set-Reset), D (Delay), J-K and T (Toggle)
5
Flip-flops: S-R (Set-Reset), D (Delay), J-K and T (Toggle)
6
Registers
7
Counters
8

3. Types of Digital Circuit
3
Combinational Circuits
In sequential circuit, output depends not only on the combination of
present inputs but also on the previous output.
Previous output is nothing but the present state
Sequential circuits contain combinational circuits along with
memory storage elements.
Sequential Circuits
Combinational circuits consist of Logic gates. These circuits operate with binary values. The outputs of combinational
circuit depends only on the combination of inputs applied at that point in time.
• In this circuit, output “S” and “C” depend only on the input combination A and B
• Output doesn’t depend on it’s previous state

4. Sequential Circuits – An Introduction
4
• Sequential Circuits
- Outputs depend not only on the present inputs, but also on the past history of the system
- The system memorizes the state in which it is currently in
• How does the circuit memorize state?
- Using basic memory elements called latches and flip-flops.
- Constitute the basic building block using which we can store some information i.e. bits (0 or 1)
Combinational Circuits Sequential Circuits
Outputs depend only on present inputs. Outputs depend on both present inputs and
present state.
Feedback path is not present. Feedback path is present.
Memory elements are not required. Memory elements are required.
Clock signal is not required. Clock signal is required.
Easy to design. Difficult to design.
• Difference between Combinational and Sequential circuits:

5. Types of Sequential Circuits
5
• Asynchronous Sequential Circuits
- The state of the device can change at any time in response to changing inputs.
- Asynchronous sequential circuits are digital circuits that are not driven by clock
- They can be called as self-timed circuits. Output behavior depends on the input at discrete time.
• Synchronous Sequential Circuits
- The state of the device changes only at discrete times in response to a clock signal
Clock Signal:
Clock signal is a periodic signal. We can represent the clock signal
as a square wave, when both its ON time and OFF time are same.

6. Types of Triggering
6
There are two types of triggering that are used in sequential circuits
Edge Triggering:
There are two levels, namely logic High and logic Low in clock signal.
1. Positive level triggering : If the sequential circuit operates with the clock signal when it is in Logic High, then that
type of triggering is known as Positive level triggering.
2. Negative level triggering : If the sequential circuit operates with the clock signal when it is in Logic Low, then that
type of triggering is known as Negative level triggering.
Level Triggering:
There are two types of transitions that occur in clock signal: From Logic Low to Logic High or Logic High to Logic Low.
1. Positive edge triggering : If the sequential circuit operates when the clock signal transitions from Logic Low to Logic
High, then that type of triggering is known as Positive edge triggering. It is also called as rising edge triggering.
2. Negative edge triggering : If the sequential circuit operates with the clock signal transitions from Logic High to Logic
Low, then that type of triggering is known as Negative edge triggering. It is also called as falling edge triggering.
High
Low

7. Basic idea behind storing a bit ….
7
• Storing a bit is the most basic form of information storage
• Consider a cascade of two inverters (NOT Gate) with feedback
- Constitute a stable state of the system
- The circuit can memorize the output value as long as power is on.
How to design a circuit in which we can store some information or bits (i.e. 0 or 1)?
0 1 0 1
0 1 0
• In practice, we need something more
- We should be able to set the output values to 0 or 1 as per our requirement
- Need some additional circuitry
- The exact functionality distinguishes between different types of latches and flip-flops
Vin1 Vout1 = Vin2 Vout2

8. Design of Latches
8
What is Latch?
Different types of Latches
1. S-R (Set-Reset) type
2. D (Delay) type
3. J-K type
4. T (Toggle) type
There are two types of memory elements based on the type of triggering that is suitable to operate it.
1. Latches
2. Flip-flops
A latch is a temporary storage device that has a two stable states – 0 and 1
Latches operate with enable signal, which is level sensitive. Latch is also called bistable multivibrator.
Flip-flops are special kind of latch where the clock signal triggers the change in stored value and it’s edge sensitive.
High
Low 0 1
0 1 0

9. S-R (Set-Reset) Latch
9
S-R Latch consists of a pair of cross-coupled NOR or NAND gates
- Two inputs ( S and R ) and two outputs ( Q and Q’ )
- The output can be set to 0 or 1 by applying suitable values on S and R inputs
S R Q Q’
0 0 No Change No Change Hold
0 1 0 1 Reset to 0
1 0 1 0 Set to 1
1 1 ? ? Invalid
State Table
S-R Latch using NOR Gate
S-R Latch using NAND Gate
Logic Symbol for S-R Latch

10. There is a Race Condition
S-R (Set-Reset) Latch
10
Why is S = 1 & R = 1 is an invalid input combination?
1
0
1
0
S = 0, R = 0  No Change
S = 1, R = 1  ?
STEP 1
STEP 2
STEP 3
STEP 4
Speed of both NOR Gates is exactly same
1
0
1
0
1
2
0
1
0
1
1
2
0
1
0
0
1
2
0
0
0
1
1
2
If NOR Gate 1 is faster than NOR Gate 2
If NOR Gate 2 is faster than NOR Gate 1
** In practical, speed of no two gates are same due to fabrication differences

11. Gated S-R Latch
11
What is Race Condition?
A scenario where the final result or output depends on the relative speeds of the various components (here logic gates).
If we apply S = 1 & R = 1, and then apply S = 0 & R = 0, the output will settle to either Q = 0 & Q’ = 1 or Q = 1 & Q’ = 0
depending on the relative speeds of the two gates.
We can’t predict what will be the output if relative speeds of the gates are not known.
Gated S-R Latch
A gated latch requires an Enable input (E) .
When E = 1, the latch is active.
When E = 0, the latch is de-active and outputs don’t change.

12. Gated D (Delay) Latch
12
Important Characteristics of gated D Latch
A D-latch has single input (D) .
When the latch is enabled, the value at D is stored in Q.
A D-Latch using a S-R Latch
State Table
D-Latch using NAND gates D-Latch using NOR gates

13. S-R (Set-Reset) Flip-flops
13
SR flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, SR
latch operates with enable signal.
Q
Q ’
CLK S R Q(t) Q(t+1)
0 OR 1 X X X NC
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 ?
1 1 1 ?
Present Inputs Present State Next State
Characteristic Equation:
R.S = 0
Q(t+1) = R’.Q(t) + S

14. Excitation Table for S-R Flip-flop
14
From To S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Output Changes Required Value
CLK S R Q(t) Q(t+1)
0 OR 1 X X X NC
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 ?
1 1 1 ?
Present Inputs Present State Next State
State Table of S-R Flip-flop
Excitation Table of S-R Flip-flop

15. D Flip-flops
15
Characteristic Equation:
Q(t+1) = D
Circuit Diagram
Excitation Table

16. J-K Flip-flops
16
The J-K flip-flop is the most versatile flip-flop.
Like in S-R flip-flop, it has two inputs J and K, but does not have any invalid inputs.
Characteristic Equation:
Q(t+1) = J.Q(t)’+K’.Q(t)

17. T Flip-flops
17
T flip-flop is the simplified version of J-K flip-flop. It is obtained by connecting the same input T to
both inputs of J-K flip-flop.
Characteristic Equation:
Q(t+1) = T + Q(t)

18. Registers: Introduction
18
What is Register and it’s variations …
• A register consists of a group of flip-flops with a common clock input, used for storing binary data.
• Depending on the configuration, there can be several different variations of registers:
1. Parallel-in parallel-out (PIPO)
2. Serial-in serial-out (SISO)
3. Parallel-in serial-out (PISO)
4. Serial-in parallel-out (SIPO)
• If the register supports serial-in and serial-out modes, it is also called a shift register.
4-bit Register

19. Basic PIPO Register
19
Symbolic Representation (using vector notation)
When active clock edge arrives, input word
D1D2D3D4 gets stored in the register, and
available on the output Q1Q2Q3Q4.
0 1 0 0
1
0 0 0

20. LOAD Signal in Register
20
In practice, the clock is coming continuously, and there is a separate signal LOAD that specifies
when the register is to be loaded with new data.
There are two possible solutions:
1. Use a gated clock
2. Separate out CLK and LOAD using a multiplexer circuit
CLK
LOAD
Not a good solution, as
gating the clock with
another signal can cause
timing problems.
Output of AND
When LOAD = 0, output of multiplexer is Q1.
When LOAD = 1, output of multiplexer is D1.
Better and recommended
solution

21. Shift Register
21
A shift register is a register in which the binary data can be stored, and the data can be shifted to
the left or right when a shift signal is applied.
Shift register can be constructed simply by connecting D, S-R or J-K flip-flops in cascade.
Diagram of 4-Bit Shift Register
No. of positive edge of clock Serial Input Q1 Q2 Q3 Q4
0 - 0 0 0 0
1 1 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 1 1 1 0 1
1 1 0 1 0 0
0
0

22. Serial In - Parallel Out (SIPO) Shift Registers
22
What is SIPO Shift Register?
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the
input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to
each one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called
as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case,
we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.
Block Diagram of 3-bit SIPO Shift Register
The shift register, which allows serial input and produces parallel output is known as Serial In - Parallel
Out (SIPO) shift register.
No. of positive
edge of clock
Serial
Input
Q2 Q1 Q0
0 - 0 0 0
1 1 1 0 0
2 1 1 1 0
3 0 0 1 1
0 1 1
Register
Serial I/P Parallel
O/P

23. Parallel In - Serial Out (PISO) Shift Registers
23
The shift register, which allows parallel input and produces serial output is known as Parallel In - Serial Out (PISO) shift register.
Block Diagram of 4-bit PISO Shift Register
There are two basic tasks we need to complete
1. Load parallel data
2. Shift loaded data at output serially
Register
Parallel
I/P
Serial O/P
Shift / Load
CLK
It operates in 2 modes:
1. Load Mode: Shift / (Load)’ = 0
2. Shift Mode: Shift / (Load)’ = 1
D0 Q0 D1 Q1 D2 Q2 D3 Q3
CLK
Shift / Load
B0 B1 B2 B3
Output
0
0 0 0
1
1
1
1
0
0
0 B3
B2
B1
B3
B2
B1
1
0
0
0
0
1 1 1
0
0
0 Q3
Q2
Q1
Q2
Q1
Q0
Q2
Q1
Q0

24. Bidirectional Shift Registers
24
The shift register, which allows shifting of data in both directions (from Left to Right or from Right to Left).
Block Diagram of 4-bit Bidirectional Shift Register
Data Shift happens in two directions:
1. When M = 1, there will be RIGHT SHIFT
2. When M = 0, there will be LEFT SHIFT
D3 Q3 D2 Q2 D1 Q1 D0 Q0
CLK
0
Register
Input Output
Mode (M)
CLK
Input
Output
Mode
Output
1
Input 0
0
0
0 1 1 1
1
0
0
0
0 Q1
Q2
Q3
Din
Q1
Q2
Q3
Din
Q1
Q2
Q3
Din

25. Application of Shift Registers
25
1. Shift register is used as Parallel to serial converter, which converts the parallel data into serial data.
It is utilized at the transmitter section after Analog signal is converted into Digital signal
2. Shift register is used as Serial to parallel converter, which converts the serial data into parallel data.
It is utilized at the receiver section before Digital signal is converted into Analog signal
3. Shift register along with some additional gates, generate the sequence of zeros and ones. Hence, it
is used as sequence generator.
4. Shift registers are also used as counters. There are two types of counters based on the type of
output from right most D flip-flop is connected to the serial input. Those are Ring counter and
Johnson Ring counter.
a

26. Counters - Introduction
26
Usage of Counter: Counter is used for counting pulses. It is also used as frequency divider.
Types of Counter: There are two types of counters based on direction of count.
• Up Counter: If the counter counts from 0 to 2𝑁 − 1, then it is called as binary up counter
• Down Counter: If the counter counts down from 2𝑁 − 1 to 0, then it is called as binary down counter.
Classifications of Counter: Counters are classified as
• Synchronous Counter: Memory elements (Flip-flops) are having same clock pulse
• Asynchronous Counter: Memory elements (Flip-flops) are having different clock pulse

27. Asynchronous Binary Up Counter
27
An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to 2𝑁 − 1.
The block diagram of 3-bit Asynchronous binary up counter is shown in the following figure.
The 3-bit Asynchronous binary up counter
contains three T flip-flops and the T-input of all
the flip-flops are connected to ‘1’.
All these flip-flops are negative edge triggered but
the outputs change asynchronously.
The clock signal is directly applied to the first T
flip-flop. So, the output of first T flip-flop
toggles for every negative edge of clock signal.
The output of first T flip-flop is applied as clock
signal for second T flip-flop. So, the output of
second T flip-flop toggles for every negative edge
of output of first T flip-flop. Similarly, the output
of third T flip-flop toggles for every negative edge
of output of second T flip-flop, since the output of
second T flip-flop acts as the clock signal for third
T flip-flop.
Block Diagram of 3-bit Asynchronous Binary Up Counter

28. Asynchronous Binary Down Counter
28
An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts from 2𝑁 − 1 to 0.
The block diagram of 3-bit Asynchronous binary down counter is shown in the following figure.
Block Diagram of 3-bit Asynchronous Binary Down Counter

29. Synchronous Binary Up Counter
29
The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-
input AND gate. All these flip-flops are negative edge triggered and the
outputs of flip-flops change synchronously.
The T inputs of first, second and third flip-flops are 1, Q0 & Q0. Q1 respectively
The output of first T flip-flop toggles for every negative edge of clock signal.
The output of second T flip-flop toggles for every negative edge of clock signal
if Q0 is 1. The output of third T flip-flop toggles for every negative edge of
clock signal if both Q0 & Q1 are 1.
Block Diagram of 3-bit Synchronous Binary Up Counter T0 Q0 T1 Q1 Q0.Q1 T2 Q2 Q2Q1Q0
1 0 0 0 0 0 0 000
1 1 1 0 0 0 0 001
1 0 0 1 0 0 0 010
1 1 1 1 1 1 0 011
1 0 0 0 0 0 1 100
1 1 1 0 0 0 1 101
1 0 0 1 0 0 1 110
1 1 1 1 1 1 1 111
1 0 0 0 0 0 0 000
CLK
T0 Q0
Flip-Flop 1
Q0
T2 Q2
Flip-Flop 3
Q2
T1 Q1
Flip-Flop 2
Q1
1
Q2
Q1
Q0
Output

30. Synchronous Binary Down Counter
30
CLK
T0 Q0
Flip-Flop 1
Q0
T2 Q2
Flip-Flop 3
Q2
T1 Q1
Flip-Flop 2
Q1
1
Output
Q2
Q1
Q0
Homework: Prepare the state table for 3-bit Synchronous Binary Down Counter

31. Asynchronous Modulo Counter
31
The number of states or counting sequences through which a particular counter advances before
returning once again back to its original first state is called the modulus (MOD). In other words, the
modulus (or just modulo) is the number of states the counter counts and is the dividing number of the
counter.
T0 Q0
Flip-Flop 1
Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T1 Q1
Flip-Flop 2
Q1
T2 Q2
Flip-Flop 3
Q2
CLK
1
Block Diagram of Asynchronous Module-6 Counter
CLR CLR
CLR
NAND
Homework: Design Asynchronous Module-10 (Binary Coded Decimal / Decade) Counter
0 1 1
1
1
1
0

32. BCD Counter
32

33. Ring Counter
33
• It is application of shift register
• Number of states = Number of flip-flops = Number of bits
Block Diagram of Ring Counter
ORI : Overriding Input
PR : Preset

34. Johnson’s Counter
34
• It is application of shift register
• Number of states = 2 * Number of flip-flops = 2 * Number of bits
Block Diagram of Johnson’s Counter

35. 35

36. 36
References
Item / Topic Link / Details
Book Digital Design by Morris Mano
Book Digital Circuits & Design by S. Salivahanan, S. Arivazhagan
YouTube videos by Prof. Indranil Sengupta
for Sequential Circuits
https://www.youtube.com/watch?v=jm0PGDSSBkI&list=PLbRMhDVUM
ngfV8C6ElNAUaQQz06wEhFM5&index=32
YouTube videos by Prof. Hitesh Dholakiya
for Registers in Digital Electronics
https://www.youtube.com/watch?v=HDk1Swndn_M&list=PLgwJf8NK-
2e7nYSG31YWEUfwgAp2uIOBY&index=183