This document discusses various topics related to flip-flops and shift registers including:
1. Flip-flop timing parameters like setup time, hold time, and propagation delay.
2. The JK master-slave flip-flop configuration which uses two flip-flops to avoid unwanted state changes.
3. Switch contact bounce and how an RS latch can be used in a de-bounce circuit.
4. Different representations of flip-flops like truth tables, characteristic tables, and state diagrams.
5. HDL implementations of different types of flip-flops.
6. Shift register types like serial-in serial-out, serial-in parallel-out, parallel-in serial-
This document discusses various counter circuits including decade counters, presettable counters, and counter design using hardware description languages. It provides state tables and circuit diagrams for a decade counter, MOD-5 counter, presettable MOD-8 counter, and asynchronous decade counter. It also discusses using counters to build a digital clock and provides a block diagram. Verilog code is given for a MOD-8 up counter and down counter. The last pages cover important questions on designing various counters.
The document appears to be a scanned copy of a legal contract for the sale of a residential property located in California. The contract details the purchase price of the property, the down payment, terms for the remaining balance, contingencies for inspections and appraisal, and closing date. The contract is signed by both the buyer and seller agreeing to the terms of the sale.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
Introduction to Computer theory Daniel Cohen Chapter 4 & 5 SolutionsAshu
Solutions to selected important questions of chapter 4 and chapter 5 of Daniel I.A Cohen book Introduction to theory of computation used in many universities.
This document describes a proposed online student feedback system. The system would allow students to provide feedback through a web-based portal. It would have modules for students, heads of department, and administrators. The objectives are to create an easy and quick feedback system with true feedback. Some advantages listed are reducing time, easy management of the process, and a user-friendly interface. The document provides details on the existing manual system, proposed system architecture, software and hardware requirements, and conclusions. It also discusses future enhancements that could be made.
This document is a project report for a School Management System developed between May 20, 2016 and July 2, 2016. It was created by Ankit Shukla for their bachelor's degree in computer science and engineering under the guidance of Kaushik Adhikary and Sanjay Sharma. The system was developed to automate the management of fees and salaries in a school to make the process more efficient compared to the previous manual system. The report includes sections on the background, objectives, feasibility study, benefits, and system design and development.
This document discusses sequential circuits and their analysis. It defines sequential logic as circuits whose outputs depend not only on current inputs but also past inputs, requiring some type of memory. There are two types of sequential circuits: synchronous use a clock for synchronization, while asynchronous can change output at any time. Analysis of sequential circuits involves obtaining a description of the input-output-state sequence over time using techniques like logic diagrams, state tables, characteristic tables, and state diagrams. Various flip-flop designs are presented, including the SR latch, D latch using transmission gates, and master-slave flip-flop. Timing considerations like clock period and setup time are also covered.
This document discusses various counter circuits including decade counters, presettable counters, and counter design using hardware description languages. It provides state tables and circuit diagrams for a decade counter, MOD-5 counter, presettable MOD-8 counter, and asynchronous decade counter. It also discusses using counters to build a digital clock and provides a block diagram. Verilog code is given for a MOD-8 up counter and down counter. The last pages cover important questions on designing various counters.
The document appears to be a scanned copy of a legal contract for the sale of a residential property located in California. The contract details the purchase price of the property, the down payment, terms for the remaining balance, contingencies for inspections and appraisal, and closing date. The contract is signed by both the buyer and seller agreeing to the terms of the sale.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
Introduction to Computer theory Daniel Cohen Chapter 4 & 5 SolutionsAshu
Solutions to selected important questions of chapter 4 and chapter 5 of Daniel I.A Cohen book Introduction to theory of computation used in many universities.
This document describes a proposed online student feedback system. The system would allow students to provide feedback through a web-based portal. It would have modules for students, heads of department, and administrators. The objectives are to create an easy and quick feedback system with true feedback. Some advantages listed are reducing time, easy management of the process, and a user-friendly interface. The document provides details on the existing manual system, proposed system architecture, software and hardware requirements, and conclusions. It also discusses future enhancements that could be made.
This document is a project report for a School Management System developed between May 20, 2016 and July 2, 2016. It was created by Ankit Shukla for their bachelor's degree in computer science and engineering under the guidance of Kaushik Adhikary and Sanjay Sharma. The system was developed to automate the management of fees and salaries in a school to make the process more efficient compared to the previous manual system. The report includes sections on the background, objectives, feasibility study, benefits, and system design and development.
This document discusses sequential circuits and their analysis. It defines sequential logic as circuits whose outputs depend not only on current inputs but also past inputs, requiring some type of memory. There are two types of sequential circuits: synchronous use a clock for synchronization, while asynchronous can change output at any time. Analysis of sequential circuits involves obtaining a description of the input-output-state sequence over time using techniques like logic diagrams, state tables, characteristic tables, and state diagrams. Various flip-flop designs are presented, including the SR latch, D latch using transmission gates, and master-slave flip-flop. Timing considerations like clock period and setup time are also covered.
This presentation describes a minor project on developing a voice and speech activated lock using digital signal processing. The project aims to design a MATLAB simulation of a hardware lock that can recognize the voice and password of two authorized users to open the lock, represented by a 12V output. It will work by extracting features from users' voice samples, storing them in a database, and matching features from input voice to the database for authentication. The status is currently a work in progress to develop the software and train it to identify voices and passwords.
This document discusses decoders and encoders. It defines a decoder as a circuit that accepts a binary input and activates only one output corresponding to the input. An encoder is the inverse, converting an active input to a coded output. Various types of decoders and encoders are described, including 2-to-4 decoders, 3-to-8 decoders, priority encoders, decimal-to-BCD encoders, and octal-to-binary encoders. Truth tables and logic diagrams are provided as examples. Expansion of decoders using multiple lower-order decoders is also covered.
The document discusses several types of flip-flops including SR, D, JK, and T flip-flops. A flip-flop is a circuit that stores state information, typically as a 1 or 0, and can change state based on input signals. The document provides the characteristic equations, state tables, and diagrams for each type of flip-flop to illustrate their behaviors on changing state.
The document discusses flip-flops, which are basic electronic circuits that have two stable states and can serve as one bit of digital memory. It defines what a flip-flop is and describes several common types of flip-flops, including SR, JK, T, D, and master-slave edge-triggered flip-flops. The document provides brief explanations of how each flip-flop type works and is implemented using logic gates.
The document outlines specifications for a bank management system that allows customers to create and manage bank accounts. It includes sections on team members, aims, problem description, requirements, module descriptions, entity relationship diagrams, outputs, conclusions, and screenshots. The system provides customers access to create accounts, deposit/withdraw funds, and view reports. It was developed to meet banking needs and allow additional functionality beyond conventional systems.
- The document discusses magnitude comparators, which are used to compare two binary numbers and output whether the first number is less than, equal to, or greater than the second number.
- It explains 1-bit and 2-bit magnitude comparators, providing their truth tables and logic diagrams. For a 1-bit comparator, it derives the logic expressions for the three outputs using K-maps.
- For a 2-bit comparator, it similarly provides the truth table and derives the K-map expressions for the three outputs. It then shows the full logic diagram for a 2-bit magnitude comparator using AND, OR, and NOT gates.
The document discusses the pumping lemma for regular and context-free languages. It states that for regular languages, any string of length greater than n can be broken down into uvxyz where pumping uvixyiz for i >= 0 keeps the string in the language. For context-free languages, any string can be broken into five parts where pumping the second and fourth parts keeps the string in the language. Examples are given demonstrating how pumping works for strings generated by a context-free grammar.
The document appears to be a scanned collection of pages from a book or manual. It contains images of many pages with text and diagrams but no clear overall narrative or topic. As a scanned document, it provides visual copies of written content but no coherent summary can be extracted in 3 sentences or less since the full meaning and essence is not clear from the images alone.
This document provides an overview of sequential circuits such as latches and flip-flops. It defines sequential circuits and explains that they produce outputs based on current and previous inputs. The basic types of latches and flip-flops are described as SR, D, JK, and T. Characteristics of synchronous and asynchronous sequential circuits are also summarized. Common applications of sequential circuits include shift registers, counters, clocks, and storing temporary information in microprocessors. The document concludes by discussing specific sequential circuit components like SR latches, D flip-flops, and JK flip-flops in more detail.
The document summarizes an online banking project created by three students for their graduation from a Ministry of Communications and Information Technology scholarship program in 2014. The project allows users to apply for accounts, view dashboards, transfer funds between accounts, view transaction histories, and more. The students used tools like NetBeans, SQL Developer, and Dreamweaver to develop the system using technologies like Oracle SQL, Java Server Faces, Enterprise Java Beans, and web services. They implemented phases of analysis using UML diagrams, database design with ERD, and developing business rules with EJB and JPA before designing the graphical user interface. The students hope to expand the system further and prove the value of their scholarship.
This document discusses several methods for designing sequential circuits, including state tables, state assignment, and deriving flip-flop input equations. It then provides examples of implementing sequential circuits using ROMs, PLAs, CPLDs, and FPGAs. Specifically, it designs a comparator circuit and code converter as examples of iterative and sequential circuits. It also discusses implementing a parallel adder and shift register using an FPGA.
The analysis describes what a given circuit will do under certain
operating conditions. The behaviour of a clocked sequential
circuit is determined from the inputs, the outputs, and the
state of its flip-flops.
More informaion:
https://sites.google.com/view/vajira-thambawita/leaning-materials/slides
The document presents the design of an online tour and travel management system. It includes modules for tours, hotel reservations, and administration. It discusses the feasibility study, cost estimation, functional point analysis, system requirements, software development life cycle using the waterfall model, data design with entity relationship diagrams, procedural design with data flow diagrams, use case diagrams, activity diagrams, class diagrams, COCOMO model, test cases, user interface design, and future scope. The system is designed to allow users to book and manage tours, hotels, and transportation online.
A computer based management system is designed to handle all the primary information required to calculate monthly statements of customer account which include monthly statement of any month. Separate database is maintained to handle all the details required for the correct statement calculation and generation.
This project intends to introduce more user friendliness in the various activities such as record updation, maintenance, and searching. The searching of record has been made quite simple as all the details of the customer can be obtained by simply keying in the identification or account number of that customer. Similarly, record maintenance and updation can also be accomplished by using the account number with all the details being automatically generated. These details are also being promptly automatically updated in the master file thus keeping the record absolutely up-to-date.
Computer Organization And Architecture lab manualNitesh Dubey
The document discusses the implementation of various logic gates and flip-flops. It describes half adders and full adders can be implemented using XOR and AND gates. Binary to gray code and gray to binary code conversions are also explained. Circuit diagrams for 3-8 line decoder, 4x1 and 8x1 multiplexer are provided along with their truth tables. Finally, the working of common flip-flops like SR, JK, D and T are explained through their excitation tables.
DIGITAL COMMUNICATION: ENCODING AND DECODING OF CYCLIC CODE ShivangiSingh241
Cyclic codes are a type of linear code where any cyclic shift of a codeword is also a codeword. This allows for efficient encoding and decoding using shift registers.
Encoding of cyclic codes can be done by dividing the message polynomial by the generator polynomial, with the remainder becoming the parity bits. Encoding circuits use shift registers with feedback to efficiently perform this division. Decoding uses the syndrome, which is computed by shifting the received word into a syndrome register. A decoder then attempts to match the syndrome to an error pattern, correcting errors one symbol at a time by shifting the syndrome and received word simultaneously.
This document discusses multiplexers and demultiplexers. It defines them as devices that allow digital information from several sources to be routed onto a single line (multiplexers) or distributed to multiple output lines (demultiplexers). The key properties of multiplexers and demultiplexers are described, including the relationship between the number of inputs, outputs, and selection lines. Examples of implementing multiplexers and demultiplexers using logic gates are provided.
This document provides an introduction to sequential circuits and various types of flip-flops. It discusses the differences between combinational and sequential circuits, and describes SR, D, JK, T, and JK flip-flops. Their block diagrams, truth tables, characteristic tables, and excitation tables are presented. Applications of flip-flops such as counters, frequency dividers, shift registers, and data storage are also covered briefly. Finally, the document discusses various types of shift registers including serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out.
The document discusses sequential circuits and different types of flip flops and counters. It describes how sequential circuits have memory and their output depends on current and past inputs. There are two main types of sequential circuits - asynchronous which can change state at any time and synchronous which use a clock signal to control when the output can change state. Common types of flip flops described include SR, JK, D and T flip flops. Counters can be asynchronous with the clock signal rippling through or synchronous where all flip flops share the same clock.
This presentation describes a minor project on developing a voice and speech activated lock using digital signal processing. The project aims to design a MATLAB simulation of a hardware lock that can recognize the voice and password of two authorized users to open the lock, represented by a 12V output. It will work by extracting features from users' voice samples, storing them in a database, and matching features from input voice to the database for authentication. The status is currently a work in progress to develop the software and train it to identify voices and passwords.
This document discusses decoders and encoders. It defines a decoder as a circuit that accepts a binary input and activates only one output corresponding to the input. An encoder is the inverse, converting an active input to a coded output. Various types of decoders and encoders are described, including 2-to-4 decoders, 3-to-8 decoders, priority encoders, decimal-to-BCD encoders, and octal-to-binary encoders. Truth tables and logic diagrams are provided as examples. Expansion of decoders using multiple lower-order decoders is also covered.
The document discusses several types of flip-flops including SR, D, JK, and T flip-flops. A flip-flop is a circuit that stores state information, typically as a 1 or 0, and can change state based on input signals. The document provides the characteristic equations, state tables, and diagrams for each type of flip-flop to illustrate their behaviors on changing state.
The document discusses flip-flops, which are basic electronic circuits that have two stable states and can serve as one bit of digital memory. It defines what a flip-flop is and describes several common types of flip-flops, including SR, JK, T, D, and master-slave edge-triggered flip-flops. The document provides brief explanations of how each flip-flop type works and is implemented using logic gates.
The document outlines specifications for a bank management system that allows customers to create and manage bank accounts. It includes sections on team members, aims, problem description, requirements, module descriptions, entity relationship diagrams, outputs, conclusions, and screenshots. The system provides customers access to create accounts, deposit/withdraw funds, and view reports. It was developed to meet banking needs and allow additional functionality beyond conventional systems.
- The document discusses magnitude comparators, which are used to compare two binary numbers and output whether the first number is less than, equal to, or greater than the second number.
- It explains 1-bit and 2-bit magnitude comparators, providing their truth tables and logic diagrams. For a 1-bit comparator, it derives the logic expressions for the three outputs using K-maps.
- For a 2-bit comparator, it similarly provides the truth table and derives the K-map expressions for the three outputs. It then shows the full logic diagram for a 2-bit magnitude comparator using AND, OR, and NOT gates.
The document discusses the pumping lemma for regular and context-free languages. It states that for regular languages, any string of length greater than n can be broken down into uvxyz where pumping uvixyiz for i >= 0 keeps the string in the language. For context-free languages, any string can be broken into five parts where pumping the second and fourth parts keeps the string in the language. Examples are given demonstrating how pumping works for strings generated by a context-free grammar.
The document appears to be a scanned collection of pages from a book or manual. It contains images of many pages with text and diagrams but no clear overall narrative or topic. As a scanned document, it provides visual copies of written content but no coherent summary can be extracted in 3 sentences or less since the full meaning and essence is not clear from the images alone.
This document provides an overview of sequential circuits such as latches and flip-flops. It defines sequential circuits and explains that they produce outputs based on current and previous inputs. The basic types of latches and flip-flops are described as SR, D, JK, and T. Characteristics of synchronous and asynchronous sequential circuits are also summarized. Common applications of sequential circuits include shift registers, counters, clocks, and storing temporary information in microprocessors. The document concludes by discussing specific sequential circuit components like SR latches, D flip-flops, and JK flip-flops in more detail.
The document summarizes an online banking project created by three students for their graduation from a Ministry of Communications and Information Technology scholarship program in 2014. The project allows users to apply for accounts, view dashboards, transfer funds between accounts, view transaction histories, and more. The students used tools like NetBeans, SQL Developer, and Dreamweaver to develop the system using technologies like Oracle SQL, Java Server Faces, Enterprise Java Beans, and web services. They implemented phases of analysis using UML diagrams, database design with ERD, and developing business rules with EJB and JPA before designing the graphical user interface. The students hope to expand the system further and prove the value of their scholarship.
This document discusses several methods for designing sequential circuits, including state tables, state assignment, and deriving flip-flop input equations. It then provides examples of implementing sequential circuits using ROMs, PLAs, CPLDs, and FPGAs. Specifically, it designs a comparator circuit and code converter as examples of iterative and sequential circuits. It also discusses implementing a parallel adder and shift register using an FPGA.
The analysis describes what a given circuit will do under certain
operating conditions. The behaviour of a clocked sequential
circuit is determined from the inputs, the outputs, and the
state of its flip-flops.
More informaion:
https://sites.google.com/view/vajira-thambawita/leaning-materials/slides
The document presents the design of an online tour and travel management system. It includes modules for tours, hotel reservations, and administration. It discusses the feasibility study, cost estimation, functional point analysis, system requirements, software development life cycle using the waterfall model, data design with entity relationship diagrams, procedural design with data flow diagrams, use case diagrams, activity diagrams, class diagrams, COCOMO model, test cases, user interface design, and future scope. The system is designed to allow users to book and manage tours, hotels, and transportation online.
A computer based management system is designed to handle all the primary information required to calculate monthly statements of customer account which include monthly statement of any month. Separate database is maintained to handle all the details required for the correct statement calculation and generation.
This project intends to introduce more user friendliness in the various activities such as record updation, maintenance, and searching. The searching of record has been made quite simple as all the details of the customer can be obtained by simply keying in the identification or account number of that customer. Similarly, record maintenance and updation can also be accomplished by using the account number with all the details being automatically generated. These details are also being promptly automatically updated in the master file thus keeping the record absolutely up-to-date.
Computer Organization And Architecture lab manualNitesh Dubey
The document discusses the implementation of various logic gates and flip-flops. It describes half adders and full adders can be implemented using XOR and AND gates. Binary to gray code and gray to binary code conversions are also explained. Circuit diagrams for 3-8 line decoder, 4x1 and 8x1 multiplexer are provided along with their truth tables. Finally, the working of common flip-flops like SR, JK, D and T are explained through their excitation tables.
DIGITAL COMMUNICATION: ENCODING AND DECODING OF CYCLIC CODE ShivangiSingh241
Cyclic codes are a type of linear code where any cyclic shift of a codeword is also a codeword. This allows for efficient encoding and decoding using shift registers.
Encoding of cyclic codes can be done by dividing the message polynomial by the generator polynomial, with the remainder becoming the parity bits. Encoding circuits use shift registers with feedback to efficiently perform this division. Decoding uses the syndrome, which is computed by shifting the received word into a syndrome register. A decoder then attempts to match the syndrome to an error pattern, correcting errors one symbol at a time by shifting the syndrome and received word simultaneously.
This document discusses multiplexers and demultiplexers. It defines them as devices that allow digital information from several sources to be routed onto a single line (multiplexers) or distributed to multiple output lines (demultiplexers). The key properties of multiplexers and demultiplexers are described, including the relationship between the number of inputs, outputs, and selection lines. Examples of implementing multiplexers and demultiplexers using logic gates are provided.
This document provides an introduction to sequential circuits and various types of flip-flops. It discusses the differences between combinational and sequential circuits, and describes SR, D, JK, T, and JK flip-flops. Their block diagrams, truth tables, characteristic tables, and excitation tables are presented. Applications of flip-flops such as counters, frequency dividers, shift registers, and data storage are also covered briefly. Finally, the document discusses various types of shift registers including serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out.
The document discusses sequential circuits and different types of flip flops and counters. It describes how sequential circuits have memory and their output depends on current and past inputs. There are two main types of sequential circuits - asynchronous which can change state at any time and synchronous which use a clock signal to control when the output can change state. Common types of flip flops described include SR, JK, D and T flip flops. Counters can be asynchronous with the clock signal rippling through or synchronous where all flip flops share the same clock.
JK flip-flops have two outputs, Q and Q', and four modes of operation: hold, set, reset, toggle. The primary output is Q. There are two stable states that can store state information. JK flip-flops are used for data storage in registers, counting in counters, and frequency division. They can divide the frequency of a periodic waveform in half by toggling on each input clock pulse.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
The document provides information about different types of flip-flops and shift registers. It discusses the RS, JK, D, and T flip-flops, explaining their symbols, truth tables, constructions, and workings. It also covers serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out shift registers, giving examples of how each type works. Finally, it poses three questions about flip-flops and shift registers.
This document discusses various types of flip-flops including RS, D, JK, T flip-flops. It describes their characteristic tables and excitation tables. It also covers sequential circuits, state tables, state diagrams, state equations, and the design of counters using flip-flops. Key topics include the use of flip-flops as memory elements, master-slave configurations to prevent race-around conditions, and how to analyze and design sequential circuits and counters.
This document describes a 4-bit synchronous binary counter. It contains the truth table for a JK flip-flop, diagrams of the counter circuit using 4 JK flip-flops connected in series with a common clock, and tables showing the output logic states and timing diagram as the counter counts from 0 to 15 over 16 clock pulses.
This document provides an overview of different types of counters used in digital logic design, including ripple counters, synchronous counters, and their variations. It discusses binary ripple counters, BCD ripple counters, synchronous binary counters, synchronous up/down counters, and synchronous BCD counters. It also covers a 4-bit binary counter with parallel load capability. The document is intended to teach a digital logic design course and provide instruction on common counter circuits.
Electrónica digital: Diseño de contador con flip-flop tipo JK y D haciendo de...SANTIAGO PABLO ALBERTO
This document describes the design of a 4-bit binary synchronous counter using JK flip-flops and D flip-flops, applying Karnaugh maps. It includes the characteristic tables of the JK and D flip-flops, the state table for the counter, simplification of the input equations, and the schematic diagram of the counter circuit. The counter is designed to count from 0 to 7 in binary and then reset.
1) Flip-flops are basic memory elements that store one bit of information as a 1 or 0. Common types include RS, D, JK, and T flip-flops.
2) Registers are groups of flip-flops that can store multiple bits and perform data processing. Data is loaded into registers by transferring new information during a clock pulse.
3) Master-slave JK flip-flops prevent racing conditions by using two flip-flops triggered on opposite clock edges, with the slave output following the master.
Registers are used to store binary numbers and consist of groups of flip flops, with one flip flop per bit. There are four basic types of registers: serial in serial out, serial in parallel out, parallel in serial out, and parallel in parallel out. Shift registers are groups of flip flops connected to allow data to be entered and shifted. Data can be shifted either serially or in parallel. Common integrated circuits used include the 74164 for serial in parallel out and 74191 for serial in serial out.
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docxDIPESH30
The document discusses latches and flip-flops. It explains that latches can remain in the state they were set in even after input signals are removed. The main difference between latches and flip-flops is that latches are level-triggered while flip-flops are edge-triggered. Various latch and flip-flop circuits like D latches, SR latches, and JK flip-flops are described along with their truth tables. Experiments were conducted using integrated circuits to observe and verify the behavior of different latch and flip-flop circuits.
Flip flops are used to store digital data and can be triggered on either the rising or falling edge of a clock signal. The D flip flop stores the input data on the rising edge of the clock. Multiple flip flops can be used together to store parallel data from combinational logic circuits. Asynchronous reset inputs allow the flip flop output to be asynchronously cleared regardless of the clock. Flip flops are fundamental building blocks that enable the storage of data in digital circuits and computers.
Flip flops are basic digital memory elements that form the building blocks of sequential and combinational circuits. They have two stable states, logic 0 and logic 1. The document discusses different types of flip flops including latches, SR flip flops, D flip flops, JK flip flops, and T flip flops. It covers their triggering methods, excitation tables, state diagrams, and characteristic equations. Master-slave configuration is also described to avoid race-around conditions in flip flops.
FYBSC IT Digital Electronics Unit IV Chapter II Sequential Circuits- Flip-FlopsArti Parab Academics
Sequential Circuits: Flip-Flop:
Introduction, Terminologies used, S-R flip-flop, D flip-fop, JK flipflop, Race-around condition, Master – slave JK flip-flop, T flip-flop, conversion from one type of flip-flop to another, Application of flipflops.
This document provides an overview of synchronous sequential circuits. It discusses sequential circuits, storage elements like latches and flip-flops, clocked sequential circuit analysis including state reduction and assignment, and design procedures. It also covers registers, counters, and HDL models of sequential circuits. Key components include sequential logic versus combinational logic, the use of clocks and clock signals, different types of latches and flip-flops like SR, D, JK, and Master-Slave configurations. Analysis methods like state tables and state transition diagrams are introduced.
Sequential circuits have memory and their output depends on both the current inputs and past outputs. They contain combinational circuits and feedback loops using latches and flip-flops. There are two main types of sequential circuits - asynchronous which can change state anytime the inputs change, and synchronous which only change on a clock signal.
Latches continuously track inputs and can change output anytime, while flip-flops only change output on a clock signal. Common flip-flop types include SR, D, T, and JK. Counters are sequential circuits that cycle through a sequence of states on each clock pulse and are used to count events.
These slides contain the basic of sequential logic, and includes a detailed and animated description of Flip-Flop and latches, it includes shift registers and counters also. It covers the fourth unit of Digital Logic Design
This document discusses different types of flip-flops, which are basic sequential circuits that have two stable states and can store one bit of data. It describes common flip-flop types like the S-R latch, clocked S-R flip-flop, J-K flip-flop, D flip-flop, and T flip-flop. It also covers the master-slave J-K flip-flop configuration and differences between latches and flip-flops. Flip-flops have applications in registers, frequency dividers, and digital counters.
This document provides information on FET devices, including JFETs and MOSFETs. It discusses the construction, operation, and biasing of N-channel and P-channel JFETs and N-channel and P-channel MOSFETs. The key differences between JFETs and MOSFETs are also outlined. Graphs of output characteristics and transfer characteristics are included to illustrate device behavior under different bias conditions. Biasing circuits like fixed bias and voltage divider bias are described for MOSFET applications.
This document contains an assembly language program to demonstrate various microprocessor and microcontroller concepts on the 8086/8088 microprocessor and 8255 Programmable Peripheral Interface (PPI) chip. It includes programs to:
1) Transfer data between memory locations using MOV instructions.
2) Perform arithmetic operations like addition, subtraction, multiplication and division using ALU instructions.
3) Perform logical operations like AND, OR, XOR on values using logical instructions.
4) Demonstrate a BCD up-down counter using an 8255 PPI chip to drive output ports.
5) Read input values from ports and perform multiplication using an 8255 PPI chip for I/O interfacing.
This document provides an overview of ARM instruction set architecture. It discusses various ARM data processing, branch, and load/store instructions. Data processing instructions include move, arithmetic, logical, comparison, and multiply instructions. Branch instructions change the flow of execution. Load/store instructions transfer data between registers and memory, including single register, multiple register, and half-word/byte instructions. The document provides syntax and examples to illustrate how each type of instruction works.
This document discusses ARM embedded systems and microprocessors. It covers ARM's RISC design philosophy, instruction set, and embedded system hardware and software components. The hardware components include the ARM processor, controllers, peripherals, and bus architecture. The software components include initialization code, operating systems, and applications. It also describes ARM registers, the program status register, pipelining, exceptions, interrupts, and the instruction set states.
This document discusses topics related to signed number arithmetic, string operations, memory interfacing, and 8255 I/O programming in microprocessors and microcontrollers. It provides details on signed number representation and arithmetic, string manipulation instructions, memory addressing decoding, and programming the 8255 parallel I/O port. Code examples are given to demonstrate signed number operations, finding average temperature and lowest value, and transferring data between memory blocks using string instructions.
This document discusses various x86 instruction sets including arithmetic, logic, shift, and compare instructions. It provides details on unsigned and signed addition, subtraction, multiplication, and division. Examples are given to demonstrate byte, word, and double word operations. Flags affected by different instructions are also outlined. The document is part of a course on microprocessors and microcontrollers and focuses on x86 instruction set descriptions.
This document provides an overview of the x86 microprocessor architecture. It discusses the history of x86 processors from the 8086 to modern Pentium and Intel 64-bit processors. It then describes the internal structure of the 8088/8086, including the bus interface unit, execution unit, registers, and flag register. It introduces assembly language programming and common instructions like MOV and ADD. It explains the code, data, stack, and extra segments and how logical addresses map to physical addresses. Memory allocation in IBM PCs is also summarized.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
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Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
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Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
artificial intelligence and data science contents.pptxGauravCar
What is artificial intelligence? Artificial intelligence is the ability of a computer or computer-controlled robot to perform tasks that are commonly associated with the intellectual processes characteristic of humans, such as the ability to reason.
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Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Comparative analysis between traditional aquaponics and reconstructed aquapon...
15CS32 ADE Module 4
1. ADE Module-4
Kishore Kumar R RLJIT Page 1
MODULE-4
Topics:
4.1Flip-Flop Timing
4.2 JK Master –Slave Flip-Flop
4.3 Switch contact Bounce circuits
4.4 Various representations of Flip-Flops
4.5 HDL implementation of Flip-Flop
4.6 SISO
4.7 SIPO
4.8 PISO
4.9 PIPO
4.10 Universal Shift register
4.11 Applications of Shift register
4.12 Register Implementation in HDL
4.13 Asynchronous Counters
4.14 Decoding Gates
4.15 Synchronous Counters
4.16 Counter Modulus
2. ADE Module-4
Kishore Kumar R RLJIT Page 2
FLIP-FLOP Timing:
Flip-flop cannot change states immediately, it always take small amount of time to
change its state. Figure below shows switching time of D-Flip- Flop.
Set-up time (tsetup): it is minimum amount of time that the data bit to be at the input before clock
edge arrives.
Hold time (thold): it is minimum amount of time that data bit must be present after clock edge.
Propagation delay (tp): the amount of time flip-flop takes to change its output after the input
changes
JK Master-Slave FLIP-FLOP:
Two flip-flops are used in JK master Slave Flip-Flop, first Flip-Flop is Master, Second
Flip-Flop is Slave, Master is Positive Level-triggered Flip-Flop and Slave is Negative
Level-Triggered Flip-Flop. Output of Master Flip flop is depends on inputs J and K when
Clock is positive, output of master is connected to Slave, hence Slave follows the Master
when clock is negative.
Case 1: when clock C=1, and inputs J=K=0 , master output remains in last state, slave
follows the master when C=0, hence output Q remains in last state
3. ADE Module-4
Kishore Kumar R RLJIT Page 3
Case2: When C=1, J=1 and K=0, master output is 1, slave follows the master when clock =0,
hence Q=1
Case 3: when C=1, J=0, K=1 master output is 0, J and K inputs of slave are 0 and 1, when
C=0, output of slave Q =0
Case 4: When C=1 J=1, K=1, Master Toggles, slave also toggles when clock goes Low
Symbol Truth Table:
The symbol ┐appearing next to Q indicates Postponed Output. The master output is
dependent on inputs J and K while clock is high, the state of master is shifted to slave when
clock goes Low.
Switch Contact Bounce Circuits:
In digital system, Switches are used to generate Low and High voltages, SPST (single
pole single Throw) switch is used in the above figure, when Switch is open the voltage at
point A is +5v, when switch is closed, the voltage at point A is 0v, ideal waveform at point A
is shown in figure (b), but actual waveform at point A appears as shown in figure (C), as a
4. ADE Module-4
Kishore Kumar R RLJIT Page 4
result of a phenomenon known as contact bounce, when the switch arm is moved from one
position to another, the arm bounces twice or thrice, because of this bouncy arm the
waveform at point A appears as shown in figure (c)
RS Latch De-bounce Circuit:
RS Latch can be used to avoid the contact bounce problem, the output Q can be used to
generate desired waveform.
When switch is moved to position H, S=1and R=0, bouncing occurs at S input, the flip-
flop output Q becomes 1 when arm touches H for the first time, when arm bounces both inputs S
and R will become 0, hence flip flop output does not change, it remains 1, similarly when switch
is moved to position L, S=0 and R=1, flip-flop output Q becomes 0, when arm bounces, both R
and S will become 0, Q does not change, it remains 0.
Various Representations of SR Flip-Flop:
Characteristic equation of SR Flip-Flop can be derived from the truth of the SR flip –flop,
expressing next state of flip-flop (Qn+1) as a function of previous state Qn and inputs of flip-flop
is characteristic equation.
Truth table of SR flip-Flop: Characteristic table: Excitation Table:
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 forbidden
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 ×
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 ×
Qn Qn+1 S R
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0
5. ADE Module-4
Kishore Kumar R RLJIT Page 5
Characteristic Equation can be derived from characteristic table using K-map for output Qn+1
State Transition Diagram of SR Flip-Flop:
Various Representations of D-Flip Flop:
Truth Table: Characteristic table: Excitation Table:
Characteristic equation of D flip-flop can be derived from characteristic table using K-map for
output Qn+1
From the K-map Qn+1 can be written as
Qn+1 = S + R Qn
D Qn+1
0 0
1 1
Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Characteristic Equation can be written as
Qn+1 = D
6. ADE Module-4
Kishore Kumar R RLJIT Page 6
State Transition Diagram of D Flip-Flop:
Various Representations of JK Flip-Flop:
Truth Table: Characteristic Table: Excitation Table:
State Transition Diagram of JK Flip-Flop:
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Qn Qn+1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Characteristic Equation of JK Flip-Flop is
7. ADE Module-4
Kishore Kumar R RLJIT Page 7
T Flip-Flop:
T Flip-Flop is also called as Toggle Flip-Flop.
T Flip-Flop has only one input.
Symbol: Truth Table:
Characteristic Table Characteristic Equation Excitation Table:
State Transition diagram of T Flip-Flop:
Problem: A fictitious Flip-Flop with two inputs A and B Functions like this, For AB=00 and 11
the output becomes 0 and 1 respectively, for AB=01 Flip flop retains previous state while output
complements for AB=10, write truth table and excitation table of this Flip-Flop.
Truth Table: Characteristic Table: Excitation table:
CLK T Qn+1
0 × Qn
0 Qn
1 Qn
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
A B Qn+1
0 0 0
0 1 Qn
1 0 Qn
1 1 1
Qn A B Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Qn Qn+1 A B
0 0 0 ×
0 1 1 ×
1 0 × 0
1 1 × 1
8. ADE Module-4
Kishore Kumar R RLJIT Page 8
HDL Implementation of Flip-Flops:
Program: Write Verilog Code for D Latch with Enable Input.
program: Write Verilog code for SR Latch with Enable Input.
Characteristic Equation of D Latch is
Qn+1=D
Characteristic Equation of SR Flip-Flop is
9. ADE Module-4
Kishore Kumar R RLJIT Page 9
Program: Write Verilog Code for Positive-Edge Triggered D Flip-Flop.
Program: Write Verilog Code for Positive-Edge Triggered D Flip-Flop.
Program: Write Verilog code for Positive-Edge Triggered D Flip-Flop with Asynchronous input
CLR
Registers:
Register is a group of flip-flops, which is used to store a word.
Bits in register can be shifted by applying clock signal, hence registers are also called as
Shift Register.
10. ADE Module-4
Kishore Kumar R RLJIT Page 10
Types of Registers:
Data can be shifted into a register either serially or in parallel, similarly data can be
shifted out of the register either serially or in parallel. Based on serial and parallel transmission,
registers are classified into four types
1. Serial in -Serial out Register
2. Serial in-Parallel out Register
3. Parallel in-Serial out Register
4. Parallel in-Parallel out register
Serial IN-Serial OUT Register:
Operation:
Assume initial state of counter is 0, hence Q3Q2Q1Q0 = 0000
11. ADE Module-4
Kishore Kumar R RLJIT Page 11
When bits 1011 are applied serially to register, data in the counter shifted as follows
At first clock Negative edge: LSB bit 1 will be shifted to FF-3, Q3 bit will be shifted to Q2, Q2
will be shifted to Q1, Q1 will be shifted to Q0, hence after first Negative edge of clock
Q3Q2Q1Q0 = 1000
At second Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter will be shifted right side
by one position, after second clock negative edge
Q3Q2Q1Q0 = 1100
At third Clock Negative Edge: Bit 0 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge
Q3Q2Q1Q0 = 0110
At Fourth Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge
Q3Q2Q1Q0 = 1011
Hence, after four clock cycles serial data 1011 is loaded in to the register
CLK Serial
Data
Q3 Q2 Q1 Q0
0 0
1 1
2 1
3 0
4 1
0 0 0 0
1 0 0 0
1 1 0 0
0 1 1 0
1 0 1 1
Timing Waveforms:
12. ADE Module-4
Kishore Kumar R RLJIT Page 12
Serial IN-Parallel OUT Register:
In SIPO, Data bits are entered serially and data bits are taken at output in parallel as shown in the
figure.
Operation:
Assume initial state of counter is 0, hence Q3Q2Q1Q0 = 0000
When bits 1011 are applied serially to register, data in the counter shifted as follows
At first clock Negative edge: LSB bit 1 will be shifted to FF-3, Q3 bit will be shifted to Q2, Q2
will be shifted to Q1, Q1 will be shifted to Q0, hence after first Negative edge of clock
Q3Q2Q1Q0 = 1000
At second Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter will be shifted right side
by one position, after second clock negative edge
Q3Q2Q1Q0 = 1100
At third Clock Negative Edge: Bit 0 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge
Q3Q2Q1Q0 = 0110
At Fourth Clock Negative Edge: Bit 1 is applied to FF-3, bits in counter shifts right side, hence
after third clock negative edge
Q3Q2Q1Q0 = 1011
Hence, after four clock cycles serial data 1011 is loaded in to the register
13. ADE Module-4
Kishore Kumar R RLJIT Page 13
CLK Serial
Data
Q3 Q2 Q1 Q0
0 0
1 1
2 1
3 0
4 1
0 0 0 0
1 0 0 0
1 1 0 0
0 1 1 0
1 0 1 1
Parallel IN –Parallel Output register:
In PIPO register, All data bits b3b2b1b0 are applied in parallel and outputs Q3Q2Q1Q0 are
collected in parallel.
Operation:
Assume initially all flip-flops are in state 0, hence output Q3Q2Q1Q0=0000, to put the data bits
1011 in to register, apply these four bits in parallel, at positive clock edge these four bits will be
stored in four flips simultaneously, hence outputs Q3Q2Q1Q0 = 1011, one clock cycle is enough to
store all four bits into register.
CLK b3 b2 b1 b0 Q3 Q2 Q1 Q0
1 1 0 1 1 1 0 1 1
Parallel IN-Serial OUT Register:
In Parallel IN-Serial OUT register, data bits b3b2b1b0 are applied as input in parallel to register,
bits are shifted out serially.
Figure below shows 4-bit Parallel IN-Serial OUT register
14. ADE Module-4
Kishore Kumar R RLJIT Page 14
Operation:
To Shift data into register:
To shift the data in register serially, set LOAD/SHIFT =0, since inversion of
LOAD/SHIFT is applied as input for AND gates 1a, 1b, 1c, inputs for AND gate 1a are Q3 and 1
hence AND gate 1a output =Q3, similarly output of AND gate 2a is Q2 and output of AND gate 3a
is Q1, since LOAD/SHIFT is connected directly to AND gate 1b, 2b,3b hence input for all AND
gates 1b,2b,3b is 0, output of all AND 1b,2b,3b gates 2 is 0.
Output of AND gates are connected to inputs of OR gates as shown in figure, inputs of OR gate
1 are 1, Q3 hence OR gate1 output =Q3, similarly OR gate 2 Output =Q2, OR gate 3 output =Q1,
OR gate 1 output Q3 is applied as input to second flip flop, OR gate 2 output Q2 is applied as input
to third flip-flop, output of OR gate 3 Q1 is applied as input to fourth flip-flop, hence Q3 is shifted
to Q2, Q2 is shifted to Q1, Q1 is shifted to Q0.
To Load data into register:
To load data b3b2b1b0=1011 into register in parallel, set LOAD/SHIFT =1, since
inversion of LOAD/ SHIFT is connected to 1a, 2a, 3a, outputs of AND gates 1a, 2a, 3a are 0, b3 is
connected directly as input to FF-3, inputs for AND gate 1b are 1, b2 hence its output is b2,
similarly output of AND gates 2b is b1, output of AND gate 3b is b0.
Outputs of OR gates are connected as inputs to FF-2 FF-1 and FF-0, inputs for OR gate 1 are 0,
b2, hence OR gate 1 output is b2 which is connected as input for FF-2, similarly output of OR gate
2 is b1, which is connected as input to FF-1, output of OR gate 3 is b0, which is connected as input
for FF-0, hence the data b3 b2 b1 b0 is loaded to FF-3 FF-2 FF-1 and FF-0 respectively
15. ADE Module-4
Kishore Kumar R RLJIT Page 15
Truth table when LOAD/SHIFT=0 and assume initial values of Q3Q2Q1Q0=0000 to put data
1011 into register serially, apply the bits 1011 serially at b3
Applications of Shift Register:
1. Ring Counter
2. Switched-Tail Counter or Johnson counter
3. Sequence Generator & Sequence Detector
5. Serial Adder
Ring Counter:
In ring counter, output of Last flip-flop is connected to input of the first flip-flop.
It is also called as circulating register.
Number of states = Number of Flip-flops
Operation:
Initially, SET input is made 0, it sets the flip-flop3 hence Q3=1, and it clears all other
three flip-flops hence, Q2=0, Q1=0, Q0=0. When first negative clock occurs, the output of flip-
flop 3 is shifted to flip-flop 2, output of flip-flop 2 is shifted to flip-flop 1, this cycle repeats at
every negative clock cycle. As shown in truth table, 1 is shifting around register each time the
clock goes negative.
CLK b3 Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 1 1 1 0 0
3 0 0 1 1 0
4 1 1 0 1 1
16. ADE Module-4
Kishore Kumar R RLJIT Page 16
Truth Table: Timing Diagram:
SET CLK Q3 Q2 Q1 Q0
0 ×
1
1
1
1
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Johnson counter or Switched-Tail counter:
In Johnson’s counter, inverted output (Q) from the last flip-flop is connected to the input
of first flip-flop.
Number of states = twice the number of flip-flops
Operation:
Initially, the CLEAR input is made 0, hence all flips-flops outputs will be 0, since Q0 is
connected to input of first flip flop, when clock goes negative, the output of FF-3 becomes 1 and
its previous output will be shifted to FF-2, FF-2 output will be shifted to FF-1 and so on, this
cycle repeats for every negative cycle.
Truth Table:
CLEAR CLK Q3 Q2 Q1 Q0
0 × 0 0 0 0
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
1 0 1 1 1
1 0 0 1 1
1 0 0 0 1
17. ADE Module-4
Kishore Kumar R RLJIT Page 17
Sequence Generator:
The shift register can be used to generate particular bit pattern repetitively, figure below
shows the basic block diagram of a sequence generator, Left most flip-flop accept the serial input
and right most flip-flop gives serial data output, serial data output is connected back to serial data
input, on every clock cycle, data shifts right, if we load desired bit pattern in register, same bit
pattern will be produced repetitively,
Sequence Detector:
Sequence detector can be used to detect desired sequence, as shown in figure below,
circuit uses two registers, one register is used to store bit pattern to be detected, and other register
accepts the input data bits serially, and sends the data out serially, on every clock cycle each and
every bit of both registers are compared using EX-NOR gates, when both inputs are same EX-
NOR gate produces high output, when the content of both registers are equal, all EX-NOR gates
produces 1, outputs of EX-NOR gates are connected to AND gate, hence AND gate produces 1
when all bits are equal in two registers, otherwise it produces zero.
As shown in figure, sequence to be detected is 1011, it is stored in below register, in
upper register data enters serially, when sequence of bits in upper register becomes 1011, AND
gate produces high output which indicates desired sequence is detected.
18. ADE Module-4
Kishore Kumar R RLJIT Page 18
Serial Adder:
Serial adder can be used to add two numbers bit by bit by using two registers, which hold
two numbers, and Full adder to perform addition at every negative clock cycle.
Operation:
On first negative clock cycle, LSB of two number A and B i.e. A0 and B0 are added by
full adder, sum S0 and carry C0 are produced, Sum S0 will be applied at serial in of Register A
and carry C0 is applied to D-Flip flop, on second negative cycle S0 will be stored in register A at
MSB position, full adder adds A1 and B1 and carry C0 from D Flip Flop will be added by , Sum
S1 and C1 are produces, on next negative clock cycle, S1 will ne stored in register A at MSB
position, S0 in register will be shifted right by one position, full adder will add A2 and B2 and
produces S2 and C2, this process continues, after 8 clock cycles final sum S7S6S5S4S3S2S1S0 will
be stored in Register A.
Universal Shift Register:
19. ADE Module-4
Kishore Kumar R RLJIT Page 19
A register which can shift data in both directions, and accepts data in serial as well as in
parallel is called Universal Shift Register. It can perform operations of all registers, SISO,
SIPO, PISO, PIPO.
Above figure shows the Universal shift register, four 4:1 multiplexers and 4 D-Flip Flops
are used, Select Lines S1 S0 are used to control the operations of universal shift register.
When S1S0 = 00, universal shift registers remains in previous state i.e. all flip-flops hold
previous outputs (Qn)
When S1S0 = 01, serial data input is applied to 1 input of left most Multiplexer, and data
will be shifted right.
When S1S0 = 10, serial data input is applied to 2 input of right most multiplexer, and data
will be shifted left.
When S1S0 = 11, parallel data b3b2b1b0 is applied to 3 input of all multiplexers
respectively, these parallel inputs will be loaded into flip-flops in parallel.
S1 S0 Function
0 0 Previous state (HOLD)
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load
Register Implementation in HDL:
Program: Write Verilog code for 6-bit negative edge triggered parallel input parallel
output register
module PIPO (D, CLK, CLR, Q);
input CLK, CLR;
input [5:0] D;
output [5:0] Q;
reg [5:0] Q;
always @ (negedge CLK or negedge CLR)
if (CLR==0) Q=6’b000000;
else Q=D;
endmodule
21. ADE Module-4
Kishore Kumar R RLJIT Page 21
Counter: Counter is a series of flip-flops used to count number of clock cycles.
Number of counts (states) of flip-flop = 2n
n number of flip flops
E.g. if counter has three flip-flops, n=3, the number of states =23
= 8 states (0-7)
There are two types of counters
1. Asynchronous Counter
2. Synchronous Counter
Asynchronous UP Counter or Ripple Counter:
In Asynchronous counter, clock is connected to first flip-flop, the output of first flip-flop
is connected to clock input of second flip-flop, and output of second flip-flop is
connected to clock input of third flip-flop.
Negative-Edge Triggered JK Flip-Flops can be used to design Asynchronous counter as
shown in figure below.
JK inputs of each flip-flop is connected to +Vcc, each flip-flop toggles its state at negative
edge of the clock.
Operation:
Assume initial state of all flip-flops is 0, hence CBA=000, at first negative edge of clock,
flip-flop A toggles to 1, hence output is CBA=001, flip-flop A toggles its state for every
negative edge of the clock, since the output of flip-flop A is connected as clock input to
flip-flop B, B toggles its state at every second negative edge of the clock, Flip-flop C
toggles its state at every fourth negative edge of the clock.
Timing Waveforms:
22. ADE Module-4
Kishore Kumar R RLJIT Page 22
Truth Table:
Asynchronous Down Counter:
In Asynchronous down counter, count decreases by one for every negative edge of clock,
In down counter, the complemented output of flip-flop is connected to clock input of next
flip-flop.
Operation:
Flip-flop A toggles its state at every negative edge of the clock, Flip-flop B toggles its
state when A changes from 1 to 0, similarly flip-flop C toggles when B changes from 1 to 0.
Timing Waveforms: Truth Table:
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Asynchronous UP-DOWN Counter:
Operation:
When count-up is 1 and count-down is 0, upper AND gate connects the output of flip-
flop to clock input of next flip-flop, hence counter works as UP-counter.
When Count-up is 0 and count-down is 1 Lower AND gate connects Complemented
output of flip-flop to clock input of next flip-flop, hence counter works as down counter.
Decoding Gates:
A Decoding gate can be connected to the outputs of a counter in such a way that the
output of gate will be HIGH only when the counter contents are equal to a given state.
Example: the Decoding gate connected to the 3-bit ripple counter in figure below will decode
state 7 i.e. C B A = 111, thus gate output is high only when C B A=111
Gate to decode state 5: Gate to decode state 0: Gate to decode state 1:
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Gate to decode 2 Gate to decode 3 Gate to decode 4 Gate to decode 5
Disadvantage of Asynchronous or Ripple counter:
Each Flip-flop has to wait for the previous flip-flop output; it increases the delay at the
counter output.
Glitches may occur at the output of decoding gates.
Synchronous UP Counter:
In Synchronous counter, same clock is applied to all the flip-flops, all flips flops get
triggered simultaneously.
J and K inputs of all flip-flops are connected to VCC, hence all flip-flops change its state
at negative clock edge. And gate is used to connect clock and output of previous flip-flop to
clock input of next flip-flop.
Operation:
Assume initially all flip-flops are in state 0, hence CBA=000, clock is applied directly to
flip-flop A, it changes its state at every negative clock edge, since clock and FF-A output is
connected to clock input of Flip-flop B through AND gate, FF-B changes its state at every
second negative clock edge, similarly FF-C changes its output at every fourth negative clock
cycle, since three flip-flops are used count starts from 000 to and last state is 111 after 111 it
repeats the count from 000
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Truth table and timing waveforms of Synchronous Up Counter:
Synchronous Down Counter:
In synchronous Down counter, ALL J and K inputs are tied to VCC and clock is applied
directly to FF-A, complemented output of FF-A and clock is connected to clock input of FF-B
through AND gate, complemented outputs of FF-A and FF-B and clock are connected to clock
input of FF-C through AND gate.
Operation:
Assume initial state of all Flip-flops is 0, hence QCQBQA=000,Clock is applied directly to
FF-A, it changes its state at every negative clock edge, FF-B changes its state at every second
negative clock edge, FF-C changes its state at every fourth negative clock cycle.
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All JK inputs are connected to VCC, both outputs of FFA are connected to clock input of
FFB through two AND gates, both outputs of FF A and FFB and clock is connected to clock
input of FF C through two AND gates.
Count-UP Mode:
When count-up control input is made 1 and count-down is made 0, clock is applied
directly to FF-A, and upper AND gates are enabled, Lower AND gates outputs are zero hence
Lower AND gates are disabled, hence FF-A output and CLOCK Is connected to connected to
clock input of FF-B, outputs of FF-A and FF-B and clock are connected to clock input of FF-C,
hence counter works as UP-counter.
Count –Down Mode:
When count-down control input is made 1 and count-up is made 0, clock is applied directly to
FF-A, and Lower AND gates are enabled, Upper AND gates outputs are zero hence upper AND
gates are disabled, hence complemented output of FF-A and CLOCK Is connected to connected
to clock input of FF-B, complemented outputs of FF-A and FF-B and clock are connected to
clock input of FF-C, hence counter works as DOWN-counter
Changing Counter Modulus:
In counter Modules = number of states in counter= 2n
, where ‘n’ is number of flip-flops,
modifying number of states of counter is called changing counter modulus.
Example: when two flip-flops are used for counter, number of states =4, it can be modified
to 3 as shown below.
MOD-3 counter:
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Operation:
1. Prior to point ‘a’ on the time line, A=0 and B=0 , a negative clock at ‘a’ will cause
a. A to toggle to 1 since its J and K inputs are high
b. B remains 0, since its J=0 and K=1
2. Prior to point ‘b’ on the time line, A=1 and B=0 , a negative clock at ‘b’ will cause
a. A to toggle to 0 since its J and K inputs are high
b. B to toggle to 1, since its J=1 and K=1
2. Prior to point ‘c’ on the time line, A=0 and B=1 , a negative clock at ‘c’ will cause
a. A remains 0 since its J=0 and K=1
b. B changes to 0, since its J=0 and K=1
Truth table of MOD-3 Logic Block of MOD-3
MOD-6 Counter:
MOD-6 counter can be designed by using MOD-3 and MOD-2 Counter (for MOD-2
single Flip-flop is enough) if B output of MOD-3 is connected to clock input of next flip-flop, it
works as MOD-6 counter.
Waveforms of MOD-6
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Truth table of MOD-6:
Truth Table:
CLK Q B A
0
1
2
3
4
5
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
CLK B A Q
0
1
2
3
4
5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
Note: This MOD-6 counter has 6 states, but count is not in straight sequence
Note: this mod-6 counter has 6 states, count is in straight sequence
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Comparison between Asynchronous and Synchronous Counters:
Asynchronous Counter Synchronous Counter
1. Output of flip-flop is connected to clock of
next flip-flop
2.Flip-flops are not triggered simultaneously
3. Design is simple
4. Asynchronous counter is slow
1. clock inputs of all flip-flops are connected to
same external clock
2. ALL Flip-flops are triggered simultaneously
3. Design is difficult
4. Synchronous Counter is faster.
Important Questions
1. What is Race-Around Condition? With block diagram and truth table explain working of JK
Master-Slave Flip-Flop JAN&JUL -17 (10 M)
2. Give State transition diagram and characteristic equations for JK and SR Flip-Flop
JAN-17 (6 M)
3. With neat diagram, explain Ring Counter JAN-17 (4 M)
4. What is shift register? With neat diagram explain 4 –bit PISO register JAN-17 (8 M)
Register in which binary bits are shifted either right side or left side is called as shift register.
5. Compare Synchronous and Asynchronous counters JAN&JUL-17 (4 M)
6. Derive characteristic equations for SR, D and JK Flip-flop JUL-17 (6 M)
7. Using negative edge triggered D Flip-flop, draw logic diagram of 4 bit SISO register , draw
waveform to shift Binary number 1010 into this register JUL-17 (6 M)
8. Explain with neat diagram how shift register can be used for serial addition JUL-17 (7 M)
9. With circuit diagram explain MOD-3 Counter
10. Design Mod-6 counter using MOD-3 and MOD-2 Counters
11. Write Verilog code for SIPO
12. Explain the operation of Universal shift register
12. Write Verilog code for Positive-Edge triggered D-Flip-Flop