This document provides an overview of SpyglassDFT, a tool for comprehensive RTL design analysis. It discusses key SpyglassDFT features such as lint checking, test coverage estimation, and an integrated debug environment. Important input files for SpyglassDFT like the project file and waiver file are also outlined. The document concludes with an example flow for using SpyglassDFT to analyze clocks and resets, identify violations, and prepare the design for manufacturing test.

1. SpyglassDft
-Kumar Gavanurmath

2. Agenda
• Understanding of SpyglassDFT
• Key Features.
• Important input files.
• Example Flow on understanding.

3. Understanding of SpyglassDFT

4. Cont…
• Spyglass DFT is comprehensive process of resolving RTL Design issues, thereby ensuring high quality RTL
with fewer design bugs.
• Spyglass DFT performs RTL testability analysis and improvement, enabling designers to fine-tune their RTL
early in the design cycle to predictably meet their manufacturing and in-system test coverage goals (TMT).
• Improves test quality by diagnosing DFT issues early at RTL or netlist.
• Shortens test implementation time and cost by ensuring RTL or netlist is scan-compliant.
Spyglass DFT
Sgdc file
Other setup files
Project file
Waiver file
Spyglass
Clean RTL

5. Key Features
• lint checking.
• RTL Test stuck-at and Transition coverage estimation.
• Integrated Debug Environment with cross-probing among views.

6. lint checking
• Earlier lint check was based on syntax analysis, later incorporated formal verification techniques as
this(Spyglass) can identify problem not just with syntax but inside state machine to catch unreadable states
and dead lock conditions.
• Some idea of problem addressing lint check
• Unsyenthesizable constructs.
• Unintentional latches.
• Unused signals, undriven and driven signals.
• Race Condition, Incorrect usage of blocking and non-blocking assignments.
• Case statement style issues.
• Set and reset conflicts.
• Uncovering at-speed test issues.
• All flops controllable by pll in at-speed test mode.
• Pll reference clock controllable from root level ports.
• Required frequencies must be achived.

7. RTL Test stuck-at and Transition coverage estimation
• Spyglass DFT ADV provides estimates stuck-at and transition delay fault coverage based on controllability
and observability analysis.
• Coverage estimates are quick and pattern less, thereby avoiding test benches or long runtimes.
• Audit reports provide step-by-step guidance that allows designers to quickly and incrementally isolate the
source of coverage loss.

8. Integrated Debug Environment with cross-probing among views

9. Important Input Files
• Project File:RTL/ required automatically generated file.
• Waiver File:
• Waivers are used to hide, waivers are used to exclude from linting.
• Use waivers to drop violations such as violations in previously validated IPs
• They are useful for excluding 3rd party IPs or libraries included in the compilation and will reduce the
total linting time without affecting the correctness of the design.
• waivers can be created using GUI.
• Sgdc file: automatically generated file, and can update according to design need
• Other setup file:Synopsys .lib files for instantiated gates and blocks, Re-check the file order. Include files
may be out of order.
• Check If design is showing blackboxes.

10. Example Flow
• After Re-check lib, .includes file, black box, Analyze the clocks reset and Domain crossing.
• Ability to read-in the design for the clocks and resets (SDC/sgdc file), and then creating sgdc file according to
design requirement to Review file and fix clock or reset definitions if required.
• Select Sync_checks template and run. Check Clock_sync01 violations.
• Check Clock-Reset-Summary for flops which will not be checked – either unconstrained or constant D-
input. And for list of domain crossings by clocks.
• Troubleshoot: Eliminate any violation which should not appear by fixing your SGDC, Tag Clocks in the
same domain with same –domain name.
• Use case analysis or cdc_false_path to eliminate crossings between non-interacting clocks.
• Use waivers to drop violations such as violations in previously validated Ips.
• Remove false violations case by case using cdc_false_path constraint.
• Creating Models for PLLs.
• If PLL has an external bypass in testmode, no action is required.
• Otherwise, replace the PLL model with a reduced model which will propagate test clock to outputs
correctly in testmode (can be a simple gated buffer model) Use only 4-state (01XZ) logic.

11. Cont…
• Creating Models for IOs.
• If IO is synthesizable, no action is required.
• Otherwise, replace each IO model with a reduced model which will propagate the pad signal to inbound
signals correctly in testmode Use only 4-state (01XZ) logic.
• Creating Models for Memories, Other IP.
• If IP has an external bypass in testmode, no action is required.
• If IP is known to make provision for upstream and downstream scan,
• scanwrap –name <IP name>
• Updating the SGDC Constraints File.
• Start with the same constraints file used for Clocks analysis in debug process to define clocks and
constraints use the following command
• clock –name CLK –domain domain1 –value rtz -testclock
• testmode –name top.scanmode –value 0

12. Cont…
• Analyze for Scan Ready
• Check Clock_11 for gated clocks not bypassed in test mode – correct each case.
• Check Async_07 for asynchronous resets not disabled in test mode and correct
• Check Latch_08 messages and correct for Latch Transparency.
• GUI for schematic debugging.

13. Thank You