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DFT-Lecture regarding the JTAG, MBIST introduction to DFT

This document discusses design for test (DFT) and integrated circuit testing. It covers: - The costs of testing including automatic test equipment, test generation software, and the high costs of defects found after manufacturing. - The production test flow including wafer sorting, assembly and packaging tests, burn-in testing, and final testing before product is shipped. - Common fault models like stuck-at faults that are used to model defects and simplify testing. Deductive and concurrent fault simulation techniques are also discussed.

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24 June 2020 Design For Test (DFT) Dr. Adam Teman EnICS Labs, Bar-Ilan University
June 24, 2020 © Adam Teman, Overview 2
Introduction Introduction Testing DFT BIST JTAG
June 24, 2020 © Adam Teman, Testing vs. Verification Verification Testing Verifies correctness of design. Verifies correctness of manufactured hardware. Performed by simulation, h/w emulation or formal methods. Two part process: 1) Test generation – SW process executed once during design 2) Test application – electrical tests applied to hardware Performed once prior to manufacturing Test application performed on every manufactured device Responsible for quality of design Responsible for quality of devices 4
June 24, 2020 © Adam Teman, Cost of Testing • Design for testability (DFT) • Hardware design styles or added hardware that reduces test generation complexity • Chip area and performance overhead • Software processes of test • Test generation and fault simulation • Test programming and debugging • Manufacturing test • Automatic test equipment (ATE) capital cost • ~$5M initial cost + ~$2M per year • Test center operational cost • ~5 cent/second (~$1.5M/year for 24hour operation) 5 Teradyne UltraFLEXplus Source: Teradyne
June 24, 2020 © Adam Teman, Cost of NOT Testing • Cost of defective ICs • IC $ • IC on a PCB (printed circuit board) $$ • IC on a PCB in a system $$$ • IC on a PCB in a system in field $$$$ ….or more • The most expensive defect is the one that wasn’t detected inline • Detect defective parts as soon as possible! Source: Easy Pace Learning
June 24, 2020 © Adam Teman, Production Testing • Testing after chip fabrication in order to detect manufacturing defects that may impact functionality or electrical parameters. • Manufacturing test ideally would check every node in the circuit to prove it is operational.
June 24, 2020 © Adam Teman, Production Test Flow Test Patterns Ship to Customers Yield Improvement Diagnostics and Yield learning
June 24, 2020 © Adam Teman, Production Test Flow • Wafer level testing (Wafer Sort) • Assembly & Packaging • Open/Short test • Packaged device test • Burn-In (@ elevated voltage and temperature) • Final Test (pass/fail) and Bin Sorting • Parametric Tests (voltage, temperature and clock) • Shmoo plot
June 24, 2020 © Adam Teman, Wafer Sort • Wafer sort or probe test • Done before wafer is scribed and cut into chips • Includes test site characterization – specific test devices are checked with specific patterns to measure gate threshold, poly sheet resistance, etc. • Probe card • Custom built PCB to allow performing wafer sort • Modern probe cards can test an entire 12" wafer with one touchdown • Can contact several dies in parallel (~1-16) • Camera in the wafer prober allows alignment 10 Source: Synergie-CAD Source: Anysilicon
June 24, 2020 © Adam Teman, Electrical Testing • DC Parametric Tests • DC contact test - Calculates pin resistance • Power consumption test - Measure max current at worst case temperature • Output short circuit test - Measure current driven when output short circuited • Output drive current test - Measure current for ‘1’ and ‘0’ outputs • Threshold test - Measure VIH, VIL of input pads • AC Parametric Tests • Rise/Fall time tests • Setup/Hold time tests • Propagation delay tests 11
June 24, 2020 © Adam Teman, Burn-in or Stress Test • Process: • Subject chips to high temperature and over-voltage supply, while running production tests • For example: 125C for 168 hours • Catches: • Infant mortality cases – these are damaged or weak (low reliability) chips that will fail in the first few days of operation – burn-in causes bad devices to fail before they are shipped to customers • Freak failures – devices having same failure mechanisms as reliable devices 12 The well known “Bath Tub Curve” Source: wikipedia
June 24, 2020 © Adam Teman, Yield & Cost • Die Yield = # 𝑔𝑜𝑜𝑑 𝑑𝑖𝑒𝑠 # 𝑚𝑎𝑛𝑢𝑓𝑎𝑐𝑡𝑢𝑟𝑒𝑑 𝑑𝑖𝑒𝑠 ≈ 1 + 𝐷 ∙ 𝐴 𝛼 −𝛼 • D – Defect Density – average number of defects per unit of chip area • A – Chip area, 𝛼 – Clustering Factor • ex. AxD=1, 𝛼=0.5 →Y=0.58 • 𝐷𝑖𝑒 𝐶𝑜𝑠𝑡 = 𝑊𝑎𝑓𝑒𝑟 𝐶𝑜𝑠𝑡 𝐷𝑖𝑒𝑠 𝑝𝑒𝑟 𝑊𝑎𝑓𝑒𝑟 ∗𝐷𝑖𝑒 𝑌𝑖𝑒𝑙𝑑 • 𝐼𝐶 𝐶𝑜𝑠𝑡 = 𝐷𝑖𝑒 𝐶𝑜𝑠𝑡+𝑇𝑒𝑠𝑡𝑖𝑛𝑔 𝐶𝑜𝑠𝑡+𝑃𝑎𝑐𝑘𝑎𝑔𝑖𝑛𝑔 𝐶𝑜𝑠𝑡 𝐹𝑖𝑛𝑎𝑙 𝑇𝑒𝑠𝑡 𝑌𝑖𝑒𝑙𝑑 • Defect Level (DL) • The ratio of faulty chips among the chips that pass test, measured in DPM (<<500 DPM) 𝐷𝐿 = 1 − 𝑌 1−𝐹𝐶 , 0 < 𝐷𝐿 < 1 − 𝑌
The Testing Process 14 Introduction Testing DFT BIST JTAG
June 24, 2020 © Adam Teman, Various Processes During Testing • Fault Modeling • Abstract the physical defects and define a suitable logical fault model • Limits/simplifies the scope of test generation • Test Generation • Giving a circuit and a set of faults F, determine a set of test vectors T that detects all faults in F. • Fault Simulation • Given a circuit, a set of faults F, and a set of test vectors T, determine the faults in F that are tested by the vectors in T. • Design for Testibility (DFT) • Formulate a set of design rules that result in a circuit that will be easily testable.
June 24, 2020 © Adam Teman, Defects – Faults – Errors • Defect: physical phenomenon • A defect is the unintended difference between the implemented hardware and its intended design. • Defects are due to shorts, opens, etc., during manufacturing or throughout the lifetime of a device. • Fault: abstract representation • A fault is a model of the influence of the defect on the circuit operation (e.g., a node is stuck at “0” or “1”) • Error: operational result • An error is the incorrect circuit response (wrong output signal) under the presence of faults (or design errors).
June 24, 2020 © Adam Teman, Defects – Faults – Errors • Different types of defects may cause the same fault • Different types of faults may cause the same error 17
June 24, 2020 © Adam Teman, Why do we need a Fault Model? • The number of physical defects in a chip can be way too large • Difficult to count and analyze all possible faults • Fault models abstract away physical defects into a logical model • Drastically reduce the number of faults to be considered • Enable test generation and fault simulation • Enable evaluation of fault coverage and comparison of test results • Fault models can be done at various levels of abstraction to trade off accuracy vs. number of possible faults • e.g., behavioral, functional, structural, switch-level, geometric 18
June 24, 2020 © Adam Teman, Commonly used Fault Models • Stuck At Fault • Assume all failures cause nodes to be “stuck-at” 0 or 1 • Static model (as opposed to at-speed test) • Independent of process technology • Not quite true, but works well in practice • Transition/Delay Fault • “Slow to Rise” or “Slow to Fall” fault • Signal propagation delays that are outside the circuit specifications • Dynamic model, tested at-speed • Other fault models • Transistor opens and shorts • Bridging faults
June 24, 2020 © Adam Teman, Stuck-at Fault (s/0, s/1) • Three properties define a single stuck-at fault • Only one line is faulty, fanout stems and branches considered separate lines • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has: • 12 fault sites • 24 single stuck-at faults 20
June 24, 2020 © Adam Teman, Stuck-at Fault Testing Examples • 2-input AND: • We have six possible faults: A/0, A/1, B/0, B/1, F/0, F1 • But we only need three test vectors to test them: • 01: detects A/1, F/1 • 10: detects B/1, F/1 • 11: detects A/0, B/0, F/0 • An N-input AND gate only needs N+1 test vectors • 3-input XOR: • We can detect all single stuck-at faults with 000 and 111 • 000: tests all inputs s-a-1, and output s-a-1 • 111: tests all inputs s-a-0, and output s-a-0 • An N-input XOR gate needs only 2 test vectors! 21
June 24, 2020 © Adam Teman, Fault Equivalence and Collapsing • Number of fault sites in a Boolean gate circuit is • #PI + #gates + # (fanout branches) • Fault equivalence: • Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. • e.g., input s-a-0 and output s-a-0 in an AND gate. • Equivalent faults can be collapsed into a single fault. 22 20 Collapse ratio = ── = 0.625 32 Faults in red removed by equivalence collapsing
June 24, 2020 © Adam Teman, Fault Dominance • If all tests of some fault f1 detect another fault f2, then f2 is said to dominate f1. • i.e., the tests for f1 are a subset of those for f2 • We can then remove (collapse) f2 • i.e., testing f1 is sufficient to test f2 23 Faults in red removed by equivalence collapsing Faults in blue removed by dominance collapsing
June 24, 2020 © Adam Teman, Fault Simulation and Coverage • Given a circuit, a set of test vectors T, and a fault list F, fault simulation computes the faults in F detected by T. • Fault Coverage is the measure of the ability of a test to detect a given defect 𝐹𝑎𝑢𝑙𝑡 𝐶𝑜𝑣𝑒𝑟𝑎𝑔𝑒 = 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝐷𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝐹𝑎𝑢𝑙𝑡𝑠 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑃𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝐹𝑎𝑢𝑙𝑡𝑠 • Trivial Approach: Serial Fault Simulation • For each fault in the fault list, inject one fault to the netlist • Simulate the modified netlist and compare response to fault-free netlist • Not feasible! Requires huge number of simulations. 26
June 24, 2020 © Adam Teman, • For each test vector mark the faults that it detects at each line. • Propagate through the circuit in event-driven fashion. • Let’s start with the simple example of a 2-input AND Gate • If one of the inputs shouldn’t change, we mark it with a “bar” and it is equivalent to the set difference: Deductive Fault Simulation 27 1 1 1 A B Z LA={A/0} LB={B/0} LZ=LA U LB U {Z/0} = {A/0, B/0, Z/0} 0 1 0 A B Z LA={A/1} LB={B/0} LZ=LA U 𝐿𝐵 U {Z/1} = (LA-LB) U {Z/1} ={A/0, Z/0}
June 24, 2020 © Adam Teman, Deductive Fault Simulation 28 LA={A/1}, LB={B/0} , LC={C/1} , LD={D/0} , LE={E/1} LF={F/0} U (LA-LB)={F/0, A/1} LG={G/0} U (LD-LC)={G/0, D/0} LH={H/0} U LF U LG = {H/0, F/0, A/1, G/0, D/0} LZ={Z/1} U (LH – LE)= {Z/1, H/0, F/0, A/1, G/0, D/0} So T1= {01010} was able to detect 6 faults!
June 24, 2020 © Adam Teman, Concurrent Fault Simulation • Concurrently simulate the fault-free and faulty versions of the circuit for a given vector. • For every gate, we maintain a concurrent fault list: • <fault : input values : output value> • Example of a 2-input AND gate: 29 0 1 0 A B Z A/1 : 11 : 1 B/0 : 00 : 0 Z/1 : 01 : 1
June 24, 2020 © Adam Teman, Concurrent Fault Simulation 30 A/1 : 11 : 1 B/0 : 00 : 0 E/1 : 01 : 1 Gate G1 C/1 : 11 : 1 D/0 : 00 : 0 F/0 : 00 : 0 Gate G2 E/1 : 11 : 0 F/0 : 00 : 1 G/0 : 01 : 0 Gate G3 Local Response From G1 A/1 : 11 : 0 From G2 E/1 : 11 : 0 D/0 : 00 : 1 F/0 : 00 : 1
June 24, 2020 © Adam Teman, Test Vector Generation • So we saw how to run fault simulation and recognize all the faults that can be detected by a given vector. • Therefore, we can: • Randomly choose a test vector • Collect all faults detected by the same vector • Reduce fault list (dictionary) • Repeat until all faults are detected • However, how can we find the test vector for testing a specific fault? • The general approach has three stages: • Control: Excite the fault • Observe: Propagate the fault through the network all the way to the output • Detect: Output value of good and faulty circuit 31
June 24, 2020 © Adam Teman, D-Algorithm Concept (Roth, 1966) • Fault Sensitization (=Assignment) • Assert the opposite of the fault at the fault site. • This creates a D or D’ • Fault Propagation (=Forward Drive) • Propagate the fault to a primary output • Line Justification (=Backward Trace) • Find the primary inputs that will ensure this propagation 32 D 1 0 X D D 1 D 1 0 0 0
June 24, 2020 © Adam Teman, Points to note • Path sensitization is not as simple as the example shows • Fanout and reconvergence may cause conflicts during backward trace • This has led to the development of many sophisticated algorithms • PODEM (Goel, 1981) • FAN (Fujiwara, 1986) • Others • Test generation is slower than fault simulation 33
Design For Test Introduction Testing DFT BIST JTAG
June 24, 2020 © Adam Teman, Controllability and Observability • DFT Mantra • To provide controllability and observability • Controllability • The ability to bring a system to any given state. • In chip design, this means that any desired value can be produced at the internal signals of the circuit by controlling the primary inputs,. • Observability • The ability to evaluate what the current state of the system is. • In chip design, this means that any internal signal can be propagated to a primary output. • Combinational circuits have inherently high controllability and observability, but the opposite is true for sequential circuits.
June 24, 2020 © Adam Teman, Design For Test • Embedding testing circuitry along with the functional Circuit Under Test (CUT) aiming to alleviate the testing process and to enhance testability • We can assist testing by applying embedded Design For Testability (DFT) techniques, e.g. • Adding control and observation points • Scan Chains • Built-In Self Test (BIST)
June 24, 2020 © Adam Teman, The sequential circuit problem • Sequential designs have limited controllability and observability. • We can gain controllability/observability by turning our sequential circuits into a collection of combinatorial circuits. 37
June 24, 2020 © Adam Teman, Scan Chain Insertion • Replace all flip flops with scan flip flops • FFs become shift register in test mode • Control the scan chains with new ports: • Scan In – input to the scan chain • Scan Out – output from the scan chain • Scan Enable – toggle between test and operational mode 38 Source: Cadence
June 24, 2020 © Adam Teman, Scan Chain Insertion • Now we can serially “scan-in” the sanitization vector. 39
June 24, 2020 © Adam Teman, Scan Testing Protocol • Enable scan (SE=1) • Shift in state vector • Disable scan (SE=0) • Toggle Clock to exercise fault (“Capture”) • Enable scan (SE=1) • Shift out result vector 40
June 24, 2020 © Adam Teman, Test Patterns Overlap • Scanning out of previous pattern overlaps scanning in of next - for all but first and last patterns in the test program. 41
June 24, 2020 © Adam Teman, Scan Chains Implementation • Implementation Considerations • The scan clock is typically slower than operational mode (e.g. 100-200 MHz) • Usually a number of parallel scan chains are implemented • Special care needs to be taken to avoid undesirable conditions during scan, e.g. bus contentions, resets, clock gates, etc. • One potential problem associated with scan chains is a temporary excessive current draw due to many flops toggling at the same clock • Additional usages: • Debug – scan chain provides visibility to the full internal state of the circuit (hence a long scan chain mode is very useable) • Reset propagation
June 24, 2020 © Adam Teman, Test Pattern Compression • Larger designs need to use embedded compression to reduce the pattern volume and test time • Compression works by dividing the chip’s scan chains into smaller balanced chains that are connected between a decompressor and a compactor • The tester patterns are smaller by a couple orders of magnitude, and only a few primary I/Os need to be connected to the external tester
June 24, 2020 © Adam Teman, AC Scan (at-speed test) • Used to verify: • Transition Faults • Delay Faults • A path delay fault requires a pair of subsequent vectors to be detected • The first test vector initializes the circuit • The second test vector activates the path under test (I) Initialization (II) Launch & Capture Source: Atrenta
June 24, 2020 © Adam Teman, AC Scan Timing Slow Shift At-Speed Launch/Capture
June 24, 2020 © Adam Teman, IDDQ Test • Tests quiescent power consumption • Many fabrication defects cause higher static power consumption (orders of magnitude) • Difficult for deep sub-micron process due to high leakage current • Design Considerations • Pure static logic design • Buses • No floating nodes • No driver conflicts • No pull-up or pulldown resistors • Separate power supply for analog • Advantages • Covers non-stuck-at faults • Cheap test equipment • Few test vectors • Disadvantages • Slow current measurement • Difficult to determine proper IDDQ threshold • Not practicable for deep sub- micron
Built-In Self Test Introduction Testing DFT BIST JTAG
June 24, 2020 © Adam Teman, Built-in Self-Test • Testing with an ATE is expensive • We need to stream in a test vector and stream out the result for evaluation. • Instead, add dedicated hardware for test generation and response evaluation • Done on chip for specific blocks (such as memory) • Hardware overhead, but runs much faster and can be done in the field. • Can run at-speed CUT Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE Pattern Generator Response Analyzer CUT PASS/FAIL Test control logic CK BIST Enable
June 24, 2020 © Adam Teman, BIST Architecture • Pattern generator • RAM or ROM with stored deterministic patterns • Counter • Random pattern generator • Response Compactor • Compactor – reduces size of output for comparison to ROM • Output Response Analyzer (ORA) generates pass/fail 49 Source: Trivedi, et al.
June 24, 2020 © Adam Teman, Linear Feedback Shift Register (LSFR) • Pseudo-Random Pattern Generator • Pattern depends on: • Feedback function (XOR, XNOR) • Tap Selection • Seed (initial value) • Properties • Taps described by characteristic polynomial • Primitive Polynomials cannot be factored. • Primitive or Maximal Length provide 2n-1 unique values • Cannot initialize to 0000 (1111 for XNOR) 50 Source: EDN.com
June 24, 2020 © Adam Teman, Response Compaction • A response compactor (not compressor) reduces the response into a signature before comparison. • The golden signature is stored on-chip. • Similar to cyclic redundancy check (CRC) • This is basically a many-to-one mapping • Can cause aliasing (low probability) • Two approaches • Signature Analyzer: compact a serial bit stream into an LSFR based compactor. • Multiple-input Signature Register (MISR): compact several bit streams in parallel 51 Source: EDN.com Source: Agarwal & Bushnell
June 24, 2020 © Adam Teman, Memory Built In Self Test (MBIST) • Many arrays (10’s or 100’s) of different types and different sizes are scattered in the device • Memory BIST is used to test these arrays • Implements commonly used testing algorithms • e.g., Zero-One, Checkboard, GALPAT, Walking 1/0, March, etc. • Built-in Self Repair (BISR) • To avoid yield loss redundant or spare rows and columns are added. • Memory repair swaps out faulty rows and/or columns for spare ones Source: Design-reuse
June 24, 2020 © Adam Teman, Logic Built In Self Test (LBIST) • In built-in self testing the test vectors are generated by an embedded circuit under control of the BIST Controller • The circuit responses are compacted to a signature • After the completion of the test, the signature is compared to the expected result to determine a PASS/FAIL result
Boundary Scan IEEE STD 1149.1 Introduction Testing DFT BIST JTAG
June 24, 2020 © Adam Teman, What about board testing? • Testing boards is also difficult • Need to verify solder joints are good • Drive a pin to 0, then to 1 • Check that all connected pins get the values • Through-hold boards used “bed of nails” • SMT and BGA boards cannot easily contact pins • JTAG (Joint Test Action Group) Standard • Build capability of observing and controlling pins into each chip to make board test easier • IEEE 1149.1 Source: Medium
June 24, 2020 © Adam Teman, Boundary Scan • Used for board (PCB) level testing • Used for debugging/controlling on-chip blocks • Implementation • TAP controller (Test Access Port) • 4 dedicated IO pins (5th is optional) • TCK test clock • TMS test mode select • TDI serial test data in • TDO serial test data out • TRST test reset (optional) • Allows to drive and sample the device IO pins • Implementation is described in BSDL (Boundary Scan Description Language)
June 24, 2020 © Adam Teman, 1149.1 Wrapper • Test Data Registers • Boundary Scan Register • Bypass Register • Instruction Register • Device-ID Register • Design Specific Registers • Important Test Modes • EXTEST: test the interconnection between devices • BYPASS: Forward test to next chip • INTEST: Test the internal logic of a chip 57 Source: EMBECOSM
June 24, 2020 © Adam Teman, Main References • Yehuda Rudin, DFT Lecture, 2018 • Sagi Fisher, DFP Lecture, 2017 • M. Bushnell, V. Agrawal, VLSI Testing Course, U. Auburn • M. Bushnell, V. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Springer 2005 • I. Sengupta, VLSI Physical Design Course, IIT Kharagpur (NPTEL) • A. Tenca, W. Ruggiero, PCS5030, Univ. Sao Paulo 58

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DFT-Lecture regarding the JTAG, MBIST introduction to DFT

  • 1.
    24 June 2020 DesignFor Test (DFT) Dr. Adam Teman EnICS Labs, Bar-Ilan University
  • 2.
    June 24, 2020 ©Adam Teman, Overview 2
  • 3.
  • 4.
    June 24, 2020 ©Adam Teman, Testing vs. Verification Verification Testing Verifies correctness of design. Verifies correctness of manufactured hardware. Performed by simulation, h/w emulation or formal methods. Two part process: 1) Test generation – SW process executed once during design 2) Test application – electrical tests applied to hardware Performed once prior to manufacturing Test application performed on every manufactured device Responsible for quality of design Responsible for quality of devices 4
  • 5.
    June 24, 2020 ©Adam Teman, Cost of Testing • Design for testability (DFT) • Hardware design styles or added hardware that reduces test generation complexity • Chip area and performance overhead • Software processes of test • Test generation and fault simulation • Test programming and debugging • Manufacturing test • Automatic test equipment (ATE) capital cost • ~$5M initial cost + ~$2M per year • Test center operational cost • ~5 cent/second (~$1.5M/year for 24hour operation) 5 Teradyne UltraFLEXplus Source: Teradyne
  • 6.
    June 24, 2020 ©Adam Teman, Cost of NOT Testing • Cost of defective ICs • IC $ • IC on a PCB (printed circuit board) $$ • IC on a PCB in a system $$$ • IC on a PCB in a system in field $$$$ ….or more • The most expensive defect is the one that wasn’t detected inline • Detect defective parts as soon as possible! Source: Easy Pace Learning
  • 7.
    June 24, 2020 ©Adam Teman, Production Testing • Testing after chip fabrication in order to detect manufacturing defects that may impact functionality or electrical parameters. • Manufacturing test ideally would check every node in the circuit to prove it is operational.
  • 8.
    June 24, 2020 ©Adam Teman, Production Test Flow Test Patterns Ship to Customers Yield Improvement Diagnostics and Yield learning
  • 9.
    June 24, 2020 ©Adam Teman, Production Test Flow • Wafer level testing (Wafer Sort) • Assembly & Packaging • Open/Short test • Packaged device test • Burn-In (@ elevated voltage and temperature) • Final Test (pass/fail) and Bin Sorting • Parametric Tests (voltage, temperature and clock) • Shmoo plot
  • 10.
    June 24, 2020 ©Adam Teman, Wafer Sort • Wafer sort or probe test • Done before wafer is scribed and cut into chips • Includes test site characterization – specific test devices are checked with specific patterns to measure gate threshold, poly sheet resistance, etc. • Probe card • Custom built PCB to allow performing wafer sort • Modern probe cards can test an entire 12" wafer with one touchdown • Can contact several dies in parallel (~1-16) • Camera in the wafer prober allows alignment 10 Source: Synergie-CAD Source: Anysilicon
  • 11.
    June 24, 2020 ©Adam Teman, Electrical Testing • DC Parametric Tests • DC contact test - Calculates pin resistance • Power consumption test - Measure max current at worst case temperature • Output short circuit test - Measure current driven when output short circuited • Output drive current test - Measure current for ‘1’ and ‘0’ outputs • Threshold test - Measure VIH, VIL of input pads • AC Parametric Tests • Rise/Fall time tests • Setup/Hold time tests • Propagation delay tests 11
  • 12.
    June 24, 2020 ©Adam Teman, Burn-in or Stress Test • Process: • Subject chips to high temperature and over-voltage supply, while running production tests • For example: 125C for 168 hours • Catches: • Infant mortality cases – these are damaged or weak (low reliability) chips that will fail in the first few days of operation – burn-in causes bad devices to fail before they are shipped to customers • Freak failures – devices having same failure mechanisms as reliable devices 12 The well known “Bath Tub Curve” Source: wikipedia
  • 13.
    June 24, 2020 ©Adam Teman, Yield & Cost • Die Yield = # 𝑔𝑜𝑜𝑑 𝑑𝑖𝑒𝑠 # 𝑚𝑎𝑛𝑢𝑓𝑎𝑐𝑡𝑢𝑟𝑒𝑑 𝑑𝑖𝑒𝑠 ≈ 1 + 𝐷 ∙ 𝐴 𝛼 −𝛼 • D – Defect Density – average number of defects per unit of chip area • A – Chip area, 𝛼 – Clustering Factor • ex. AxD=1, 𝛼=0.5 →Y=0.58 • 𝐷𝑖𝑒 𝐶𝑜𝑠𝑡 = 𝑊𝑎𝑓𝑒𝑟 𝐶𝑜𝑠𝑡 𝐷𝑖𝑒𝑠 𝑝𝑒𝑟 𝑊𝑎𝑓𝑒𝑟 ∗𝐷𝑖𝑒 𝑌𝑖𝑒𝑙𝑑 • 𝐼𝐶 𝐶𝑜𝑠𝑡 = 𝐷𝑖𝑒 𝐶𝑜𝑠𝑡+𝑇𝑒𝑠𝑡𝑖𝑛𝑔 𝐶𝑜𝑠𝑡+𝑃𝑎𝑐𝑘𝑎𝑔𝑖𝑛𝑔 𝐶𝑜𝑠𝑡 𝐹𝑖𝑛𝑎𝑙 𝑇𝑒𝑠𝑡 𝑌𝑖𝑒𝑙𝑑 • Defect Level (DL) • The ratio of faulty chips among the chips that pass test, measured in DPM (<<500 DPM) 𝐷𝐿 = 1 − 𝑌 1−𝐹𝐶 , 0 < 𝐷𝐿 < 1 − 𝑌
  • 14.
  • 15.
    June 24, 2020 ©Adam Teman, Various Processes During Testing • Fault Modeling • Abstract the physical defects and define a suitable logical fault model • Limits/simplifies the scope of test generation • Test Generation • Giving a circuit and a set of faults F, determine a set of test vectors T that detects all faults in F. • Fault Simulation • Given a circuit, a set of faults F, and a set of test vectors T, determine the faults in F that are tested by the vectors in T. • Design for Testibility (DFT) • Formulate a set of design rules that result in a circuit that will be easily testable.
  • 16.
    June 24, 2020 ©Adam Teman, Defects – Faults – Errors • Defect: physical phenomenon • A defect is the unintended difference between the implemented hardware and its intended design. • Defects are due to shorts, opens, etc., during manufacturing or throughout the lifetime of a device. • Fault: abstract representation • A fault is a model of the influence of the defect on the circuit operation (e.g., a node is stuck at “0” or “1”) • Error: operational result • An error is the incorrect circuit response (wrong output signal) under the presence of faults (or design errors).
  • 17.
    June 24, 2020 ©Adam Teman, Defects – Faults – Errors • Different types of defects may cause the same fault • Different types of faults may cause the same error 17
  • 18.
    June 24, 2020 ©Adam Teman, Why do we need a Fault Model? • The number of physical defects in a chip can be way too large • Difficult to count and analyze all possible faults • Fault models abstract away physical defects into a logical model • Drastically reduce the number of faults to be considered • Enable test generation and fault simulation • Enable evaluation of fault coverage and comparison of test results • Fault models can be done at various levels of abstraction to trade off accuracy vs. number of possible faults • e.g., behavioral, functional, structural, switch-level, geometric 18
  • 19.
    June 24, 2020 ©Adam Teman, Commonly used Fault Models • Stuck At Fault • Assume all failures cause nodes to be “stuck-at” 0 or 1 • Static model (as opposed to at-speed test) • Independent of process technology • Not quite true, but works well in practice • Transition/Delay Fault • “Slow to Rise” or “Slow to Fall” fault • Signal propagation delays that are outside the circuit specifications • Dynamic model, tested at-speed • Other fault models • Transistor opens and shorts • Bridging faults
  • 20.
    June 24, 2020 ©Adam Teman, Stuck-at Fault (s/0, s/1) • Three properties define a single stuck-at fault • Only one line is faulty, fanout stems and branches considered separate lines • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has: • 12 fault sites • 24 single stuck-at faults 20
  • 21.
    June 24, 2020 ©Adam Teman, Stuck-at Fault Testing Examples • 2-input AND: • We have six possible faults: A/0, A/1, B/0, B/1, F/0, F1 • But we only need three test vectors to test them: • 01: detects A/1, F/1 • 10: detects B/1, F/1 • 11: detects A/0, B/0, F/0 • An N-input AND gate only needs N+1 test vectors • 3-input XOR: • We can detect all single stuck-at faults with 000 and 111 • 000: tests all inputs s-a-1, and output s-a-1 • 111: tests all inputs s-a-0, and output s-a-0 • An N-input XOR gate needs only 2 test vectors! 21
  • 22.
    June 24, 2020 ©Adam Teman, Fault Equivalence and Collapsing • Number of fault sites in a Boolean gate circuit is • #PI + #gates + # (fanout branches) • Fault equivalence: • Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. • e.g., input s-a-0 and output s-a-0 in an AND gate. • Equivalent faults can be collapsed into a single fault. 22 20 Collapse ratio = ── = 0.625 32 Faults in red removed by equivalence collapsing
  • 23.
    June 24, 2020 ©Adam Teman, Fault Dominance • If all tests of some fault f1 detect another fault f2, then f2 is said to dominate f1. • i.e., the tests for f1 are a subset of those for f2 • We can then remove (collapse) f2 • i.e., testing f1 is sufficient to test f2 23 Faults in red removed by equivalence collapsing Faults in blue removed by dominance collapsing
  • 24.
    June 24, 2020 ©Adam Teman, Fault Simulation and Coverage • Given a circuit, a set of test vectors T, and a fault list F, fault simulation computes the faults in F detected by T. • Fault Coverage is the measure of the ability of a test to detect a given defect 𝐹𝑎𝑢𝑙𝑡 𝐶𝑜𝑣𝑒𝑟𝑎𝑔𝑒 = 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝐷𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝐹𝑎𝑢𝑙𝑡𝑠 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑃𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝐹𝑎𝑢𝑙𝑡𝑠 • Trivial Approach: Serial Fault Simulation • For each fault in the fault list, inject one fault to the netlist • Simulate the modified netlist and compare response to fault-free netlist • Not feasible! Requires huge number of simulations. 26
  • 25.
    June 24, 2020 ©Adam Teman, • For each test vector mark the faults that it detects at each line. • Propagate through the circuit in event-driven fashion. • Let’s start with the simple example of a 2-input AND Gate • If one of the inputs shouldn’t change, we mark it with a “bar” and it is equivalent to the set difference: Deductive Fault Simulation 27 1 1 1 A B Z LA={A/0} LB={B/0} LZ=LA U LB U {Z/0} = {A/0, B/0, Z/0} 0 1 0 A B Z LA={A/1} LB={B/0} LZ=LA U 𝐿𝐵 U {Z/1} = (LA-LB) U {Z/1} ={A/0, Z/0}
  • 26.
    June 24, 2020 ©Adam Teman, Deductive Fault Simulation 28 LA={A/1}, LB={B/0} , LC={C/1} , LD={D/0} , LE={E/1} LF={F/0} U (LA-LB)={F/0, A/1} LG={G/0} U (LD-LC)={G/0, D/0} LH={H/0} U LF U LG = {H/0, F/0, A/1, G/0, D/0} LZ={Z/1} U (LH – LE)= {Z/1, H/0, F/0, A/1, G/0, D/0} So T1= {01010} was able to detect 6 faults!
  • 27.
    June 24, 2020 ©Adam Teman, Concurrent Fault Simulation • Concurrently simulate the fault-free and faulty versions of the circuit for a given vector. • For every gate, we maintain a concurrent fault list: • <fault : input values : output value> • Example of a 2-input AND gate: 29 0 1 0 A B Z A/1 : 11 : 1 B/0 : 00 : 0 Z/1 : 01 : 1
  • 28.
    June 24, 2020 ©Adam Teman, Concurrent Fault Simulation 30 A/1 : 11 : 1 B/0 : 00 : 0 E/1 : 01 : 1 Gate G1 C/1 : 11 : 1 D/0 : 00 : 0 F/0 : 00 : 0 Gate G2 E/1 : 11 : 0 F/0 : 00 : 1 G/0 : 01 : 0 Gate G3 Local Response From G1 A/1 : 11 : 0 From G2 E/1 : 11 : 0 D/0 : 00 : 1 F/0 : 00 : 1
  • 29.
    June 24, 2020 ©Adam Teman, Test Vector Generation • So we saw how to run fault simulation and recognize all the faults that can be detected by a given vector. • Therefore, we can: • Randomly choose a test vector • Collect all faults detected by the same vector • Reduce fault list (dictionary) • Repeat until all faults are detected • However, how can we find the test vector for testing a specific fault? • The general approach has three stages: • Control: Excite the fault • Observe: Propagate the fault through the network all the way to the output • Detect: Output value of good and faulty circuit 31
  • 30.
    June 24, 2020 ©Adam Teman, D-Algorithm Concept (Roth, 1966) • Fault Sensitization (=Assignment) • Assert the opposite of the fault at the fault site. • This creates a D or D’ • Fault Propagation (=Forward Drive) • Propagate the fault to a primary output • Line Justification (=Backward Trace) • Find the primary inputs that will ensure this propagation 32 D 1 0 X D D 1 D 1 0 0 0
  • 31.
    June 24, 2020 ©Adam Teman, Points to note • Path sensitization is not as simple as the example shows • Fanout and reconvergence may cause conflicts during backward trace • This has led to the development of many sophisticated algorithms • PODEM (Goel, 1981) • FAN (Fujiwara, 1986) • Others • Test generation is slower than fault simulation 33
  • 32.
    Design For Test IntroductionTesting DFT BIST JTAG
  • 33.
    June 24, 2020 ©Adam Teman, Controllability and Observability • DFT Mantra • To provide controllability and observability • Controllability • The ability to bring a system to any given state. • In chip design, this means that any desired value can be produced at the internal signals of the circuit by controlling the primary inputs,. • Observability • The ability to evaluate what the current state of the system is. • In chip design, this means that any internal signal can be propagated to a primary output. • Combinational circuits have inherently high controllability and observability, but the opposite is true for sequential circuits.
  • 34.
    June 24, 2020 ©Adam Teman, Design For Test • Embedding testing circuitry along with the functional Circuit Under Test (CUT) aiming to alleviate the testing process and to enhance testability • We can assist testing by applying embedded Design For Testability (DFT) techniques, e.g. • Adding control and observation points • Scan Chains • Built-In Self Test (BIST)
  • 35.
    June 24, 2020 ©Adam Teman, The sequential circuit problem • Sequential designs have limited controllability and observability. • We can gain controllability/observability by turning our sequential circuits into a collection of combinatorial circuits. 37
  • 36.
    June 24, 2020 ©Adam Teman, Scan Chain Insertion • Replace all flip flops with scan flip flops • FFs become shift register in test mode • Control the scan chains with new ports: • Scan In – input to the scan chain • Scan Out – output from the scan chain • Scan Enable – toggle between test and operational mode 38 Source: Cadence
  • 37.
    June 24, 2020 ©Adam Teman, Scan Chain Insertion • Now we can serially “scan-in” the sanitization vector. 39
  • 38.
    June 24, 2020 ©Adam Teman, Scan Testing Protocol • Enable scan (SE=1) • Shift in state vector • Disable scan (SE=0) • Toggle Clock to exercise fault (“Capture”) • Enable scan (SE=1) • Shift out result vector 40
  • 39.
    June 24, 2020 ©Adam Teman, Test Patterns Overlap • Scanning out of previous pattern overlaps scanning in of next - for all but first and last patterns in the test program. 41
  • 40.
    June 24, 2020 ©Adam Teman, Scan Chains Implementation • Implementation Considerations • The scan clock is typically slower than operational mode (e.g. 100-200 MHz) • Usually a number of parallel scan chains are implemented • Special care needs to be taken to avoid undesirable conditions during scan, e.g. bus contentions, resets, clock gates, etc. • One potential problem associated with scan chains is a temporary excessive current draw due to many flops toggling at the same clock • Additional usages: • Debug – scan chain provides visibility to the full internal state of the circuit (hence a long scan chain mode is very useable) • Reset propagation
  • 41.
    June 24, 2020 ©Adam Teman, Test Pattern Compression • Larger designs need to use embedded compression to reduce the pattern volume and test time • Compression works by dividing the chip’s scan chains into smaller balanced chains that are connected between a decompressor and a compactor • The tester patterns are smaller by a couple orders of magnitude, and only a few primary I/Os need to be connected to the external tester
  • 42.
    June 24, 2020 ©Adam Teman, AC Scan (at-speed test) • Used to verify: • Transition Faults • Delay Faults • A path delay fault requires a pair of subsequent vectors to be detected • The first test vector initializes the circuit • The second test vector activates the path under test (I) Initialization (II) Launch & Capture Source: Atrenta
  • 43.
    June 24, 2020 ©Adam Teman, AC Scan Timing Slow Shift At-Speed Launch/Capture
  • 44.
    June 24, 2020 ©Adam Teman, IDDQ Test • Tests quiescent power consumption • Many fabrication defects cause higher static power consumption (orders of magnitude) • Difficult for deep sub-micron process due to high leakage current • Design Considerations • Pure static logic design • Buses • No floating nodes • No driver conflicts • No pull-up or pulldown resistors • Separate power supply for analog • Advantages • Covers non-stuck-at faults • Cheap test equipment • Few test vectors • Disadvantages • Slow current measurement • Difficult to determine proper IDDQ threshold • Not practicable for deep sub- micron
  • 45.
    Built-In Self Test IntroductionTesting DFT BIST JTAG
  • 46.
    June 24, 2020 ©Adam Teman, Built-in Self-Test • Testing with an ATE is expensive • We need to stream in a test vector and stream out the result for evaluation. • Instead, add dedicated hardware for test generation and response evaluation • Done on chip for specific blocks (such as memory) • Hardware overhead, but runs much faster and can be done in the field. • Can run at-speed CUT Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE Pattern Generator Response Analyzer CUT PASS/FAIL Test control logic CK BIST Enable
  • 47.
    June 24, 2020 ©Adam Teman, BIST Architecture • Pattern generator • RAM or ROM with stored deterministic patterns • Counter • Random pattern generator • Response Compactor • Compactor – reduces size of output for comparison to ROM • Output Response Analyzer (ORA) generates pass/fail 49 Source: Trivedi, et al.
  • 48.
    June 24, 2020 ©Adam Teman, Linear Feedback Shift Register (LSFR) • Pseudo-Random Pattern Generator • Pattern depends on: • Feedback function (XOR, XNOR) • Tap Selection • Seed (initial value) • Properties • Taps described by characteristic polynomial • Primitive Polynomials cannot be factored. • Primitive or Maximal Length provide 2n-1 unique values • Cannot initialize to 0000 (1111 for XNOR) 50 Source: EDN.com
  • 49.
    June 24, 2020 ©Adam Teman, Response Compaction • A response compactor (not compressor) reduces the response into a signature before comparison. • The golden signature is stored on-chip. • Similar to cyclic redundancy check (CRC) • This is basically a many-to-one mapping • Can cause aliasing (low probability) • Two approaches • Signature Analyzer: compact a serial bit stream into an LSFR based compactor. • Multiple-input Signature Register (MISR): compact several bit streams in parallel 51 Source: EDN.com Source: Agarwal & Bushnell
  • 50.
    June 24, 2020 ©Adam Teman, Memory Built In Self Test (MBIST) • Many arrays (10’s or 100’s) of different types and different sizes are scattered in the device • Memory BIST is used to test these arrays • Implements commonly used testing algorithms • e.g., Zero-One, Checkboard, GALPAT, Walking 1/0, March, etc. • Built-in Self Repair (BISR) • To avoid yield loss redundant or spare rows and columns are added. • Memory repair swaps out faulty rows and/or columns for spare ones Source: Design-reuse
  • 51.
    June 24, 2020 ©Adam Teman, Logic Built In Self Test (LBIST) • In built-in self testing the test vectors are generated by an embedded circuit under control of the BIST Controller • The circuit responses are compacted to a signature • After the completion of the test, the signature is compared to the expected result to determine a PASS/FAIL result
  • 52.
    Boundary Scan IEEE STD1149.1 Introduction Testing DFT BIST JTAG
  • 53.
    June 24, 2020 ©Adam Teman, What about board testing? • Testing boards is also difficult • Need to verify solder joints are good • Drive a pin to 0, then to 1 • Check that all connected pins get the values • Through-hold boards used “bed of nails” • SMT and BGA boards cannot easily contact pins • JTAG (Joint Test Action Group) Standard • Build capability of observing and controlling pins into each chip to make board test easier • IEEE 1149.1 Source: Medium
  • 54.
    June 24, 2020 ©Adam Teman, Boundary Scan • Used for board (PCB) level testing • Used for debugging/controlling on-chip blocks • Implementation • TAP controller (Test Access Port) • 4 dedicated IO pins (5th is optional) • TCK test clock • TMS test mode select • TDI serial test data in • TDO serial test data out • TRST test reset (optional) • Allows to drive and sample the device IO pins • Implementation is described in BSDL (Boundary Scan Description Language)
  • 55.
    June 24, 2020 ©Adam Teman, 1149.1 Wrapper • Test Data Registers • Boundary Scan Register • Bypass Register • Instruction Register • Device-ID Register • Design Specific Registers • Important Test Modes • EXTEST: test the interconnection between devices • BYPASS: Forward test to next chip • INTEST: Test the internal logic of a chip 57 Source: EMBECOSM
  • 56.
    June 24, 2020 ©Adam Teman, Main References • Yehuda Rudin, DFT Lecture, 2018 • Sagi Fisher, DFP Lecture, 2017 • M. Bushnell, V. Agrawal, VLSI Testing Course, U. Auburn • M. Bushnell, V. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Springer 2005 • I. Sengupta, VLSI Physical Design Course, IIT Kharagpur (NPTEL) • A. Tenca, W. Ruggiero, PCS5030, Univ. Sao Paulo 58