This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
Design of IEEE 1149.1 Tap Controller IP Core csandit
An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an
established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG
TAP controllers are becoming a delivery and control mechanism for Design For Test. The
objective of this work is to design and implement a TAP controller IP core compatible with
IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test
Mode Persistence controller and its associated logic. This work is expected to serve as a ready
to use module that can be directly inserted in to a new digital IC designs with little
modifications.
DESIGN OF IEEE 1149.1 TAP CONTROLLER IP COREcscpconf
An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG
TAP controllers are becoming a delivery and control mechanism for Design For Test. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
Design of IEEE 1149.1 Tap Controller IP Core csandit
An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an
established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG
TAP controllers are becoming a delivery and control mechanism for Design For Test. The
objective of this work is to design and implement a TAP controller IP core compatible with
IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test
Mode Persistence controller and its associated logic. This work is expected to serve as a ready
to use module that can be directly inserted in to a new digital IC designs with little
modifications.
DESIGN OF IEEE 1149.1 TAP CONTROLLER IP COREcscpconf
An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG
TAP controllers are becoming a delivery and control mechanism for Design For Test. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications.
Data Volume Compression Using BIST to get Low-Power Pseudorandom Test Pattern...IJMTST Journal
This project describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to pattern-count ratios. Furthermore, this proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO based logic BIST (LBIST) infrastructure. The proposed architecture is extended in such that the patterns generated from PRPG is gone through CUT and then to TRA to perform ATE.
Review journal CA pRNG with global loop non-uniform rule controldaraaulia Feryando
CA(Cellular Automaton) adalah pemodelan sistem secara otomatis. Penggunaan CA yang dikombinasi dengan pRNG mampu menghasilkan keacakan yang baik untuk diterapkan pada sebuah prosesor. Pada review jurnal ini, CA pRNG diterapkan pada hardware atau tepatnya pada FPGA.
Scan-Based Delay Measurement Technique Using Signature RegistersIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware...奈良先端大 情報科学研究科
Outsourcing of IC fabrication components has initiated the
potential threat of design tempering using hardware Trojans and also has drawn the attention of government agencies and the semiconductor industry. The added functionality, known as hardware Trojan, poses major detection and isolation challenges. This paper presents a hardware Trojan detection technique that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified LOC test pattern application method is proposed so as to maximize dynamic power consumption of any target segment. The proposed architecture allows activating any target segment of scan chain and keeping others freeze which reduces total circuit switching activity. This helps magnify the Trojan’s contribution to selected segment by increasing dynamic power
consumption. Experimental results for ISCAS89 benchmark circuit demonstrate its effectiveness in side-channel analysis.
Design for Testability in Timely Testing of Vlsi CircuitsIJERA Editor
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self-test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test.
JTAG
https://www.corelis.com/education/tutorials/jtag-tutorial/
JTAG is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. JTAG is commonly referred to as boundary-scan and defined by the Institute of Electrical and Electronic Engineers (IEEE) 1149.1, which originally began as an integrated method for testing interconnects on printed circuit boards (PCBs) implemented at the integrated circuit (IC) level.
Similar to Level sensitive scan design(LSSD) and Boundry scan(BS) (20)
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2. Design for testability
Design for testability (DFT) refers to the design techniques
that make test generation and test application cost-
effective.
DFT methods for digital circuits:
Ad-hoc methods
Structured methods:
Scan
Partial Scan
Boundary scan
2
3. Scan chain
Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified design:
Replacing flip-flops by scan flip-flops and connect to form one or more
shift registers in the test mode.
Make input/output of each scan shift register controllable/observable
from PI/PO.
Scan design techniques involves modifying the registers to allow them to be
chained into a long shift register, called a scan chain.
3
4. Scan Flip-Flop (master-slave) 4
D
TC
SD
CK
Q
Q
MUX
D flip-flop
Master latch Slave latch
CK
TC Normal mode, D selected Scan mode, SD selected
Master open Slave open
t
t
Logic
overhead
5. Operation
Circuit with two modes of operation
Normal functional mode
Test mode
Circuit bistables are interconnected into a shift register With the circuit in test
mode It is possible to shift an arbitrary test pattern into the bistables.
By returning the circuit to normal mode for one clock period the
combinational circuitry acts upon the bistable contents and primary input
signals, Stores the results in the bistables Circuit is then placed into test mode
It is possible to shift out the contents of the bistables and compare these
contents with the correct response
5
7. Adding Scan Structure 7
SFF
SFF
SFF
Combinational
logic
PI PO
SCANOUT
SCANIN
TC or TCK
8. Comb. Test Vectors 8
I2I1
O1 O2
PI
PO
SCANIN
SCANOUT
S1 S2
N1 N2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC
Don’t care
or random
bits
Sequence length = (nsff + 1) ncomb + nsff clock periods
ncomb = number of combinational vectors
nsff = number of scan flip-flops
9. Multiple Scan Registers
Scan flip-flops can be distributed among
any number of shift registers, each having
a separate scanin and scanout pin.
Test sequence length is determined by
the longest scan shift register.
9
SFF
SFF
SFF
Combinational
logic
PI/SCANIN PO/
SCANOUTM
U
X
CK
TC
10. Hierarchical Scan
Scan flip-flops are chained within
subnetworks before chaining subnetworks.
Advantages:
Automatic scan insertion in netlist
Circuit hierarchy preserved – helps in debugging and
design changes
Disadvantage: Non-optimum chip layout.
10
SFF1
SFF2 SFF3
SFF4
SFF3SFF1
SFF2SFF4
Scanin Scanout
Scanin
Scanout
Hierarchical netlist Flat layout
11. Cons.
If the path is a critical timing path, performance of the whole system is
affected.
Another disadvantage of scan design, when compared to some other DFT
techniques, is that the scan chain is very long.
Shifting test vectors in and result vectors out takes a large fraction of test time,
so the system cannot be tested at full operational speed.
11
12. Level-Sensitive Scan Design (LSSD)
This approach was introduced by Eichelberger and T. Williams in 1977 and 1978.
It is a latch-based design used at IBM.
It guarantees race-free and hazard-free system operation as well as testing.
Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing
test process.
It is a DFT scan design method which uses separate system and scan clocks to
distinguish between normal and test mode.
Latches are used in pairs, each has a normal data input, data output and clock
for system operation. For test operation, the two latches form a master/slave
pair with one scan input, one scan output and non-overlapping scan clocks A
and B which are held low during system operation but cause the scan data to
be latched when pulsed high during scan.
12
13. Advantages & Drawbacks of LSSD
1. Correct operation independent of AC characteristics is guaranteed.
2. FSM is reduced to combinational logic as far as testing is concerned.
3. Hazards and races are eliminated, which simplifies test generation and fault
simulation.
1. Complex design rules are imposed on designers.
2. Asynchronous designs are not allowed in this approach.
3. Sequential routing of latches can introduce irregular structures.
4. Faults changing combinational function to sequential one may cause trouble, e.g.,
bridging and CMOS stuck-open faults.
5. Test application becomes a slow process, and normal-speed testing of the entire test
sequence is impossible.
6. It is not good for memory intensive designs.
13
15. Boundary scan
Boundary scan is a method for testing interconnects (wire lines) on printed circuit
boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used
as a debugging method to watch integrated circuit pin states, measure voltage, or
analyze sub-blocks inside an integrated circuit.
The success of boundary scan techniques led to the formation of the Joint Test
Action Group (JTAG) in the 1980s for standardizing boundary scan components and
protocols.
Each component have a test access port (TAP), consisting of the following
connections:
o Test Clock (TCK): provides the clock signal for the test logic.
o Test Mode Select Input (TMS): controls test operation.
o Test Data Input (TDI): serial input for test data and instructions.
o Test Data Output (TDO): serial output for test data and instructions.
15
18. Operation
To test the PCB, the test equipment shifts a test vector into the scan chain.
When the chain is loaded, the vector is driven onto the external outputs of the
chips.
The scan-chain flip-flops then sample the external inputs, and the sampled
values are shifted out to the test equipment.
The test equipment can then verify that all of the connections between the
chips.
The TAP Controller operates as a simple finite-state machine, changing between
states depending on the value of the TMS input. Different states govern shifting
of data into the Instruction Register or one of the data registers.
The JTAG standard defines a number of instructions formats for operations that
select among data registers, control the mode of the scan chain
18
19. A BS cell 19
1. Normal: Mode_Control=0;
IN->OUT
2. Scan: ShiftDR=1,ClockDR;
TDI->...->SIN->SOUT->...TDO
3. Capture: ShiftDR=0, ClcokDR;
IN-> QA, OUT driven by IN or QB
4. Update: Mode_Control=1, UpdateDR;
QA->OUT
21. States of TAP Controller
Test-Logic-Reset: normal mode
Run-Test/Idle: wait for internal test
Select-DR-Scan: initiate a data-scan sequence
Capture-DR: load test data in parallel
Shift-DR: load test data in series
Exit1-DR: finish phase-1 shifting of data
Pause-DR: temporarily hold the scan operation (allow the bus master to reload
data)
Exit2-DR: finish phase-2 shifting of data
Update-DR: parallel load from associated shift registers
21
22. BSDL
BSDL description of a component, together with a set of test vectors, as input to
ATE for testing the component and the board in which it is embedded.
Test data can be shifted into the cells at the inputs and then driven onto the
core’s inputs. The core’s outputs can be sampled into the cells at the output
pins and then shifted out to the ATE.
Thus, the JTAG architecture solves two problems: in-circuit testing of
components in a system, and in-circuit testing of the connections between the
components.
22
25. EXTEST & SAMPLE/PRELOAD
• Test off-chip circuits and board-level
interconnections
• Data is first loaded into boundary register chain
with SAMPLE/PRELOAD instruction
• Samples inputs and outputs, pass-through
• Loads boundary register with data
25