The document discusses VLSI design methodologies and limitations using CAD tools. It provides an overview of different VLSI design methodologies such as full custom design, semi-custom design, gate array design, standard cell design, FPGA-based design and CPLD-based design. It also discusses the evolution of VLSI design flows from past to present technologies. Furthermore, it describes the complexities in VLSI design and how CAD tools help manage these complexities and automate the design process. Finally, it summarizes different types of VLSI CAD tools and compares various open source and licensed CAD tool vendors.
Very Large Scale Integration is the technology used now a day everywhere. Diploma as well as degree students can refer this
(For Downloads, send me mail
agarwal.avanish@yahoo.com)
Very Large Scale Integration is the technology used now a day everywhere. Diploma as well as degree students can refer this
(For Downloads, send me mail
agarwal.avanish@yahoo.com)
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The History of the transistor dates to the mid-1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.
With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose.
One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.
The Invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material. The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single silicon wafer, which led to small-scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then millions, and now billions (109)).
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
These presentation was given to Electronics and Communication Students, Sem6, CENTRAL INSTITUTE OF TECHNOLOGY(CIT) KOKRAJHAR. This presentation includes general overview of VLSI industry and career guidance for VLSI industry. The program was initiated by Dr. Agile Mathew, Assistant Professor at CIT.
Semiconductor engineering is becoming more dynamic fiels since the technology scaling is taking place. Power reduction techniques are lucrative solutions to the performance, area and power trade off. Therefore Power reduction of VLSI designs are critical.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The History of the transistor dates to the mid-1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.
With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose.
One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.
The Invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material. The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single silicon wafer, which led to small-scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then millions, and now billions (109)).
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
These presentation was given to Electronics and Communication Students, Sem6, CENTRAL INSTITUTE OF TECHNOLOGY(CIT) KOKRAJHAR. This presentation includes general overview of VLSI industry and career guidance for VLSI industry. The program was initiated by Dr. Agile Mathew, Assistant Professor at CIT.
Semiconductor engineering is becoming more dynamic fiels since the technology scaling is taking place. Power reduction techniques are lucrative solutions to the performance, area and power trade off. Therefore Power reduction of VLSI designs are critical.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
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VLSI Training Course in Chandigarh (Front End Design, Back End CMOS Design)Naresh Dhamija
This slideshare ppt explains what is vlsi technology, job profiles for which a VLSI Engineer can opt for, VLSI Training Details, Course Syllabus, pre qualification details, advantages of joining JK Soft Tech Solutions for VLSI Training etc.. For more information on VLSI Design Training Please visit: http://www.jksofttechsolutions.com/training/vlsi-training-in-chandigarh-pcb-gate-id-designing/
Triad Semiconductor Analog and Mixed Signal ASIC Company OverviewTriad Semiconductor
Triad Semiconductor, www.triadsemi.com, designs and manufactures analog and mixed-signal custom IC solutions. We support customers in consumer, automotive, industrial, medical and defense markets. Learn how to get your products to market quickly (we've gone from kickoff to working silicon in 60 days), how to fix problems quickly and inexpensively (we've fixed problems in hours that take others months), and how to ship cost effectively (our customers are shipping over 50-million devices per year using our Agile ASIC™ technology).
Study and Comparison of Open Source and Licensed VLSI CAD Tools using CMOS De...ijsrd.com
the design of VLSI circuits can be achieved at many different refinement levels from the most detailed layout to the most abstract architectures. VLSI design has been the study of electronic design automation and related semiconductor science, and many software tools have been written to solve one or more problems associated with the VLSI design flow. VLSI CAD tools have emerged as a boon in assisting VLSI Design engineers to choose and optimize various design models and technology. The importance of CAD tool can be understood by seeing its complex algorithms, data structures and modeling assumptions used in each of the following steps namely logic synthesis, logic verification, layout synthesis, timing verification and many others. Thus a number of standard tools have emerged to design and analyze VLSI chip from one step of the flow to another. Computer-aided design (CAD) is the use of computer systems to assist in the creation, modification, analysis, or optimization of a design. Computer aids in VLSI now offer advance capabilities so engineers can better visualize their product designs. The VLSI CAD tools work sideways together with chip designers to design and analyze entire semiconductor chips. In this paper, a number of open-source and licensed CAD tools will be studied and compared. The tools have been used for various commercial and academic purposes in various companies and universities at different design abstraction levels. This paper will help to comprehend many EDA tools and help to select appropriate computer aid for chip design.
Conference: 13th IEEE International Conference on Industrial Informatics, INDIN 2015. Cambridge, UK – July 22-24 2015
Title of the paper: A knowledge-based solution for automatic mapping in component based automation systems
Authors: Borja Ramis Ferrer, Bilal Ahmad, Andrei Lobov, Daniel Vera, José L. Martinez Lastra, Robert Harrison
Tool-Driven Technology Transfer in Software EngineeringHeiko Koziolek
This talk presentst the tool-driven technology transfer process ABB Corporate Research applies in selected software engineering University collaborations. As an example, we have created an add-in to a popular UML tool and developed the tooling in close interaction with the target users. Centering the technology transfer around tool implementations brings many benefits such as the need to make conceptual contributions applicable and the ability to quickly benefit from the new concepts. A challenge to this form of technology transfer is the long-term commitment to the maintenance of the tooling, which we try to address by creating an open developer community. Tool-driven technology transfer projects have proven to be valuable a instrument of bringing advanced software engineering technologies into our organization.
Architectural Design Spaces for Feedback Control in Self-Adaptive Systems Con...Sandro Andrade
Presented at 25th International Conference on Software Engineering and Knowledge Engineering (SEKE 2013) - Boston/MA - EUA.
A lot of current research efforts in self-adaptive systems community have been dedicated to the explicit modeling of architectural aspects related to system self-awareness and context-awareness. This paper presents a flexible and extensible representation of architectural design spaces for self-adaptation approaches based on feedback control loops. We have defined a generic representation for design spaces meta-modeling and have instantiated it in order to provide direct support for early reasoning and trade-off analysis of self-adaptation aspects with the aid of a set of feedback control metrics. The proposed approach has been fully implemented in a supporting tool and a case study with a distributed industrial data acquisition service has been undertaken. Whilst preliminary experiences with the proposed approach indicate useful reasoning support when comparing alternative design solutions for self-adaptation, further investigation regarding scalability aspects and automatic handling of conflicting goals has been identified as future work.
TMPA-2017: Stemming Architectural Decay in Software SystemsIosif Itkin
TMPA-2017: Tools and Methods of Program Analysis
3-4 March, 2017, Hotel Holiday Inn Moscow Vinogradovo, Moscow
Stemming Architectural Decay in Software Systems
Nenad Medvidovic (Professor, USA University of Southern California, ACM SIGSOFT Executive Committee Chair)
For video follow the link: https://youtu.be/D7ZVSifyJoA
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These slides present the needs, challenges, and opportunities in architecture description languages. They have been presented at the Empirical Software Engineering unit, at the University of Bolzano.
The presentation starts with an introduction to software architecture, then presents some challenges and opportunities in architecture description languages.
Study of vlsi design methodologies and limitations using cad tools for cmos technology presentation
1. INFLUENCE 2013
National Conference on Mega Trends in Engineering
(August 16 & 17, 2013)
“Study of VLSI Design Methodologies and Limitations
using CAD tools for CMOS Technology”
Presented By:
Ayoush Johari
VVS Lavanya
School of Interdisciplinary Science and Technology School of Interdisciplinary Science and Technology
International Institute of Information Technology
International Institute of Information Technology
Pune, India
Pune, India
Rakeshwari Pal
Department of Electrical and Electronics Engineering
Trinity Institute of Technology and Research
Bhopal, India
2. VLSI Technology and Design Drivers
Less Power Consumption
Less Price/ More Economical
More or Less components per board/system
Less Price/ More Economical
Higher reliability
Improved Interconnects
More Compactness
High Speed of Operation
Lesser Manufacturing Costs
Area Utilization/compactness
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
Source: http://www.gdiamos.net
2
3. Why not Silicon Compiler ?
Reality
Ideal Scenario
Design Methodology
Silicon Compiler
Simple Tasks
Complex Procedures
VLSI designers
Lots Of Human
Interaction
No Human
Interaction
Spec/Verilog/VHDL
Synthesis
Testing team
Placement
Verification
Routing
CAD developers
Circuit on Silicon
Process people
3
source : http://www.vlsicad.ucsd.edu/maryjanerwin/psu
4. View of IC Designer
Design parameters by which Design success is measured:
Performance Specifications
Size of Wafer, Die and overall manufacturing cost
Design time including engineering and time to tape out
Ease of Test pattern generation , verification and testability.
Proposed
Architecture
Algorithm
Process
Technology
VLSI
CAD
Tools
Chip for
fabrication
Figure 1: Generalized View of a IC Designer
source: http://ic.engin.brown.edu/classes/EN1600S08/projects.html
Design is a continuous tradeoff between namely 3 parameters namely
Price, Power and performance.
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
4
5. VLSI Design Methodologies
Full Custom Design
Semi Custom Design
Gate Array Design
Standard Cell Design
FPGA Based Design
CPLD Based Design
Hardwired Control
PLA Based Control
HDL Based Design Methodology
RT-Level Synthesis
IP Cores, SOCs, DSPs, MEMs
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
5
6. VLSI Design Methodologies
Systematic design methods or the design methodologies are necessary for
successfully designing complex digital hardware.
Our design methods usually differ by the number of abstraction levels and the
complexities involved.
A Gated array, standard cell design, full custom design, CPLDs FPGAs are some
of the design methodologies well known.
More Levels of
abstraction
System
Specifications
Analysis
Synthesis
Automation
Manual
Less Levels
of abstraction
Final
Chip
Figure 2: Abstraction hierarchies in VLSI Design Methods
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
6
7. Design Flow Evolution
Past- 250-180nm
Monday, March 03, 2014
Present- 90-45nm
VLSI Design Methodologies and Limitations
using CAD Tools
Future 22.5-10nm
Source http://www.vlsicad.ucsd.edu/
7
8. VLSI Design Complexities
VLSI Design is a process of converting an Idea to a Chip.
Problem Domain complexity
Development Process complexity
Choice Domain complexity
Testing related complexity
Packaging related complexity
source: LSI Logic LEA300K ;(0.6 m CMOS)
www.lsi.com
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
8
9. VLSI CAD Tools
Current systems are very complex.
Design abstraction and decomposition is done to manage complexities.
Tools automate the process of converting our design from
one abstraction level to another.
Design automation tools improve productivity.
Figure 3: Layout of 4004 microprocessor invented by Intel Engineers Federico
Faggin, Ted Hoff, and Stanley Mazor
source : http://ic.engin.brown.edu/classes/lecture6
The First IC based microprocessor was built using manual design.
To get the chip to the market fast CAD tools are indeed needed.
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
9
10. Classification and Comparison of VLSI CAD Tools
1. High Level Synthesis(HDLs)
Open
Source/
Licensed
S.No.
1
Cadence EDA
Licensed
Analog and
Mixed
signal
2
Mentor
Graphics
EDA
Licensed
Analog and
Mixed
signal
3
Synopsys EDA
Licensed
Analog and
Mixed
signal
4
Tanner EDA
Licensed
Analog and
Mixed
signal
5
Alliance
Open
Source
Mixed
Signal
Logic to
Layout
6
Electric CAD
Open
Source
Mixed
Signal
Logic to
Layout
7
Magic
Open
Source
Mixed
Signal
Circuit
Layout
8
SystemC
Open
Source
Electronic
System
Level
Library
for Digital
Design
9
2. Logic Synthesis Tools
CAD Tool
myHDL
Open
Source
Electronic
System Level
Hardware
Description
language
3. Circuit Optimization Tools
3.1 Transistor Sizing Tools
3.2 Process Variation Tools
3.3 Stastical Design Tools
4. Layout Tools
4.1 Floorplanning
4.2 Place and Route
Type
4.3 Module Generation
4.4 Automatic Cell Placement Routing
5. Layout Extraction Tools
Function
Complete
CAD
Flow
Complete
CAD
Flow
Complete
CAD
Flow
Complete
CAD
Flow
Table : Comparative study of various open source
and licensed set of VLSI EDA tools.[18]
6. Simulation (Spice for circuit level Simulation)
7. Monday, March 03, 2014 Verification Tools
Layout Schematic
10
11. VLSI CAD Tools (Contd..)
VLSI CAD Tools
Front End
Tools
Back End
Tools
Design
Capture Tools
Synthesis
Tools
Design Entry
Floor Planning
Editors
Behavioral Synthesis
Editors
Place & Route
VHDL/Verilog
RTL Synthesis
Simulation
Extraction
Synthesis
LVS, LVL
System Verilog /
SystemC, Vera
FPGA Synthesis
ERC,DRC
State Charts
Physical Synthesis
DFT Insertion
Pattern Generators
FSM Capture
Module/Cells
Test Generation
Format Converters
Timing Analysis
Logic Synthesis
DSP Synthesis
Pattern Generators
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
11
12. VLSI CAD Tools (Contd..)
VLSI CAD Tools
Analysis
Tools
Checkers
Testing Related
Tools
Verifiers
DRC,ERC
Timing Verifier
Netlist Compare
ATPG
ICE/ Hardware
Ratio Checker
DFT
Formal Verifiers
Fan-in/ FanOut Checker
Power Checker
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
12
13. Design and Analysis
VHDL / Verilog / SystemC
compilation/
synthesis
mask layout patterns
design schematics
find wire routes
device layout
• Design development is facilitated using Computer-Aided Design (CAD) tools
source :http://ic.engin.brown.edu/classes/lecture1
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
13
14. tape out
mask layout patterns
mask writer
printing
test and
packaging
chip
masks
dice
die
wafer
• Design development is facilitated using Computer-Aided Design (CAD) tools
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
source: http://ic.engin.brown.edu/
14
classes/lecture1
15. Simple VLSI CAD Tool Chain
Specifications
Hardware
Description
Languages
if
SEL == “00“ then Y
elseif SEL == “01“ then Y
elseif SEL == “10“ then Y
else
Y
end if;
=
=
=
=
A;
B;
C;
D;
Schematic
Entry
2:1 MUX
2:1 MUX
D
Synthesis
2:1 MUX
C
B
Y
A
SEL == 10
SEL == 01
SEL == 00
IC Layout
/Area
Layout and Routing
Cell Library
Simulation
Verification and timing/ power results
Monday, March 03, 2014
VLSI Design Methodologies and Limitations Source: http://ic.engin.brown.edu/classes
15
using CAD Tools
16. VLSI CAD Tool Vendors
[32]
[26]
[27]
[31]
[30]
[28]
[29]
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
16
17. Typical VLSI Design Flows
Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
17
19. Design Representation Levels and Associated Formats
Design Behavior
ISA,C,C++
Architecture
SystemC, VHDL, Verilog
Micro -Architecture
Software and
Operating System
EDA Servers
and
Linux, RTOS
Digital Hardware
(Register Transfer)
Gate Level Netlist
(Logic Gates & Latches)
Layout and Masks
(Fabrication Patterns)
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
19
20. VLSI Design Complexities vs CAD Tools
Design Challenges and
Priorities
Algorithms
and
CAD Tools
Methodology
and
EDA Flows
Process Technology and
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
Limitations
using CAD Tools
20
21. Limitations and Challenges to Overcome
Designer’s Aim – Transfer Design description in one domain into a fully
equivalent design descriptions in respective other domains.
Fast
Prototyping
Custom Design
Labor Intensive
Low
Volume
High Volume
Guiding Design Organization Principles
Programmable Interconnects
Mask Programmable Gate Arrays
Mixed Standard Cell and Custom Cell
to CMOS IC Designers.
Design investment increasing for a given
Monday, March 03, 2014
Programmable Logic Structures
Standard Cell Design
Design Options available
application
Programmable Logic
Full Custom mask Design
Design Time and
Cost Decreasing
(for given application)
VLSI Design Methodologies and Limitations
using CAD Tools
Performance
Increasing,
Die Area Decreasing ,
Power Dissipation
increasing
21
22. Conclusion
VLSI Design – complexities increases as the time progresses .
Design Methodologies and CAD tools are integral parts in VLSI
Design and go hand in hand and they evolve based on designer’s needs.
CAD Tools allows the freedom to VLSI Designers to focus on
creativity with respect to process technology.
The development in the design tools, collaborative design methods, the
role of human factors and integration factors in the design technology
marks the outline of various design methodologies.
Monday, March 03, 2014
VLSI Design Methodologies and Limitations
using CAD Tools
22
23. References
[1] Randal E. Bryant, Kwang-TingCheng , Andrew B Kahang, Kurt Kreutzer, Wojciech
Maly,Richard Newton, Lawerance Pileggi, Jan M Rabaey, Alberto SaniovanniVincentelli, “Limitations and Challenges of CAD technology for CMOS VLSI” .
[2] Catherine H. Gebotys, Mohamed I. Elmasry,“Vlsi Design Synthesis and Testability”.
[3]A.H. Farrahi, D.J. Hathaway, M.Wang and M.Sarrafzadeh, “Quality OF EDA CAD Tools:
Definitions, Metrices and Directions”.
[4] Anantha Chandrakasan, Isabel Yang, Carlin Veiri, Dimitri Antoniadis, “Design Considerations
and tools for Low voltage Digital system Design”
[5] Mike Spreitzer “Comparing Structurally different views of a VLSI Design”
[6] Catherine H. Gebotys, Mohamed I. Elmasry, “VLSI Design Synthesis and Testibility”
[7] T.S. Cheung, K.Asada, K.L. Yip, H. Wong, Y.C. Cheng, “Low Power CMOS Design Methodologies
with reduced voltage swing ”
[8] K.A. Sumithra Devi, “Algorithms for CAD tools VLSI design”
[9] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design
VLSI Design Methodologies and Limitations
perspective Second edition
Monday, March 03, 2014
23
using CAD Tools
24. References ( Contd..)
10] Dr. Nicos Bilalis, “Computer Aided Design CAD”, January 2000 edition
[11] Course: “Trends in VLSI Design: Methodologies and CAD tools”. Presenter Raj Singh. IC
Design group,CEERI,Pilani-333031
[12] P.van der Wolf. “CAD Frameworks: Principle and Architecture” Kluwer Academic
Publishers,236pp
[13] K.Chaudhary, A.Onawaza, and E.S. Kuh. “Algorithms for Performance Enhancement and
Crosstalk Reduction”. In International conference on Computer Aided Design, pages 697702,1993.
[14] C.Chen and M.Sarrafzadeh. “Provably Good Algorithm for low power consumption and
supply voltages” ”. In International conference on Computer Aided Design, pages 76-79,1999.
[15] H.M. Chen, H.Zhou, F.Y.Young, D.F. Wong, H.H. Yang, and N.Sherwani. “Integrated
Floorplanning and Interconnect Planning”. ”. In International conference on Computer Aided
Design, pages 354-357,November 1999.
[16]http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php
[17] https://www.coursera.org/course/vlsicad/
[18]http://www.vlsiacademy.org/open-source-cad-tools.html
24