CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Class-20 These slides explain about the basic approach and requirements of re synchronization of micro-grid to utility grid. Other names very often used in place of re-synchronization are re-connection or transition. Later , I will explain about the implementation of one approach through simulation in MATLAB/SIMULINK software
Reducing power in using different technologies using FSM architectureVLSICS Design
As in today’s date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs . The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.
Loss Reduction by Optimal Placement of Distributed Generation on a Radial feederIDES Editor
Due to the increasing interest on renewable sources
in recent times, the studies on integration of distributed
generation to the power grid have rapidly increased. In order
to minimize line losses of power systems, it is crucially
important to define the location of local generation to be placed.
Proper location of DGs in power systems is important for
obtaining their maximum potential benefits. This paper
presents analytical approaches to determine the optimal
location to place a DG on radial systems to minimize the power
loss of the system. Simulation results are given to verify the
proposed analytical approaches.
This research presents a method for reliability assessment considering the 23MVA, 230/15 kV
transformer through two 15 kV outgoing transmission lines at Debre Markos substation. It also goes further to
include 139 low voltage 15/0.4 kV distribution transformers. The total load connected to the 15 kV feeders are
varies between 0.33255 and 6.3185 MW. A composite system adequacy and security assessment is done using
Monte Carlo simulation. The basic data and the topology used in the analysis are based on the Institution of
Electrical and Electronics Engineers - Reliability Test System and distribution system for bus two of the IEEEReliability
Bus bar Test System. The reliability indices SAIDI, SAIFI, CAIDI, EENS, AENS, ASAI, ASUI, and
expected interruption costs are being assessed and considered. Distribution system reliability information was
obtained from actual data for systems operating in Ethiopia Electric Utility office and Debre Markos substation
recorded data and online SCADA system.
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Class-20 These slides explain about the basic approach and requirements of re synchronization of micro-grid to utility grid. Other names very often used in place of re-synchronization are re-connection or transition. Later , I will explain about the implementation of one approach through simulation in MATLAB/SIMULINK software
Reducing power in using different technologies using FSM architectureVLSICS Design
As in today’s date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs . The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.
Loss Reduction by Optimal Placement of Distributed Generation on a Radial feederIDES Editor
Due to the increasing interest on renewable sources
in recent times, the studies on integration of distributed
generation to the power grid have rapidly increased. In order
to minimize line losses of power systems, it is crucially
important to define the location of local generation to be placed.
Proper location of DGs in power systems is important for
obtaining their maximum potential benefits. This paper
presents analytical approaches to determine the optimal
location to place a DG on radial systems to minimize the power
loss of the system. Simulation results are given to verify the
proposed analytical approaches.
This research presents a method for reliability assessment considering the 23MVA, 230/15 kV
transformer through two 15 kV outgoing transmission lines at Debre Markos substation. It also goes further to
include 139 low voltage 15/0.4 kV distribution transformers. The total load connected to the 15 kV feeders are
varies between 0.33255 and 6.3185 MW. A composite system adequacy and security assessment is done using
Monte Carlo simulation. The basic data and the topology used in the analysis are based on the Institution of
Electrical and Electronics Engineers - Reliability Test System and distribution system for bus two of the IEEEReliability
Bus bar Test System. The reliability indices SAIDI, SAIFI, CAIDI, EENS, AENS, ASAI, ASUI, and
expected interruption costs are being assessed and considered. Distribution system reliability information was
obtained from actual data for systems operating in Ethiopia Electric Utility office and Debre Markos substation
recorded data and online SCADA system.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Impact of Positive Sequence Admittance and Negative Sequence Conductance of D...ijtsrd
Voltage fluctuations resulting from variable output power of renewable energy sources are strictly challenging power quality in distributed-generation systems. This paper presents a control method for distributed static synchronous compensator (D-STATCOM) to alleviate variation of both positive- and negative-sequence voltages. The D-STATCOM simultaneously operates as fundamental positive-sequence admittance and fundamental negative-sequence conductance to restore the positive sequence voltage to the nominal value as well as reduce the negative-sequence voltage to an allowable level. Both admittance and conductance are dynamically tuned to improve voltage regulation performances in response to load changes and power variation of renewable sources. A proportional“resonant current regulator with selectively harmonic compensation is realized to control the fundamental current of the D-STATCOM as well as reduce the harmonic current, which could be an advantage in practical applications due to high voltage distortion in low-voltage micro grids. Voltage-regulation performances are discussed for different D-STATCOM locations as well as different D-STATCOM currents. Computer simulations and laboratory tests validate effectiveness. CH. Venkata Krishna | N. S. Kalyan Chakravarthi"Impact of Positive Sequence Admittance and Negative Sequence Conductance of D-Statcom to Compensate Variations in Voltage Levels in Distributed Generation Systems" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-1 , December 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5919.pdf http://www.ijtsrd.com/engineering/electrical-engineering/5919/impact-of-positive-sequence-admittance-and-negative-sequence-conductance-of-d-statcom-to-compensate-variations-in-voltage-levels-in-distributed-generation-systems/ch-venkata-krishna
This slide presents the control aspects of Energy Storage System in Microgrid. Later I will discuss about the control strategy with integration to DGs and EVs.
Optimal Placement and Sizing of Distributed Generation Units Using Co-Evoluti...Radita Apriana
Today, with the increase of distributed generation sources in power systems, it’s important to
optimal location of these sources. Determine the number, location, size and type of distributed generation
(DG) on Power Systems, causes the reducing losses and improving reliability of the system. In this paper
is used Co-evolutionary particle swarm optimization algorithm (CPSO) to determine the optimal values of
the listed parameters. Obtained results through simulations are done in MATLAB software is presented in
the form of figure and table in this paper. These tables and figures, show how to changes the system
losses and improving reliability by changing parameters such as location, size, number and type of DG.
Finally, the results of this method are compared with the results of the Genetic algorithm (GA) method, to
determine the performance of each of these methods.
Voltage sag mitigation using supercapacitor based dynamic voltage restorereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Introducing LQR-fuzzy for a dynamic multi area LFC-DR modelIJECEIAES
It is well known that Load Frequency Control (LFC) model plays a vital role in electric power system design and operation. In the literature, much research works has stated on the advantages and realization of DR (Demand Response), which has proved to be an important part of the future smart grid. In an interconnected power system, if a load demand changes randomly, both frequency and tie line power varies. LFC-DR model is tuned by standard controllers like PI, PD, PID controllers, as they have constant gains. Hence, they are incapable of acquiring desirable dynamic performance for an extensive variety of operating conditions and various load changes. This paper presents the idea of introducing a DR control loop in the traditional Multi area LFC model (called LFC -DR) using LQR- Fuzzy Logic Control. The effect of DR-CDL i.e. (Demand Response Communication Delay Latency) in the design is also considered and is linearized using Padé approximation. Simulation results shows that the addition of DR control loop with proposed controller guarantees stability of the overall closed-loop LFC-DR system which effectively improves the system dynamic performance and is superior over a classical controller at different operating scenarios.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Abstract- This paper presents a major revision of the Universal Four Leg ‘DC Grid Laboratory Experimental Setup’. This revision includes the reduction of current loops, the increase of efficiency in the power stage, the expansion of measurement possibilities and the re-specification of the input/output range.
To deal with an ever present complication in the world of measurements, simple fuse holders are converted into dedicated probe measurement connectors. These connectors reduce large ground loops to a minimum.
Key features include a clear board layout and silkscreen, a tremendous reduction of semiconductor losses resulting in a heatsink-less power stage and easy, reliable probe and power connections. Provisions are made for a Single Board Computer (SBC) to read and control the Universal Four Leg V4. The SBC can also be used to communicate with external devices to allow for remote control of the Universal Four Leg and the presentation of measurements performed.
The Universal Four Leg is a power management device with a wide range of applications in both higher educational laboratory courses, as well as a dedicated grid manager in low voltage DC-grids.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Impact of Positive Sequence Admittance and Negative Sequence Conductance of D...ijtsrd
Voltage fluctuations resulting from variable output power of renewable energy sources are strictly challenging power quality in distributed-generation systems. This paper presents a control method for distributed static synchronous compensator (D-STATCOM) to alleviate variation of both positive- and negative-sequence voltages. The D-STATCOM simultaneously operates as fundamental positive-sequence admittance and fundamental negative-sequence conductance to restore the positive sequence voltage to the nominal value as well as reduce the negative-sequence voltage to an allowable level. Both admittance and conductance are dynamically tuned to improve voltage regulation performances in response to load changes and power variation of renewable sources. A proportional“resonant current regulator with selectively harmonic compensation is realized to control the fundamental current of the D-STATCOM as well as reduce the harmonic current, which could be an advantage in practical applications due to high voltage distortion in low-voltage micro grids. Voltage-regulation performances are discussed for different D-STATCOM locations as well as different D-STATCOM currents. Computer simulations and laboratory tests validate effectiveness. CH. Venkata Krishna | N. S. Kalyan Chakravarthi"Impact of Positive Sequence Admittance and Negative Sequence Conductance of D-Statcom to Compensate Variations in Voltage Levels in Distributed Generation Systems" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-1 , December 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5919.pdf http://www.ijtsrd.com/engineering/electrical-engineering/5919/impact-of-positive-sequence-admittance-and-negative-sequence-conductance-of-d-statcom-to-compensate-variations-in-voltage-levels-in-distributed-generation-systems/ch-venkata-krishna
This slide presents the control aspects of Energy Storage System in Microgrid. Later I will discuss about the control strategy with integration to DGs and EVs.
Optimal Placement and Sizing of Distributed Generation Units Using Co-Evoluti...Radita Apriana
Today, with the increase of distributed generation sources in power systems, it’s important to
optimal location of these sources. Determine the number, location, size and type of distributed generation
(DG) on Power Systems, causes the reducing losses and improving reliability of the system. In this paper
is used Co-evolutionary particle swarm optimization algorithm (CPSO) to determine the optimal values of
the listed parameters. Obtained results through simulations are done in MATLAB software is presented in
the form of figure and table in this paper. These tables and figures, show how to changes the system
losses and improving reliability by changing parameters such as location, size, number and type of DG.
Finally, the results of this method are compared with the results of the Genetic algorithm (GA) method, to
determine the performance of each of these methods.
Voltage sag mitigation using supercapacitor based dynamic voltage restorereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Introducing LQR-fuzzy for a dynamic multi area LFC-DR modelIJECEIAES
It is well known that Load Frequency Control (LFC) model plays a vital role in electric power system design and operation. In the literature, much research works has stated on the advantages and realization of DR (Demand Response), which has proved to be an important part of the future smart grid. In an interconnected power system, if a load demand changes randomly, both frequency and tie line power varies. LFC-DR model is tuned by standard controllers like PI, PD, PID controllers, as they have constant gains. Hence, they are incapable of acquiring desirable dynamic performance for an extensive variety of operating conditions and various load changes. This paper presents the idea of introducing a DR control loop in the traditional Multi area LFC model (called LFC -DR) using LQR- Fuzzy Logic Control. The effect of DR-CDL i.e. (Demand Response Communication Delay Latency) in the design is also considered and is linearized using Padé approximation. Simulation results shows that the addition of DR control loop with proposed controller guarantees stability of the overall closed-loop LFC-DR system which effectively improves the system dynamic performance and is superior over a classical controller at different operating scenarios.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Abstract- This paper presents a major revision of the Universal Four Leg ‘DC Grid Laboratory Experimental Setup’. This revision includes the reduction of current loops, the increase of efficiency in the power stage, the expansion of measurement possibilities and the re-specification of the input/output range.
To deal with an ever present complication in the world of measurements, simple fuse holders are converted into dedicated probe measurement connectors. These connectors reduce large ground loops to a minimum.
Key features include a clear board layout and silkscreen, a tremendous reduction of semiconductor losses resulting in a heatsink-less power stage and easy, reliable probe and power connections. Provisions are made for a Single Board Computer (SBC) to read and control the Universal Four Leg V4. The SBC can also be used to communicate with external devices to allow for remote control of the Universal Four Leg and the presentation of measurements performed.
The Universal Four Leg is a power management device with a wide range of applications in both higher educational laboratory courses, as well as a dedicated grid manager in low voltage DC-grids.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
Low power requirement has become a principal motto in today’s world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
Back track input vector algorithm for leakage reduction in cmos vlsi digital ...VLSICS Design
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a
circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI
circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard
logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
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SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
DOI : 10.5121/vlsic.2018.9101 1
SURVEY ON POWER OPTIMIZATION
TECHNIQUES FOR LOW POWER VLSI CIRCUIT
IN DEEP SUBMICRON TECHNOLOGY
T. Suguna and M. Janaki Rani
Department of Electronics and Communication Engineering,
Dr.M.G. R Educational and Research Institute, Chennai, India
ABSTRACT
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
KEYWORDS
leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic.
1. INTRODUCTION
Energy efficiency is the critical feature of modern electronic systems, due to desirability of
portable devices, demand for reliability and performance, to extend battery life, need to reduce
package cost, to reduce Green cost etc. [1]. Advancements in scaling with reduced threshold and
supply voltages lead to increased leakages in MOS transistors. Many studies presented that
leakage power consumption is up to 40% of total power consumption in nanometre technology
[2]. To overcome the power dissipation problem many researchers have proposed different ideas
from the device level to the architectural level. However, there is no universal way to avoid
trade-offs between power, delay and area. Thus, designers are required to choose appropriate
techniques that satisfy application and product needs. In VLSI circuits, to control the power
consumption supply voltage plays an important role. Supply voltage scaling without scaling of
threshold voltage degrades the performance of the device [3]. The reduction of threshold voltage
and supply voltages proportionally retains the performance. The threshold voltage reduction leads
to five times higher leakage current [4]. The requirements for power optimization continue to
increase significantly and the motivations to optimise power differ from application to
application. Power consumption has become primary design issue and needs suitable power
management in the design of digital circuits where switching and standby mode affects the
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
2
performance of system. The design of a low power circuits mainly focuses on a problem occurred
due to the performance, power dissipation and chip area.
This paper is organised as follows in section I we discussed about the sources of power
dissipation in CMOS. In section II we mention the power optimization at different levels of
abstraction broadly. In section IIII we focussed on different power optimization techniques. In
section IV we presented the advanced power recovery technique and in section V we concluded
about the selection of different techniques for different approaches.
2. POWER DISSIPATION IN CMOS
2.1 Sources of Power Consumption
The main sources of power consumption, that affect CMOS circuits are dynamic power and
standby power.
The following equations define the power within the device:
Ptotal = Pdynamic + Pshort + Pleakage
Pdynamic = α*C *Vdd
2
* f
Pshort = α(β/2) (V-2Vth)3
*f *Trf
Pleakage = (Idiode + Isubthreshold) *Vdd
α = Switching Activity, C = Total Load Capacitance, Vdd= Supply Voltage f = clock
Frequency, β= Gain Factor, Trf = Rise/Fall Time (gate inputs), Vth = Threshold Voltage.
Fig:1 Sources of Power Consumption in CMOS
Dynamic power or active power is the power consumed by the device when it switches from one
state to another state actively. It consists of switching power due to charging and discharging the
loads on the device and short circuit power, consumed during output transitions due to current
flowing from the supply to ground. Leakage power is actually consumed when the device is both
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
3
static and switching, but generally the main concern with leakage power is during inactive state of
device. This is the power which should be concentrated more in deep submicron design of device
as it exponentially depends on size of the device [5]. Fig.1 shows both dynamic power and
leakage power consumption that occur in CMOS circuits. In deep submicron technology sub-
threshold leakage current is problematic because it increases as transistor threshold voltages (Vth)
decrease. At 90 nm, leakage power can represent as much as 50 percent of the total power
consumed by a chip, depending on the design. In addition, high leakage power can exponentially
increase reliability related failures, even in standby which is represented in fig 2.
Fig.2 Leakage power and active power at different deep submicron CMOS technologies.
3. OPTIMIZATION AT DIFFERENT LEVELS OF ABSTRACTION
An integrated low power methodology requires optimization at all design abstraction levels as
mentioned below.
3.1. System level
Qiaing Tong et al[6] discussed about power optimization at system level. System level design
consists of the mapping of a high-level system model on to an architecture. in order to achieve
about 75 % of power optimization different processing algorithms and architectures are needed
with proper executable specifications. The choice of algorithm used can impact the power cost
because it determines the runtime complexity of a program. Some of the techniques used for
system level power optimization are Adaptive Voltage Scaling (AVS), Memory access reduction,
branching reduction, Loop unrolling and combining, Loop unrolling and combining Hardware are
preferable.
3.2. Algorithm level
Chetan Sharma et al [7] discussed that power consumption at algorithm level relates the proper
choice of algorithm, word length, modular interfaces, technology implementation, software and
hardware selection, and behavioural constrains and trade-off will minimise the power
requirement. The algorithm which is more useful is which have minimum number of operations
because it will require less hardware. By increasing concurrency, we can increase efficiency of
that device.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
4
3.3. Architecture level
Chetan Sharma et al [7] discussed that impact of low-power techniques on the architecture level
can be more significant than at the gate level. He mentioned the techniques parallelism, pipeline,
distributed processing and power management, can be used to reduce the power dissipation at
architecture level. The techniques like both parallelism and pipelining can optimise the power an
at the expense of area while maintaining the same throughput. The combination of pipelining and
parallelism can result in further power reduction, because the power supply voltage can be
reduced aggressively and also, he mentioned by multiple frequency and voltage islands, reduction
in switching activity and through logic transformations approaches can be implemented at
architecture level to reduce the consumption of power.
3.4. Gate level
Amberly Babu et al [8] discussed that at gate level we get accurate verification of power
consumption. Up to 20%of power can be saved by implementing clock gating, power gating,
clock tree optimization techniques. at gate level also we can employ logic level transformations to
reduce switching activity there by reducing power consumption.
3.5. Transistor level
Sumitha Gupta et al [9]mentioned that advanced process can built transistors with different
threshold voltages. Up to 30% of power can be saved by using a mixture of CMOS transistors
with multiple threshold voltages. There are two different thresholds are available, generally called
high Vth and low Vth. High threshold transistors are slower but leak less, and can be used in non-
critical circuits.
Fig.3 shown below gives the details of power saving, speed and error trade off at different level
of abstraction
Fig.3.Power optimization at different levels of Abstraction with power saving speed and error [9]
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
5
4. POWER OPTIMIZATION TECHNIQUES
4.1 Static Power Reduction Techniques
There are various leakage power reduction techniques based on modes of operation of systems.
The two operational modes are a) active mode and b) standby (or) idle mode. To minimize this
power, technology scaling, voltage scaling, clock frequency scaling, reduction of switching
activity, etc., were widely used.
4.1.1. Multi-Vth optimization/ (Multi Threshold -MTCMOS):
P. Sreenivasulu etal [10] discussed that MTCMOS (Multiple Threshold CMOS) is very effective
technique in reducing leakage currents in the standby mode. This technique utilizes transistor
with multiple threshold voltages(Vth)to optimise power and delay. Here low voltage devices were
used in critical delay paths to minimize clock periods. Higher voltage devices were used on non-
critical paths to reduce static leakage power without incurring a delay penalty.
Fig.4 MTCMO Stechnique [10]
He also discussed that this technique reduces several orders of magnitude reduction in leakage
power through two effects. First. if the original CMOS circuit effective leakage width is reduced
to the width of the single “off” nMOS Transistor second the increase in an exponential reduction
in leakage power can be achieved due to increased threshold voltage. in this if the sleep transistor
is turned off more strongly further reduction in leakage can be achieved.
4.1.2. Transistor Stacking
Narendra et al, [11] showed that stacking of two OFF transistors which significantly reduce sub-
threshold leakage compared to a single OFF transistor. It is an effective way toreduce leakage
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
6
power in active mode. Transistor stacking technique uses the dependence of Isub on the source
terminal voltage Vs. With the increase of Vs of the transistor, the subthreshold leakage current
reduces exponentially. If natural stacking of transistors does not exist in a circuit, then to utilize
the stacking effect a single transistor of width W is replaced by two transistors each of width W/2.
This is called forced stacking as shown in Figure 5.
Fig.5 Forced Stacking Circuit
4.1.3 Sleepy Stack Approach
J.C. Park et al, [12] described a sleepy stack technique which combines the sleep transistor
approach during active mode and the stack approach during standby mode. In this technique,
forced stacking is first implemented. Then to one of the stacked transistors a sleep transistor is
inserted in parallel. Thus, during active mode, the sleep transistors are on thereby reducing the
effective resistance of the path. This leads to reduced propagation delay during active mode as
compared to the forced stacking method. During standby mode, the sleep transistor is turned off
and the stacked transistor suppresses the leakage power. Figure 6 shows the circuit of a sleepy
stack inverter, where the S and S’ are sleep control signals.
Fig.6 sleepy stack inverter circuit
4.1.4. Sleepy Keeper Approach
Ajay Kumar dadoria et al [13] proposed sleepy keeper approach. In this approach two extra
transistors are used in parallel with sleep transistor. Over the pull up network we are using MOS
transistor which is drive by the feedback of the output circuit and PMOS transistor in pull-down
network. In this [13] technique two transistors are connected in parallel with sleep transistor.
Above the pull up network NMOS transistor is used. For this input is given from the feedback of
the output circuit. PMOS transistor is used in pull down network. It maintains proper output logic
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
7
since it is using feedback technique and here we can use higher Vth transistors for further
reduction of static power.
Fig.7. Two input NAND gate with sleepy keeper technique [13]
Then Ajay Kumar dadoria et al[13] proposed Modified galeor with sleepy with low and high Vth
transistors. in this the modifications are the gate of NMOS and PMOS galeor transistor has been
connected to the drain and instead of using low Vth NMOS galeor transistors high Vth transistors
are used. in this approach proper voltage swing is achieved by changing the position if inputs of
galeor transistors and applying high threshold to sleep transistors. This advantage achieved by
this technique.
Fig.8 NAND gate with galeor with sleepy approach
4.1.5. Lector approach
Narender Hanchate et al, [14] proposed a novel technique called LECTOR (Refer Fig. 6) for
reducing leakage power in CMOS circuits. He introduced two leakage control transistors(LCT) a
PMOS and NMOS within the logic gate. The gate terminal of each LCT is controlled by the
source of the other. In this arrangement, one of the LCT’s is always near its cut off voltage for
any input combination. This increases the resistance of the path from Vdd to ground leading to
significant decrease in leakage currents. This technique works effectively in both active and idle
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
8
states of the circuit, resulting in better leakage reduction. The experimental results indicate an
average leakage reduction of 79.4% for MCNC “91benchmark circuits.
Fig.9 LECTOR technique
4.1.6. Body Bias Technique
Xin He Al-Kadry et.al, [15] proposed a novel concept to control power dissipation in VLSI
processors. This paper emphasizes on adaptive leakage control using body bias technique to
reduce the power dissipation of the 65 nm MOS devices. Through adding forward body biasing,
the leakage is reduced in sub-100 nm CMOS devices (unlike above-100 nm devices) while
slightly increasing the signal propagation delay. For the conditions where the circuit does not use
up the entire clock cycle, this slack can be used to reduce the power dissipation without any loss
in performance. The fact that the circuit delay remains less than the clock period provides the
opportunity to reduce power consumption of VLSI circuits. The objective is to change the voltage
of the body bias to reduce leakage, allowing the circuit to consume less power whenever the
clock edge can be met as detected beforehand.
Fig.10 Body connections of MOS devices [15]
4.2. Dynamic Power Optimization Schemes
4.2.1. Clock gating
Dushyant Kumar Soni et al[16] proposed clock gating which reduces dynamic power dissipation.
in typical synchronous circuit such as general-purpose microprocessor, only some portion of the
circuit is active at a given time. Hence by making remaining portion idle the power consumption
can be reduced. one way is to masking the clock going to idle portion. He proposed a new scheme
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
for the same purpose by using tri state buffer and gated logic is used which is designed by the
combination of double gated with bundled inputs respectively.
Fig.11.Clock Gating Technique
The power is saves in such a way that if target device clock is ON the controlling devices clock is
OFF and vice versa in this technique the clock and dynamic power is saved during negative edge
of clock as this technique is designed for positive edge
synchronous circuits power is saved up to 20% and also reduces the hardware complexity.
4.2.2. Dual VDD
V.Sai Sri Harsha [17] discussed A Dual VDD Configuration Logic Block and a Dual VDD
routing matrix is shown in figure.12. In this technique the supply voltage of the logic and
routing blocks are programmed to reduce the power consumption .it can be done by
assigning low-VDD to non-critical paths in the design.
voltages co- exist, static current flows at the interface of the VDDLv part and the VDDH part.
Level converters can be used to up convert a low VDD to a high VDD.
4.3.3. Clustered Voltage Scaling (CVS)
Siva kumar et al[18] discussed that this technique power can be optimised without compromising
circuit performance by making use of two supply voltages. Gates in the critical path are run at the
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
for the same purpose by using tri state buffer and gated logic is used which is designed by the
combination of double gated with bundled inputs respectively.
Fig.11.Clock Gating Technique [15]
The power is saves in such a way that if target device clock is ON the controlling devices clock is
OFF and vice versa in this technique the clock and dynamic power is saved during negative edge
of clock as this technique is designed for positive edge. This technique by implementing on
synchronous circuits power is saved up to 20% and also reduces the hardware complexity.
V.Sai Sri Harsha [17] discussed A Dual VDD Configuration Logic Block and a Dual VDD
ure.12. In this technique the supply voltage of the logic and
routing blocks are programmed to reduce the power consumption .it can be done by
critical paths in the design. But whenever two different supply
exist, static current flows at the interface of the VDDLv part and the VDDH part.
Level converters can be used to up convert a low VDD to a high VDD.
Fig.12 Dual VDD architecture[16]
4.3.3. Clustered Voltage Scaling (CVS)
et al[18] discussed that this technique power can be optimised without compromising
circuit performance by making use of two supply voltages. Gates in the critical path are run at the
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
9
for the same purpose by using tri state buffer and gated logic is used which is designed by the
The power is saves in such a way that if target device clock is ON the controlling devices clock is
OFF and vice versa in this technique the clock and dynamic power is saved during negative edge
. This technique by implementing on
synchronous circuits power is saved up to 20% and also reduces the hardware complexity.
V.Sai Sri Harsha [17] discussed A Dual VDD Configuration Logic Block and a Dual VDD
ure.12. In this technique the supply voltage of the logic and
routing blocks are programmed to reduce the power consumption .it can be done by
But whenever two different supply
exist, static current flows at the interface of the VDDLv part and the VDDH part.
et al[18] discussed that this technique power can be optimised without compromising
circuit performance by making use of two supply voltages. Gates in the critical path are run at the
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
10
lower supply, as shown in Fig. 9. To minimize the number of interfacing level converters needed,
the circuits which operate at reduced voltages are clustered leading to clustered scaling. Here only
one voltage transition is allowed along a path and level conversion takes place only at flip-flops.
Fig.13. Cluster Structure[18]
4.4.4. Dynamic Voltage and Frequency Scaling (DVFS)
Siva Kumar et al [18] discussed that many circuits have time varying performance requirements
in such cases the power can be saved by reducing the clock frequency to a sufficient level to
complete the task on schedule then reducing the voltage to that level. This is called dynamic
voltage frequency scaling (DVFS). Fig.15 shows DVFS technique to save power. This technique
can be implemented by proper controlling program. [18].
Fig.14 DVFS technique [18]
4.5.5. Adaptive Voltage Scaling (AVS)
This is an extension of DVFS where the control loop is used to adjust voltage and frequency for
changing work load. [18]. The AVS loop regulates processor performance by automatically
adjusting the output voltage of the power supply to compensate for process and temperature
variation in the processor [18]. When compared to open loop voltage scaling solutions like
Dynamic Voltage Scaling (DVS), AVS uses up to 45% less energy as shown in Fig10. AVS is a
system level scheme that has components in both the processor and power supply.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
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Fig.15 Comparisons of fixed voltage, DVS and AVS energy saving in a processor.
5. ADVANCED POWER OPTIMIZATION TECHNIQUES
5.1 Adiabatic Switching
Bhuvana et al [19] discussed that an adiabatic switching is an alternative solution to reduce power
dissipation in the digital logic shown in the Fig.12. Adiabatic offers reuse of energy stored in the
load capacitor, rather than discharging the load capacitor to the ground and wasting this energy.
Operations of adiabatic logic circuits are based on some basic rules such as never turn on a
transistor when there is a voltage potential between the source and drain terminals, and never
suddenly change the voltage across any of the transistor [19]. The adiabatic logic is widely known
as ENERGY RECOVERY CMOS logic as it uses reversible logic to conserve energy.
The energy stored in the output gets retrieved by reversing the current source direction.
Here, the constant current source is used to charge the load capacitance not a constant voltage
source as used in the case of conventional CMOS circuits. Where, R represents the on resistance
of PMOS network.
Fig. 12 Adiabatic Switching Circuit. [19]
The constant current power supply is capable of retrieving the energy back from the circuit. Thus,
adiabatic logic circuits require non-standard power supplies with time varying voltages such as
pulsed power supplies. To meet today’s power requirement, most research has focused on
building adiabatic logic, which is a promising design for low power applications at present.
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5.2. Classification of Adiabatic logic families
Adiabatic logic is broadly classified into two categories. They are partially adiabatic logic and
fully adiabatic logic [19].
5.2.1. Partially Adiabatic logic
In partially adiabatic or Quasi adiabatic circuits, some charge gets transferred to the ground i.e.
some heat is dissipated. Hence a part of the energy is only 4255being able to recover, but these
circuits are easy to implement as compared to fully adiabatic logic circuits.
Some partially adiabatic logic families are: -
1. Efficient Charge Recovery Logic (ECRL)
2. 2N-2N2P Adiabatic Logic
3. Positive Feedback Adiabatic Logic (PFAL)
4. Clocked Adiabatic Logic
5.2.2. Fully Adiabatic
In fully adiabatic circuits, all the charges on the load capacitance gets recovered and feedback to
the power supply. Due to which fully adiabatic circuits become slower and complex as compared
to partial adiabatic circuits [20].
Some fully adiabatic logic families are: -
1. Pass Transistor Adiabatic Logic (PAL)
2. Two Phase Adiabatic Static CMOS Logic (2PASCAL)
3. Split-Rail Charge Recovery Logic (SCRL).
Yet some complexities in adiabatic logic design perpetuate. Two such complexities, for instance,
are circuit implementation for time-varying power sources needs to be done and computational
implementation by low overhead circuit structures needs to be followed.
There are two big challenges of energy recovering circuits; first, slowness in terms of today’s
standards, second it requires ~50% of more area than conventional CMOS, and simple circuit
designs get complicated.
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Fig.13 Variation of power dissipation with frequency for different
Fig .13 shows the comparision of performance of different adiabatic logic adder circuits with
traditional CMOS adder circuits for different full adder circuits. Y.sunil gavaskar reddy et al[21]
implemented and their analysis shows that designs based on adiabatic principle gives superior
performance when compared to traditional approaches in terms of power even though their
transistor count is high in some circuits.
adiabatic logic is an effective alternative for traditional CMOS logic circuit design.
6. CONCLUSION
In this paper we presented various power optimization techniques almost in all levels of design. It
can be concluded that the important
power, propagation delay and the PDP are strongly inter related.
Table.1 Advantages and Disadvantages of Power Optimization Techniques
Technique
MTCMOS [10] Power efficient
Transistor
Stacking [11]
Easy to implement, leakage saving, easy to
fabricate
Sleepy stack [12] Single threshold transistors, less delay
compared to transistor stacking
LECTOR [14] Control circuit is not required. Best power
savings in both the modes of operation
Body bias [15] More power savings
Clock gating [16] Medium power
Dual Vdd [17] Medium power savings
DVFS [18] More power savings
Adaptive voltage
scaling [18]
Efficient in power
Improves performance compared to DVFS.
Adiabatic [21] More power savings
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
Fig.13 Variation of power dissipation with frequency for different fulladder circuits using different
adiabatic logic [21]
Fig .13 shows the comparision of performance of different adiabatic logic adder circuits with
traditional CMOS adder circuits for different full adder circuits. Y.sunil gavaskar reddy et al[21]
mented and their analysis shows that designs based on adiabatic principle gives superior
performance when compared to traditional approaches in terms of power even though their
transistor count is high in some circuits. So for low power and ultra low power requirements
adiabatic logic is an effective alternative for traditional CMOS logic circuit design.
In this paper we presented various power optimization techniques almost in all levels of design. It
can be concluded that the important performance parameters such as dynamic power, leakage
power, propagation delay and the PDP are strongly inter related.
Table.1 Advantages and Disadvantages of Power Optimization Techniques
Advantages Disadvantages
Power efficient with no effect on speed More area
Easy to implement, leakage saving, easy to Propagation delay increases
Single threshold transistors, less delay
compared to transistor stacking
Needs to control circuits, area
increases, less power savings
Control circuit is not required. Best power
savings in both the modes of operation
Delay increases
More power savings Complexity in implementation
Medium power savings, less effect on speed Complexity in implementation
Medium power savings Effects on speed, control circuitry
is required
More power savings Complexity in implementation
Efficient in power savings,
Improves performance compared to DVFS.
Effects in speed
More power savings More area
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.1, February 2018
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fulladder circuits using different
Fig .13 shows the comparision of performance of different adiabatic logic adder circuits with
traditional CMOS adder circuits for different full adder circuits. Y.sunil gavaskar reddy et al[21]
mented and their analysis shows that designs based on adiabatic principle gives superior
performance when compared to traditional approaches in terms of power even though their
r requirements
In this paper we presented various power optimization techniques almost in all levels of design. It
performance parameters such as dynamic power, leakage
Disadvantages
Propagation delay increases
circuits, area
increases, less power savings
Complexity in implementation
Complexity in implementation
Effects on speed, control circuitry
Complexity in implementation
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Optimization of one parameter needs trade-off of other 3 parameters. To meet today’s power
requirement, most research has focused on building adiabatic logic, which is a promising design
for low power applications [21]. We can say here that adiabatic approach is advanced technique
for power reduction and it is giving better results than conventional methods. Domino logic is
mainly applied to have high speed operation. For this also there are many reduction techniques
and observed than power can be save for this logic also. Finally, we can conclude that this study
provides an appropriate choice for power optimization techniques technique for a specific
application by a VLSI circuit designer.
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AUTHORS
T. SUGUNA is a research scholar in E.C.E department, Dr M.G.R Educational and
Research Institute. Her area of research is in design of low power VLSI circuits.
M. JANAKI RANI working as professor in E.C.E Department, Dr M.G.R Educational
and Educational Research institute. She has 28 years of teaching experience. Her
teaching interests includes VLSI design, embedded systems Microprocessors and
Microcontrollers, Digital Electronics, Solid State Devices, VLSI Testing and Verification
etc.