This document discusses ASIC placement, which involves assigning exact locations to circuit components within a chip's core area. The goals of placement are to minimize the total interconnect length and costs while meeting timing requirements. It describes two main placement techniques - global placement, which groups cells to minimize interconnect between groups, and detailed placement, which further optimizes placement objectives. The document outlines various placement algorithms, goals, and trends like mixed-size placement and whitespace distribution to improve routability and performance.

1. ASIC DESIGN
MODULE - III
ASIC CONSTUCTION :
PLACEMENT
PRESENTED BY
HARSHADA BURUTE.

2. Contents
 Introduction
 Definition of placement
 Goals and objectives
 Placement layout
 Types of placements
 Placement steps
 Placement trends(solutions)
 References

3. Introduction
 Placement is an essential step in physical design flow since it assigns exact locations
for various circuit components within the chips core area.
 A placer takes a given synthesized circuit netlist together with a technology library and
produces a valid placement layout.
 Decide the locations of cells in a block.
 Selects the specific location for each logic block in the FPGA, while trying to
minimize the total length of interconnect required.
 Placement is much more suited to automation than floorplanning.
 Placement is a key step in physical design.
 Placement placed in ASIC design flow step no. 6 in physical design.

4. Placement position in ASIC design flow

5. Definition of placement
 Exact placement of the
modules (modules can
be gates, standard cells,
macros…).
 The general goal is to
minimize the total area
and interconnect cost.

6. Placement
 There are various types of placements.
 System-level placement: Place all the PCBs together such that Area
occupied is minimum and Heat dissipation is within limits.
 Board-level placement: All the chips have to be placed on a PCB. Area is
fixed. All modules of rectangular shape. The objective is to, minimize the
number of routing layers and Meet system performance requirements.
 Chip-level placement: Normally placement carried out along with pin
assignment

7. Placement goals & objectives
 Goals
 To arrange all the logic cells within the flexible blocks on a chip.
 Objectives
 Minimize all the critical net delays
 Minimize power dissipation
 Minimize crosstalk between signals
 Minimize the interconnect congestion
 Guarantee the router can complete the router step
 Minimize the total estimated interconnect length
 Specific timing requirement for critical nets

8. PLACEMENT
LAYOUT AREA
ROW CONSIST OF NUMBER OF SITES WHICH
CAN BE OCCUPIED BY THE CIRCUIT
COMPONENT.
LAYOUT AREA SPECIFIES THE FIX HEIGHT OF
ROWS.
STANDARD CELLS HAVE A FIXED HEIGHT
EQUAL TO ROWS HEIGHT BUT HAVE
VARIABLE WIDTHS.
BLOCKS CAN HAVE PREASSIGNED
LOCATIONS.
THIS IS CALLED MIXED MODE PLACEMENT.

9. BASIC
TECHNIQUES OF
PLACEMENT
GLOBAL PLACEMENT DETAILED PLACEMENT

10. GLOBAL PLACEMENT
 The goal of global placement is to find well spread, ideally with
no overlaps, placement for the given net list that attains
required objectives such as wirelength minimization or timing
specifications.
 Standard cells are placed into groups such that the number of
connections between groups is minimized.
 This is solved through circuit partitioning.

11. Algorithms
1. Simulated-annealing placers
2. Analytical placers
3. Min–cut placers –
Min cut placers operate in a top-down hierarchical fashion by recursively
partitioning a given netlist into partitions.
Where k>1 multiway partitioning
k=1 bisection partitioning
k=2 quadrisection partitioning
Divided into sub section for better results:
i) Min cut partitioners- k-way min cut partitioning
ii) Cut sequences- cut directions
iii) Capturing global connectivity- useful for improve placement results.

12. DETAILED PLACEMENT AND LEGALIZERS
 A placement is illegal if cells or blocks are overlaps.
 A detailed placer takes a legal placement and improve some placement objectives like wirelength
congestion.

13. DETAILED PLACEMENT AND
LEGALIZERS
 Goals of detailed placer and legalizers
 Remove all overlaps, and snap cells to sites with the minimum impact on
wirelength, timing and congestion.
 Improve wirelength by reordering groups of cells.
 Improve routability by carefully distributing free sites.
Classification of detailed placement into heuristic or exact methods.
1) Heuristic method : typically achieve good results in fast runtime.
2) Exact method : only applicable for a few cases and usually take longer
runtime.

15. PLACEMENT STEPS

16. Placement trends(solutions)
 Mixed size placement
 Simultaneously places cells and blocks.
 Whitespace distribution
Whitespace or free space is the percentage of placement sites not
occupied by cells and blocks.
 Whitespace enlarges the core layout area more than necessary for
placement, in order to provide larger routing area.
 Placement algorithms can allocate whitespace to improve performance
in a number of ways including congestion reduction, overlap
minimization, and timing improvement.
 Placement benchmarking
 Estimate the proper benchmark which described the performance gap
between the reported results.

17. Good placement vs. Bad placement
 Good placement
 No congestion
 Shorter wires
 Less metal levels
 Smaller delay
 Lower power dissipation
 Bad placement
 Congestion
 Longer wire lengths
 More metal levels
 Longer delay
 Higher power dissipation

18. REFERENCES
 Michael Smith, “Application Specific Integrated Circuits”
Pearson Education Asia , chapter 16.
 Andrew kahng and Reda, “digital layout – placement” ,chapter
5, EDA for IC implementation, circuit design and process
technology.
 Physical design flow