In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 56
A Survey on Low Power VLSI Designs
Raj Kumari1
, Madhu Priya2
, Mr. Subhash Chand3
1,2
PG Scholar, Department of ECE, NITTTR, Chandigarh, India
3
Associate Engineer HCL Infosystems, Noida, India
1
kumari09raj@gmail.com, 2
madhu19feb.89@gmail.com, 3
thakur.subhash578@gmail.com
Abstract- In today’s modern electronics industries energy or
power efficiency is most important feature to increase the
speed, portability, reliability, popularity and efficiency of
electronic products. Reduction in power consumption or low
power requirement for a system adds features of low cost,
high speed, more efficiency and reliability. CMOS
technology is a popular name in the field of low power
systems. In the field of CMOS technology various methods
are used to make the systems more power efficient like, use
of Sleepy transistors, Stack method in which transistor
length or width is increased to get reduction in leakage
power, use of pre-computation technique with the use of
BDD (Binary Decision Diagram), use of SRAM (Static
Random Access Memory) for high speed operations. In this
paper we survey low power systems in which various
techniques are used to reduce the power consumption in
different circuit areas of the system to get more power
efficient and cost effective electronic systems.
Keywords: Power consumption, Leakage power, Flip-Flop,
CMOS, BDD, Sleepy Transistor, Adders.
I. INTRODUCTION
In VLSI a few years ago cost, reliability, area,
performance, delays were considered as of major concern.
But as the time passes power becomes an area of major
concern. Now-a-days lower power consumption is one of
the important challenges for VLSI system designers. It is
important to save power in the electronic circuits without
compromising state integrity or performance [3]. Also in
this era of integration because of the popularity of
portable electronics products or battery operated
electronics systems,
low power systems becomes more popular. On reducing
the power consumption battery life increases as well as
overheating of the circuits can be removed. A major
application of low power consumption is in the field of
mobile technology, as these are battery operated devices.
There are so many power factors in a circuit i.e. switching
power, short circuit power, power in capacitance, gate
current, source leakage current, input rise time, leakage
power which affects the power consumption of a device.
And by controlling any of these, we can control the power
consumption in an electronics circuit. We analyze several
existing designs to verify different power optimization
techniques at different circuit levels. Reduction in power
also increases the reliability and efficiency of a device.
With this important need of low power consumption
systems development of CMOS technology comes into
existence. These devices are best known for their low
power requirements. But it is not enough to use only
CMOS devices to minimize the power requirement of
system. In CMOS devices power dissipation depends on
charging and discharging circuit nodes, where capacitors
are connected and switching of these capacitor transitions
per clock cycles. Another important dependence factor is
transition due to the short circuit current flowing from
supply to ground and one more is leakage current in the
circuit. The results of these factors are switching activity
power, short circuit power and leakage current power. To
minimize the total dissipated power in the circuit we
have to minimize all these three powers by applying
optimization at different levels of abstraction i.e. circuit,
logic, architecture and system level. This also focuses
on industrial and academic research to minimize power
dissipation at various abstraction levels. One another
reason for low power requirement is that, due to the
expensive packaging techniques, cooling management
system, which increases the density by a huge factor on
chip.
II. TECHNIQUES FOR LOW POWER
CONSUMPTION
In this section, we bring the main schemes which we
have surveyed from large number of papers. In these all
energy efficient techniques power abstraction is being
done at different levels of circuit [1].
Power Reduction at Logic Level
Power dissipation at logic level is most difficult to be
optimized or minimized, because of latches and flip-flops.
At logic level it is most important to reduce power in flip-
flops and clock distribution networks (CDN) [5]. One
technique utilized is clock gating. At logic level flip-flops
and latches are basic elements. In flip-flops we observed if
we use Pulse triggered flip-flop designs then because of
their shorter discharging paths they will consume low
power in the circuit.
A second case at logic level is a large amount of power is
consumed in clocking. And this power can be minimized or
optimized if we replace simple flip-flops with multi bit flip-
flops [9]. Power can be minimized because in multi bit, two
bit flip-flops can share the same clock. Hence power
consumed by clocking can be reduced further by replacing
several flip-flops with multi bit flip-flops. Therefore less

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57 NITTTR, Chandigarh EDIT-2015
number of clock sinks exists, and that clock network would
have smaller power consumption.
One more pre-computation technique is used in CMOS
circuits to minimize power consumption i.e. use of BDD
(Binary Decision Diagrams) [14]. BDD is directed acyclic
graph (DAG), which represents a Boolean function as a sum
of disjoint product form [18]. BDD are binary decision trees
for any expression and these are MUX (Multiplexer) based
realization. Number of MUX required for a circuit depends
on the BDD tree [11]. This MUX realization for a circuit is
done using different power reduction techniques.
Power Reduction at Arithmetic and Logical Unit (ALU)
In most of the electronic circuits which are designed using
VLSI technique an arithmetic logical unit is present which is
used to perform arithmetic operations and calculations like
addition, subtraction, multiplication and division are
performed. And it is noticeable that most of the power is
consumed at this part of circuit. To reduce this power
consumption we can use different adder circuits in ALU
which have less power requirements. We have surveyed
some of these circuits which reduces the power consumption
by an important factor by applying different techniques.
Generally transistors are used to build these important adder
circuitry. As with advancement in integration technology the
size of chips shrinking day by day and density of transistors
or other components is increasing by a huge amount [12].
And because of this leakage currents increases considerably,
thus increases the power consumption. Various techniques
are used to reduce this power consumption and one of these
techniques is Stack method using sleepy transistors [21]. A
sleepy transistor method gives a leakage power reduction
with 12.486 ụw as compare to other methods. In this method
power reduction can be achieved by increasing length or
width , by using clock gating, by implementing multiple
threshold CMOS etc [13].
Also a major use of ALU is in Mobile technology or in
microprocessors [10]. Thus an important application of low
power consumption is in the field of mobile technology. As
these are using adders in ALU and also these are battery
operated devices. To save power we generally put device in
stand-by mode in which a portion of circuit is disconnected
from power or shut down. As mentioned above a leakage
current also consume power when it is off. Now to reduce
this leakage power here again we can utilize the properties
of Sleepy transistor. In this technique of power gating Sleep
transistor is added between actual ground rail and circuit
ground or virtual ground. Thus device is turned off to cut-off
the leakage current. In this way sleepy transistor is used in
applications of low power consumption to reduce to total
consumed power.
In high performance and portable applications to increase
energy efficiency one more adder used in ALU is SERF full
adder [24]. SERF full adder is an optimized full adder which
is based on XOR gate [19] [20] [22]. Full adders are utilized
in multiplier modules of DSP filters.
By knowing the fact that in case of adders speed is limited
by time taken by carry to propagate through adder, Which
also increases the total power consumption of adders. An
adder CSLA (Carry Select Adder) [45] is developed which
is a compromise between small area longer delay and longer
area shorter delays [29]. It uses multiple pairs of ripple carry
adder (RCA) to generate partial sum and carry by
considering carry input either 0 or 1[30]. Then final sum and
carry are selected by multiplexer.
Power Reduction at Circuit Level
Power reduction at circuit level can be done by reducing
power consumption across transistors or components used
on the chip.
One technique to reduce power at circuit level is to use
MOS transistor in di-erent modes i.e. weak and strong
inversion layers. These di-erent modes of transistors can be
implemented using CNN (Cellular Neural Network) [34].
CNN model is main characteristic of low power
consumption, programmability [25]. Chua—Yang model is
generally used for simple circuits which is a special type of
analog, non-linear processor array [43]. Due to regularity,
parallelism and local connectivity found in CNN circuit
array it is used for VLSI implementation. To reduce power
consumption we process the small currents using MOS
transistors in weak inversion for all di-erential pairs.
Second low power consumption technique is to use Scaling
and Voltage Islands [44]. This technique partitions the
circuit into multiple voltage and frequency islands which
reduces the dynamic and leakage power. This technique is
similar to the Sleepy transistor technique in which transistor
switches off the portion of circuits which are in rest state or
not active, to reduce the power consumption. Same is done
here using voltage Islands [26]. Voltage Islands reduces the
power by selectively shutting down the different portion of
chip and run only selected parts at different voltage and
frequency levels. This is done at software level with the
compiler support using voltage islands. This technique has
better performance, energy savings and voltage scaling of
memory.

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NITTTR, Chandigarh EDIT -2015 58
Power Reduction at Bus Interfaces
An idea to reduce power dissipation in circuits comes
from the fact that an important part of power is dissipated
by the buses [39], which are used for the communication
of circuit components. Thus to reduce power dissipation
efforts are made for low power bus design.
As a result a technique Bus – invert (BI) [33] [46] Coding
is designed to reduce the power dissipation by reducing
the number of bus transitions. It is very simple and usable
technique because of which a large number of BI (Bus-
Invert) algorithms are developed [35]. A major drawback
of Bus-Invert technique is, increase in bus areas and
because of which degradation occurs into its transition
[36].
Therefore a new technique is introduced to overcome
this limitation of BI technique. This new technique is
TBIC (Two-bit Bus Invert Coding) [37]. It divides an n-
bit bus into n/2 sub-buses of width 2 and BI coding is
individually applied to each sub-bus [38] . It reduces the
bus transition by about 45.7%. Hence total power
dissipation reduces as the bus transitions get reduced.
III. CONCLUSION
In this paper, we have surveyed various energy
efficient techniques from device level to thee architecture
level to overcome the problem of power dissipation.
Through this whole survey we observed how devices,
circuits and architecture within the design space can be
optimized for minimum energy consumption. There are so
many power factors in a circuit like switching power,
short circuit power, power in capacitance, gate current,
source leakage current, input rise time, leakage power,
which affect the power consumption of a device. And by
controlling any of these factors we can control the power
consumption in a circuit. It is observed that a number of
parameters like leakage current, input supply voltage
level, frequency of operation, load capacitance, rise time,
switching power, power dissipation capacitance and
loading effect directly affects the power consumption of a
circuit. Thus if, power consumption is reduced it results in
so many benefits like, no requirement of heat sinks
because of very less heat generation in the circuit due to
low power. Also circuit size get reduced due to the
removal of heat sinks or other components associated with
high temperature. Due to small sizes reliability of system
also increases and cost of product get reduced. Low power
consumption also increases the portability and life of
battery in all the battery operated systems. In future we
will work on an energy efficient design which includes
these all power consumption reduction techniques at
different circuit levels and thus get minimum total power
consumption.
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