The document outlines various data transfer mechanisms used in computer-based data acquisition, focusing on polling, interrupts, and DMA (Direct Memory Access). It describes the functionality of DMA controllers on PC motherboards, detailing native and bus-master DMA types, as well as their implementations and performance implications. Additionally, it provides insights into the DMA operation code flow and references for further reading on related topics.

1. Data Transfer Mechanisms
➢ In computer-based data acquisition applications,
data incoming or outgoing through computer I/O
devices must often be managed at high speeds
or in large quantities. The three primary data
transfer mechanisms:
➢ Polling
➢ Interrupts ( Programmed I/O)
➢ DMA

2. DMA Transfer

3. DMA Controller
The PC motherboard has a DMA controller on the South Bridge that can
master
the I/O bus and initiate DMA to or from a peripheral.
This is usually the case for legacy ISA cards.
Can be viewed in /proc/dma on Linux machines

4. On Galileo

5. DMA Implementations
➢ Native DMA
➢ ISA Bus-master DMA
➢ PCI Bus-master DMA

6. Native DMA
The only pieces of legacy hardware that use
ISA DMA and are still fairly common are Super
I/O devices on motherboards that often
integrate a built-in floppy disk controller, an
IrDA infrared controller when FIR (fast infrared)
mode is selected, and a IEEE 1284 parallel port
controller when ECP mode is selected.

7. Native DMA

8. ISA Bus-master DMA
● lshw command on terminal

9. PCI Bus-master DMA

10. PCI Bus-master DMA

11. PCI IDE Bus-mastering
● The PCI bus also allows you to set up
compatible IDE/ATA hard disk drives to be bus
masters. Under the correct conditions this can
increase performance over the use of PIO
modes, which are the default way that IDE/ATA
hard disks transfer data to and from the system.
When PCI bus mastering is used, IDE/ATA
devices use DMA modes to transfer data
instead of PIO.

12. PCI IDE Bus-mastering

13. PCI IDE Bus-mastering
● hdparm -i /dev/sda
●

14. Bitbake menuconfig

17. DMA Controller in Galileo

18. Quark SoC Block Diagram

19. Channels Present
ls -l /sys/class/dma

20. Used and Unused Channels

21. Inserting our module

22. dmesg

23. Execution of a DMA-operation (single block transfer)
1)The CPU prepares the DMA-operation by the construction
of a descriptor , containing all necessary information for the
DMAC to independently perform the DMA-operation (off-
load engine for data transfer).
2)It initializes the operation by writing a command to a
register in the DMAC (2a) or to a special assigned memory
area (command area), where the DMAC can poll for the
command and/or the descriptor (2b).
3)Then the DMAC addresses the device data register
4) and reads the data into a temporary data register .
5)In another bus transfer cycle, it addresses the memory
block and
6) writes the data from the temporary data register to the
memory block .

26. dmesg after rmmod

27. Contd.

28. Issues faced on Ubuntu

29. Code Flow

30. External links and References
➢ LDD 3- DMA
➢ Essential Linux Device Drivers
➢ https://en.wikipedia.org/wiki/Direct_memory_access
➢ http://www.pcguide.com/ref/mbsys/buses/types/pciID
➢ http://www.pcguide.com/ref/hdd/if/ide/confControllers
➢ http://www.tweak3d.net/articles/howbusmaster/3.sht
● Intel Quark SoC Datasheet

31. External links and References
● Intel ICH7 Datasheet
● Intel ICH5 Datasheet
● http://stackoverflow.com/questions/28868932/using
● National Instruments Application Note 011-DMA
Fundamentals on Various PC Platforms
● http://zeus.nyf.hu/~bajalinov/OS/07/dma.pdf

32. Thanks