3. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
DMA CONTROLLER 8257
In microprocessor based system, data transfer can be controlled by either
software or hardware. To transfer data microprocessor has to do the
following tasks:
● Fetch the instruction
● Decode the instruction
● Execution of the instruction
4. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● Microprocessor needs some amount of time to complete these tasks. But
this data transfer is not suitable for large data transfer such as data
transfer from magnetic disk or optical disk to memory. In this situation
hardware controlled data transfer technique is required.
● The Direct Memory Access or DMA mode of data transfer is the fastest
amongst all the modes of data transfer.
● In this mode, the device may transfer data directly to/from memory without
any interference from the CPU.
5. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● Intel‘s 8257 is a four channel DMA controller designed to be interfaced with
their family of microprocessors. Each channel can be independently
programmable to transfer up to 64kb of data by DMA. Each channel can be
independently perform read transfer, write transfer and verify transfer.
● In maximum mode of the microprocessor RQ/GT pin is used as bus request input.
● On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in
maximum mode) from the CPU, the requesting devices gets the access of
the bus, and it completes the required number of DMA cycles for the data
transfer and then hands over the control of the bus back to the CPU.
6. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Memory DMA
Peripheral
Devices
CPU
● DMA is a device that is programmed to perform a sequence of data transfers
on behalf of the CPU.
● DMA can directly access memory and is used to transfer data from one
memory to another or from an I/O device to memory and vice versa.
● DMA manages several channels, each of which can be programmed to
perform a sequence of these data transfers.
7. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● During any given bus cycle, one of the system components connected to the
system bus is given control of the bus. This component is said to be the
master during that cycle and the component it is communicating with is said
to be the slave.
● The CPU with its bus control logic is normally the master, but other
specially designed components can gain control of the bus by sending a bus
request to the CPU.
● After the current bus cycle is completed the CPU will return a bus grant
signal and the component sending the request will become the master.
10. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
VCC and GND – power supply connections [+ 5V power supply]
CS:
● It is active low, Chip select input line.
● Used to enable controller onto the data bus for CPU communication.
RESET:
● Used to clear mode set registers and status registers, request and temporary
registers i.e. becomes zero
● Active High signal (1)
● Reset the DMA by disabling all the channels.
11. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
READY:
● Active high asynchronous input line.
In master mode
● When ready is high it received the signal.
● When ready is low, it adds wait state between S1 and S3
● In slave mode ,this signal is ignored.
HRQ:
● It is used to receive the hold request signal from the output device.
HLDA:
● It is acknowledgment signal from microprocessor
12. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
DRQ0-DRQ3(DMA Request):
● These are the asynchronous peripheral request input signal to obtain DMA
service.
● The request signals is generated by external peripheral device.
● DRQ0 has highest priority and DRQ3 has least priority.
● DRQ must be maintained until the corresponding DACK goes active.
DACK0-DACK3:
● These are the active low DMA acknowledge output lines.
● Low level indicate that ,peripheral is selected for giving the information (DMA
cycle).
● In master mode it is used for chip select.
13. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
D0-D7:
● it is a bidirectional ,tri-state ,Buffered ,Multiplexed data (D0-D7)
● In the slave mode it is a bidirectional (Data is moving).
● In the Master mode it is a unidirectional (Address is moving).
IOR:
● It is active low bidirectional lines.
● It is used to access data from the peripherals.
IOW:
● It is active low ,tri-state ,buffered ,Bidirectional control lines.
● In the slave mode it is an input signal used by CPU to load data into 8257.
● In the master mode it is an output signal used by 8257 to load data to the peripherals.
14. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
A0-A3: Lower order address
A4-A7: Higher order address
AEN (Address enable):
● It is a control output line.
● In master mode ,it is high
● In slave mode ,it is low
● Used to isolate the system address ,data ,and control lines.
ADSTB: (Address Strobe)
● It is a control output line.
● Used to split data and address line.
● It is works in master mode only.
● In slave mode it is ignored.
15. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
MEMR:
● It is active low control output line.
● Read the data from a memory location
MEMW:
● It is active low control input line.
● Write the data into selected memory location
TC (Terminal Count):
● It is a status of output line.
● It is activated in master mode only.
● If it is high ,it selects the peripheral.
● If it is low ,its free and looks for a new peripheral.
MARK:
● It is a modulo 128 MARK output line.
● It is activated in master mode only.
● It goes high ,after transferring every 128 bytes of data block.
17. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
The functional Block Diagram of DMA controller(8257) is shown in Figure. It
consists of five functional blocks:
a) Data bus buffer
b) Control logic
c) Read/write logic
d) Priority Resolver
e) DMA channels
19. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Data Bus Buffer:
● 8-bit Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system
bus under the control of various control signals.
● In the slave mode it is used to transfer data between microprocessor and internal registers of
8257. In the master mode, it is used to send higher byte address (A8 – A15) onto the data
bus.
Read/Write Logic:
● In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the
Ao-A3 lines and either writes the contents of the data bus to the addressed internal register
or reads the selected register depending upon whether IOW or IOR signal is activated.
● In master mode, the read/write logic generates the IOR and IOW signals to control the data
flow to or from the selected peripheral.
20. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Control Logic:
The control logic controls the sequences of operations and generates the
required control signals like AEN, ADSTB, MEMR,MEMW, TC and MARK
along with the address lines A4-A7, in master mode.
Priority Resolver:
The priority resolver resolves the priority of the four DMA channels depending
upon whether normal priority or rotating priority is programmed.
22. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Register Organization of 8257:
● The 8257 performs DMA operation over four independent DMA channels with
the following Registers.
DMA Address Register
● Each DMA channel has one DMA address register. The function of this
register is to store the address of the starting memory location, which will be
accessed by the DMA channel.
● The device that wants to transfer data over a DMA channel, will access the
block of the memory with the starting address stored in the DMA Address
Register.
23. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Format of DMA Address Register
Format of Terminal Count Register
24. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Terminal Count Registers
● Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit
register is used for ascertaining that the data transfer through a DMA channel ceases or
stops after the required number of DMA cycles.
● After each DMA cycle, the terminal count register content will be decremented by one and
finally it becomes zero after the required number of DMA cycles are completed. The bits 14
and 15 of this register indicate the type of the DMA operation (transfer).
Mode Set Register
● The mode set register is used for programming the 8257 as per the requirements of the
system. The function of the mode set register is to enable the DMA channels individually and
also to set the various modes of operation as shown in Figure
26. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● The bits Do-D3 enable one of the four DMA channels of 8257.If the TC STOP bit is set, the
selected channel is disabled after the terminal count condition is reached, and it further
prevents any DMA cycle on the channel.
● If the TC STOP bit is programmed to be zero, the channel is not disabled, even after the
count reaches zero and further request are allowed on the same channel.
● The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without
immediate software intervention between the two successive blocks.
● The extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by
activating them earlier, which is useful in interfacing the peripherals with different access
times.
27. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Status register
● The lower order 4-bits of this register contain the terminal count status for the
four individual channels. If any of these bits is set, it indicates that the specific
channel has reached the terminal count condition.
● The update flag is not affected by the read operation. This flag can only be
cleared by resetting 8257.
● The update flag is set every time, the channel 2 registers are loaded with
contents of the channel 3 registers. It is cleared by the completion of the first
DMA cycle of the new block. This register can only read.
29. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Operating Modes
● In 8257 when set, the various bits in Mode set register enable each of the four DMA
channels and allow four different Operating Mode options for the 8257.
● The use of this mode register is to enable/disable a channel.
Rotating priority
● In mode set register Bit D4 is
● set to one then the channels will have rotating priority and if it is zero, then channels will have
the fixed priority.
● In rotating priority the channels will have a circular sequence. In this channel being serviced
will get the lowest priority and the channel next to it will get the highest priority.
30. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● Thus with rotating priority mode in a single chip DMA system, any device
requesting services is guaranteed to be recognized after no more than three
high priority services have occurred.
31. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Fixed priority
● In fixed priority after recognition of any one channel for service, the other
channels are prevented from interfering with that service until it is completed.
● If Bit 4 of mode set register is logic 0, operating modes of 8257 operates in
fixed priority mode.
32. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Extended Write Mode
● If the Bit 5 is set to one, then the timing of low write signals (MEMW and IOW) will
be extended.
● Microcomputer systems allow use of various types of memory and I/O devices
with different access time.
● If a device cannot be accessed within a specific amount of time it returns a “not
ready” indication to the 8257 that causes the 8257 to insert one or more wait
states in its internal sequencing.
TC STOP mode
● If the Bit 6 is set to one then the DMA operation is stopped at the terminal count.
● If TC STOP bit is set, a channel is disabled.
33. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Auto Load Mode
● In this mode, channel 2 parameters (DMA starting address, terminal count
and DMA transfer mode) are initialized as usual for the first data block.
● These parameters are automatically duplicated in the channel 3 registers
when channel 2 is initialized.
● After the first block of DMA cycles is executed by channel 2 (i.e., after the TC
output goes high), the parameters stored in the channel 3 registers are
transferred to channel 2 during an ‘update’ cycle and next block of DMA cycle
is executed.
34. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
DMA Cycles
● DMA READ : In this cycle, data is transferred from memory to I/O device.
● DMA Write : In this cycle, data is transferred from I/O device to memory.
● DMA Verify : In this cycle, data is not transferred between memory and I/O It
is used by the, peripheral device to verify the data that has been recently
transferred. To avoid overwriting registers of channel 3, update flag in the
status register can be monitored by the CPU.
36. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● Intel 8255 is a peripheral interface (PPI) chip which is programmable.
● It is used for the connection of peripheral devices and interfacing peripheral
devices and the microprocessor for parallel data transfer. We call Peripheral
device also as Input Output device.
● Use Input Output ports for the connection of Input Output devices. Hence 8255 is
a programmable Input Output port chip.
● It can be used with almost any microprocessor.
● 8 pins connect the 8255 to an 8-bit bidirectional CPU data bus.
● 24 pins are attached to several IO devices and are programmable, in that the
functions they perform are determined by a control word issued by CPU
instruction and stored internally in the 8255.
● Control word can specify a variety of operating modes.
38. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Features
● It is a 40 pin chip available for dual line packaging. Power supply of +5 Volt DC
is needed for its working.
● 24 I/O lines
3 ports
Port A (8 lines)
Port B
(8 lines)
Port C (8 lines)
4 lines Cupper
4 lines Clower
PC4 – PC7
PC0 – PC3
PA0 – PA7
PB0 – PB7
39. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● These ports are again grouped as
Total 12 lines available in each group
● Each port can be programmed either as an input port or output port.
● The two groups can be programmed in different modes.
○ Bit set / reset mode
○ Input/output mode
Group A Group B
Port A (8) Port B (8)
Port Cu (4) Port CL (4)
41. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
CS : Chip select
A low on this input selects the chip and enables the communication between the 8255
and the CPU.
RD : Read Input
When this signal is low 8255 sends out data or status information to the CPU on the
data bus i.e. CPU reads data from the ports.
WR: Write Input
A low on this input pin enable the CPU to write data or control words into the 8255 i.e.
CPU writes data onto the ports.
CPU 8255
RD
WR
42. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
A1, A0: Port select pins
These input signals along with RD and WR input control the selection of the
control/status word registers or one of the three ports.
A1 A0 RD WR CS
0 0 0 1 0 Port A Data bus
0 1 0 1 0 Port B Data bus
1 0 0 1 0 Port C Data bus
0 0 1 0 0 Data bus Port A
0 1 1 0 0 Data bus Port B
1 0 1 0 0 Data bus Port C
1 1 1 0 0 Control Register
Input operation
Output operation
43. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
RESET
● A high on this pin clears the control register and all ports (A, B and C) are
initialized to input mode. This connected to RESET OUT
● This is done to prevent destruction of circuitry connected to port lines.
D0 – D7 : Data bus
● These tri-state bidirectional data bus lines are connected to the system data bus.
● They are used to transfer data and control word from microprocessor to 8255 or to
receive data or status word form 8255 to the microprocessor.
44. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
PA0 – PA7 (Port A)
● These 8-bit bidirectional I/O pins are used to send data to output device and
receive data from input device.
● It functions as an 8-bit data output latch/buffer when used in output mode and 8-
bit input data latch/buffer when used in input mode.
PB0 – PB7 (Port B)
● These 8-bit bidirectional I/O pins are used to send data to output device and
receive data from input device.
● It functions as an 8-bit data output latch/buffer when used in output mode and 8-
bit input data latch/buffer when used in input mode.
PC0 – PC7 (Port C)
● These 8-bit bidirectional I/O pins are divided into two groups that individually can
transfer data in or out when programmed for simple I/O.
47. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Functional Units:
1. Data Bus buffer
2. Read and Write Control logic
3. Group A and Group B Control Units
4. I/O ports
Data Bus Buffer
● It is a tri-state, bidirectional 8-bit buffer used to interface 8255 to the system bus of
CPU.
● It is used to transfer/receive data upon the execution of IN and OUT instructions
by the CPU, control word and status between 8255 and the processor.
48. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
I/O ports:
● 8255 has three 8-bit ports [24 pins] and they are Port A, Port B and Port C.
● The 24 I/O bidirectional pins are arranged in two groups of 12 pins.
● Group A : Port A (8) and Port Cupper (4)
● Group B : Port B (8) and Port Clower (4)
● Port A can be programmed in all modes
● Port B can be programmed in mode0 and mode1
● Port C can be programmed in BSR mode.
Group A and Group B Control Units
● Each of the group A and B control blocks receive the control words fro the CPU and provide
appropriate commands to each port.
● Control word is written into control register by CPU.
49. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Timing and Control Logic Unit
These are six control input signals from the processor
RD, WR, A0,A1, RESET and CS
50. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Operational Modes of 8255
● Each port can be programmed either as an input port or an output port.
● The function of the ports is defined by writing a control word in the control
register.
● Each group of ports can be programmed in different modes.
1. Input/output mode
2. Bit set/reset mode
● Control register – 8bit register
● Control word – 8 bit word written in the control register
Lets look into the functioning of control word.
51. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Internal
Decoding
Control
Register
Port A
Port C
Port B
WR WR
WR
WR
EN
EN
EN
EN
RD
RD
RD
CS
A1
A0
Port C
Port B
Port A
11
10
01
00
00
10
01
Control word
provided
by MP
52. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
CS
A1 A0
Hex
Address
Ports
A7 A6 A5 A4 A3 A2
1 0 0 0 0 0 0 0 80H Port A
0 1 81H Port B
1 0 82H Port C
1 1 83H Control
Register
8085 8255
A0 – A7 I/O device
53. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● So these addresses are provided by the 8085 MP and when these addresses are
given, then the respective ports or the control register is selected by the 8255.
● For example if the 82H address is given and RD signal is activated then whatever the
data available in port C that is being read by the microprocessor which is given by the
8255.
● Now when the 83H address is sent and WR signal is activated then the 8bit data which
is available on the data bus D0-D7 in 8085, that 8bit data will be written into the control
register. This 8bit data is called control word.
● This control word decides in which mode the 8255 is working.
1 / 0
D7 D6 D5 D4 D3 D2 D1 D0
I/O mode BSR mode
54. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Bit set/reset mode
● This mode is used to set or reset the bits of port C (PC0 – PC7)
● BSR mode does not affect the function of port A and port B
● Bit D7 of control word is zero(reset)
55. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Input/output Mode
● If in control word Bit 7 = 1 then I/O mode will work.
● 3 modes – mode0, mode 1, mode 2
● The ports A, B and C can work in any of these modes
Group A Group B
56. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● Mode 0: Simple I/O mode
● Mode 1: I/O mode with handshake
when ports use some of the lines of other
ports for its use.
To sync MP and I/O devices i.e. valid
connection.
● Mode 2: Bidirectional mode
Used to transfer data between two computers or floppy disks.
57. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Mode 0
● In this mode port A and port B are used as 8bit I/O ports.
● Port C is used as two 4-bits I/O ports
● Each port can be programmed to function as Input port or Output port.
● Outputs are latched and Inputs are not latched
● Ports do not have handshake or interrupt capability.
Ex: Configure
● Port A and port CU as out port
● Port B and port CL as in port
59. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Interfacing switches and LEDs
Problem: Interface an 8255 with 8086 to work as an I/O port. Initialize port A as o/p port , port B as
i/p port and port C as o/p port. Port A address should be 0704H. Write a program to sense
switch portions SW0 – SW7 as port B.
The sensed pattern is to be displayed on port A, to which 8 LEDs are connected, while the
port C lower displays number of on switches out of total 8 switches.
Solution: Given Port A address is 0704H
CWR format
B7 B6 B5 B4 B3 B2 B1 B0
1 0 0 0 0 0 1 0
82H
I/O mode
Port A
Mode 0
Port A
o/p
Port C
o/p
Port B
Mode 0
Port B
i/p
Port C
o/p
61. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
● The 8255 is to be interfaced with lower order data bus; i.e. D0-D7.
● The A0 and A1 pins of 8255 are connected to A1 and A2 pins of the
microprocessor respectively. We will use absolute decoding scheme that
uses all the16 address lines.
● For deriving the device address pulse. Out of A0 - A15 lines, two address
lines A2 and A1 are directly required by 8255 for three port and CWR address
decoding. Hence only A3 to A15 are used for decoding addresses.
● Circuit diagram, the 8086 is assumed to be in the maximum mode so that
IORD and IOWR are readily available.
64. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
DAC 0808
● A DAC or digital-to-analog converter in electronics is one kind of system, used
to change a digital signal to an analog signal.
● DAC architectures are classified into different types based on the merits such as
resolution, maximum sampling frequency, and many more.
● The applications of DACs include music players, televisions, mobiles, etc.
● The IC DAC0808 is a digital to analog converter, used to convert a digital data
input to analog signal output, where the input is an 8-bit data.
● This IC is a monolithic integrated circuit, the accuracy of this IC in conversion is
good as well as power utilization is also less for making it prominent.
66. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Pin diagram
The IC DAC0808 includes 16-pins and each
pin description is discussed below.
67. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Pin Name Description
1 NC No connection
2 GND Ground
3 VEE Negative power supply
4 IO Output signal pin
5 A1 Digital input bit 1 (Most
Significant Bit)
6 A2 Digital input bit 2
7 A3 Digital input bit 3
8 A4 Digital input bit 4
Pin Name Description
9 A5 Digital input bit 5
10 A6 Digital input bit 6
11 A7 Digital input bit 7
12 A8 Digital input bit 8 (Least
Significant Bit)
13 VCC Positive power supply
14 VREF+ Positive reference voltage
15 VREF- Negative reference voltage
16 COMPENSATI
ON
Compensation capacitor pin
69. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
In circuit
● For the working of device DAC0808, we need two voltage sources +5V and -
15V as shown in the diagram. This is a major drawback that is eliminated in
modern DAC to make them work from a single power source.
● Eight digital inputs are given to the chip and are supposed to be in order from
MSB to LSB. This is also a major drawback because we need to waste 8 I/O
pins. This is also eliminated in modern DACs.
● A +10V power source is connected as a reference voltage for the device and
the negative reference is grounded.
70. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Working
● The device takes in parallel 8-bit data from a microcontroller or microprocessor
and converts that data into an analog signal at the output.
● And the analog output from DAC is a current quantity, and this needs to be
converted into voltage parameters for use in application easily.
● So to convert the current parameter into voltage parameter, we will use an op-
amp circuit as shown in the circuit diagram. This op-amp circuit is called current-
to-voltage converter.
● The output analog voltage from op-amp is in linear relation with input digital value
and hence DAC conversion with DAC0808 is achieved. Similarly, you can also
use other application circuits for DAC0808 given in the datasheet.
72. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
ADC0808
● The process of conversion of analog signal to digital signal is referred to as
analog to digital conversion.
● ADC 0808 and ADC 0809 are monolithic CMOS devices with an 8-channel
multiplexer.
● These devices are also designed to operate from common microprocessor
control buses, with tri-state output latches driving the data bus.
74. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE,MVGRA
Operation
● ADC 0808/0809 has eight input channels, so to select desired input channel,
it is necessary to send 3-bit address on A, B and C inputs.
● The address of the desired channel is sent to the multiplexer address inputs
through port pins. After at least 50 ns, this address must be latched: This can
be achieved by sending ALE signal.
● After another 2.5 μs, the start of conversion (SOC) signal must be sent high
and then low to start the conversion process.
● To indicate end of conversion ADC 0808/0809 activates EOC signal.
● The microprocessor system can read converted digital word through data bus
by enabling the output enable signal after EOC is activated.
Because microprocessor is slow and when peripherals are ready for communication, the DMA controller will wait to synchronize microprocessor and the peripherals.
Tristate means three states i.e. Logic 0, Logic 1 and high impedance states. In high impedance state, the pin is neither connected to supply nor to ground. It removes the port from the circuit as it were not a part of it.
The Tristate Buffer is used in microprocessor circuits as they allow multiple logic devices to be connected to the same wire or bus without damage or loss of data.
For example, we have a data line or data bus with some memory, peripherals, I/O or a CPU connected to it.
In parallel data transfer mode, 8-bit data send all together with 8 parallel wire i.e. simultaneously over eight data lines (parallel I/O mode).
Note: Due to the difficulty as well as the requirement of exactly matched components, the most specific DACs are executed like Integrated Circuits (ICs)
Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) are very important components in electronic equipment. Since most real world signals are analog, these two converting interfaces are necessary to allow digital electronic equipments to process the analog signals.
Positive and negative voltages are approximately equal in value but opposite. Opposite in the sense that negative voltage is an excess of electrons and a positive voltage is a deficiency of electrons.
The reference voltage (generally known as Vref) is usually the maximum voltage value that the D/A converter can reach. This value depends on what is connected to the Vref pin.
The digital signal is represented with a binary code, which is a combination of bits 0 and 1.
A Compensation capacitor whose purpose is to be connected either in series or in parallel with a coil in a circuit.
Current is the rate of flow of electric charge.
Voltage is the energy per unit charge.