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Direct Memory Access (DMA)
Direct Memory Access (DMA)
• An I/O technique used for high data transfer
• Between memory and peripheral
• MPU releases the control of Buses
• DMA controller manages data transfer
8085 signals for DMA
• HOLD
• HLDA (Hold Acknowledge)
8257 DMA Controller
• Programmable DMA controller
• Primary function: a sequential memory access
which allow the peripheral to read or write
data directly to or from memory
• Has 4 independent channels each capable of
transferring 64Kbytes of data
• Must be interfaced with MPU and peripherals
8257 DMA Controller
• Plays two role:
– I/O to Microprocessor (Slave mode)
– Data transfer processor to peripherals
(Master mode)
• Has priority DMA request logic
8257 – Block Diagram
1. DMA Channels
2. Data Bus Buffer
3. Read/Write Logic
4. Control Logic
1. DMA Channels
• Four separate DMA channels (CH-0 to CH-3)
• Each channel includes two 16 bit regs
1. DMA address register
2. Terminal count register
• 14 bit count (N-1) is loaded into TC reg
– 2 msb’s give the type of DMA operation
• Signals DRQ0 to DRQ3, to
Type of DMA Operation
Bit 15 Bit 14 Type of DMA Operation
0 0 Verify DMA Cycle
0 1 Write DMA Cycle
1 0 Read DMA Cycle
1 1 (Illegal)
2. Data Bus Buffer
• This three-state, bi-directional, eight bit buffer
interfaces the 8257 to the system data bus
• D0 – D7
3. Read/Write Logic
• A0 – A3
• IOR, IOW
– Input signals in slave mode
– Output signals in master mode
• RESET
• CLK
• CS
4. Control Logic
• ADSTB (Address Strobe):
– This output strobes the most significant byte of
the memory address into the 8212 device from
the data bus
• AEN (Address Enable):
– Used to disable the system buses
• TC (Terminal Count)
• MARK (Modulo 128 Mark)
8257 Mode Word
DMA Execution
• Two modes:
– Slave Mode
– Master Mode
DMA Execution: Slave Mode
1. MPU unit selects the DMA Controller through
CS
2. MPU writes control register
Note:- In slave mode, IOR and IOW of 8257 are
input signals and MEMR and MEMW are tri-
stated.
DMA Execution: Master Mode
1. Peripherals sends DRQ
2. If Channel is enabled, ctrl logic sends HRQ
3. MPU relinquishes buses and sends HLDA
4. Controller asserts AEN high.
– Places high order address on its data bus and low
order address on its address bus.
– Then asserts ADSTB high which places high
address on A15 – A8
DMA Execution: Master Mode
5. Once address is kept on bus, DMA sends
DACK
6. DMA controller continues data tranfer
7. At the end of data transfer, DMA sends TC to
peripheral
8. DMA makes HRQ low

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Direct memory access (dma) with 8257 DMA Controller

  • 2. Direct Memory Access (DMA) • An I/O technique used for high data transfer • Between memory and peripheral • MPU releases the control of Buses • DMA controller manages data transfer
  • 3. 8085 signals for DMA • HOLD • HLDA (Hold Acknowledge)
  • 4. 8257 DMA Controller • Programmable DMA controller • Primary function: a sequential memory access which allow the peripheral to read or write data directly to or from memory • Has 4 independent channels each capable of transferring 64Kbytes of data • Must be interfaced with MPU and peripherals
  • 5. 8257 DMA Controller • Plays two role: – I/O to Microprocessor (Slave mode) – Data transfer processor to peripherals (Master mode) • Has priority DMA request logic
  • 6.
  • 7. 8257 – Block Diagram 1. DMA Channels 2. Data Bus Buffer 3. Read/Write Logic 4. Control Logic
  • 8. 1. DMA Channels • Four separate DMA channels (CH-0 to CH-3) • Each channel includes two 16 bit regs 1. DMA address register 2. Terminal count register • 14 bit count (N-1) is loaded into TC reg – 2 msb’s give the type of DMA operation • Signals DRQ0 to DRQ3, to
  • 9. Type of DMA Operation Bit 15 Bit 14 Type of DMA Operation 0 0 Verify DMA Cycle 0 1 Write DMA Cycle 1 0 Read DMA Cycle 1 1 (Illegal)
  • 10. 2. Data Bus Buffer • This three-state, bi-directional, eight bit buffer interfaces the 8257 to the system data bus • D0 – D7
  • 11. 3. Read/Write Logic • A0 – A3 • IOR, IOW – Input signals in slave mode – Output signals in master mode • RESET • CLK • CS
  • 12. 4. Control Logic • ADSTB (Address Strobe): – This output strobes the most significant byte of the memory address into the 8212 device from the data bus • AEN (Address Enable): – Used to disable the system buses • TC (Terminal Count) • MARK (Modulo 128 Mark)
  • 14. DMA Execution • Two modes: – Slave Mode – Master Mode
  • 15. DMA Execution: Slave Mode 1. MPU unit selects the DMA Controller through CS 2. MPU writes control register Note:- In slave mode, IOR and IOW of 8257 are input signals and MEMR and MEMW are tri- stated.
  • 16. DMA Execution: Master Mode 1. Peripherals sends DRQ 2. If Channel is enabled, ctrl logic sends HRQ 3. MPU relinquishes buses and sends HLDA 4. Controller asserts AEN high. – Places high order address on its data bus and low order address on its address bus. – Then asserts ADSTB high which places high address on A15 – A8
  • 17. DMA Execution: Master Mode 5. Once address is kept on bus, DMA sends DACK 6. DMA controller continues data tranfer 7. At the end of data transfer, DMA sends TC to peripheral 8. DMA makes HRQ low

Editor's Notes

  1. IOR and IOW are active low signals. When DMA is working in slave mode, it receives IOR and IOW signals from microprocessor, to send status and get settings respectively. When it is working in master mode it sends IOR and IOW signals to peripherals.