discuss the drawbacks of programmed and interrupt driven i/o and describe in general the functionality of the DNA Solution Programmed I/O Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control to access registers or memory on a device. The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time for the I/O module of concern to be ready for either reception or transmission of data. The CPU, while waiting, must repeatedly check the status of the I/O module, and this process is known as Polling. As a result, the level of the performance of the entire system is severely degraded. Programmed I/O basically works in these ways: Interrupt The CPU issues commands to the I/O module then proceeds with its normal work until interrupted by I/O device on completion of its work. For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved by the system processor. The actual actions to perform depend on whether the device uses I/O ports, memory mapping. For output, the device delivers an interrupt either when it is ready to accept new data or to acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually generate interrupts to tell the system they are done with the buffer. Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in data transfer of large amount because the CPU has to transfer the data word by word between I/O module and memory. The main limitation of programmed I/O and interrupt driven I/O is given below: Programmed I/O Each instructions selects one I/O device (by number) and transfers a single character (byte) Example: microprocessor controlled video terminal. Four registers: input status and character, output status and character. Interrupt-driven I/O Primary disadvantage of programmed I/O is that CPU spends most of its time in a tight loop waiting for the device to become ready. This is called busy waiting. With interrupt-driven I/O, the CPU starts the device and tells it to generate an interrupt when it is finished. Done by setting interrupt-enable bit in status register. Still requires an interrupt for every character read or written. Interrupting a running process is an expensive business (requires saving context). Requires extra hardware (DMA controller chip). All these limitation can be overcome by the Introduction of DMA (Direct Memory Access) To write block of 32 bytes from memory address 100 to device 4 1. CPU writes 32, 100, 4 into the first three DMA registers (memory address, count, device number) 2. CPU puts code for WRITE (say 1) into fourth (direction) DMA register, which signals DMA controller to begin operation 3. Controller reads (via bus request as CPU would) byte 100 from memory 4. Controller makes I/O request to write to device 4 5. Controller increments m.

1. discuss the drawbacks of programmed and interrupt driven i/o and describe in general the
functionality of the DNA
Solution
Programmed I/O
Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control
to access registers or memory on a device.
The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster
than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time
for the I/O module of concern to be ready for either reception or transmission of data. The CPU,
while waiting, must repeatedly check the status of the I/O module, and this process is known as
Polling. As a result, the level of the performance of the entire system is severely degraded.
Programmed I/O basically works in these ways:
Interrupt
The CPU issues commands to the I/O module then proceeds with its normal work until
interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved
by the system processor. The actual actions to perform depend on whether the device uses I/O
ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new data or to
acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually
generate interrupts to tell the system they are done with the buffer.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in
data transfer of large amount because the CPU has to transfer the data word by word between I/O
module and memory.
The main limitation of programmed I/O and interrupt driven I/O is given below:
Programmed I/O
Each instructions selects one I/O device (by number) and transfers a single character (byte)
Example: microprocessor controlled video terminal.
Four registers: input status and character, output status and character.
Interrupt-driven I/O
Primary disadvantage of programmed I/O is that CPU spends most of its time in a tight loop
waiting for the device to become ready. This is called busy waiting.
With interrupt-driven I/O, the CPU starts the device and tells it to generate an interrupt when it is

2. finished.
Done by setting interrupt-enable bit in status register.
Still requires an interrupt for every character read or written.
Interrupting a running process is an expensive business (requires saving context).
Requires extra hardware (DMA controller chip).
All these limitation can be overcome by the Introduction of DMA (Direct Memory Access)
To write block of 32 bytes from memory address 100 to device 4
1. CPU writes 32, 100, 4 into the first three DMA registers (memory address, count, device
number)
2. CPU puts code for WRITE (say 1) into fourth (direction) DMA register, which signals DMA
controller to begin operation
3. Controller reads (via bus request as CPU would) byte 100 from memory
4. Controller makes I/O request to write to device 4
5. Controller increments memory address register and decrements count register
6. Controller continues this loop until count decrements to 0
7. When count becomes 0 I/O is complete and controller asserts interrupt line on bus.
8. With DMA the CPU only has to start the I/O and respond to the final interrupt
9. There is only one interrupt per block of bytes input or output
10. Some DMA controllers can do two or more simultaneous I/O operations
11. DMA process is not free
– When controller wants to read/write via the bus it must make the CPU wait (DMA controller
always has higher priority on bus). This process is called cycle stealing
- DMA I/O is used on PCs and minicomputers.
A programmed I/O needs to be polled at regular intervals to detect its state, hence, a short
transition may NOT be detected.
An interrupted Input will generate an interrupt a any change of state, and the CPU will respond
(nearly) immediately to that change, entering and executing the interrupt routine.
A program has to wait and repeatedly tests the status; Waiting period for an asynchronous event
can be too large
Many I/O devices generate asynchronous events— events that occur at times that the processor
cannot predict or control, but which the processor must respond to reasonably quickly to provide
acceptable performance
Direct Memory Access (DMA)
Direct Memory Access (DMA) means CPU grants I/O module authority to read from or write to
memory without involvement. DMA module controls exchange of data between main memory
and the I/O device. Because of DMA device can transfer data directly to and from memory,

3. rather than using the CPU as an intermediary, and can thus relieve congestion on the bus. CPU is
only involved at the beginning and end of the transfer and interrupted only after entire block has
been transferred.
Direct Memory Access needs a special hardware called DMA controller (DMAC) that manages
the data transfers and arbitrates access to the system bus. The controllers are programmed with
source and destination pointers (where to read/write the data), counters to track the number of
transferred bytes, and settings, which includes I/O and memory types, interrupts and states for
the CPU cycles.
DMA increases system concurrency by allowing the CPU to perform tasks while the DMA
system transfers data via the system and memory busses. Hardware design is complicated
because the DMA controller must be integrated into the system, and the system must allow the
DMA controller to be a bus master. Cycle stealing may also be necessary to allow the CPU and
DMA controller to share use of the memory bus.
Direct Memory Access (DMA) is a capability provided by some computer bus architectures that
allows data to be sent directly from an attached device (such as a disk drive) to the memory on
the computer's motherboard. The microprocessor is freed from involvement with the data
transfer, thus speeding up overall computer operation.
Usually a specified portion of memory is designated as an area to be used for direct memory
access. In the ISA bus standard, up to 16 megabytes of memory can be addressed for DMA. The
EISA and Micro Channel Architecture standards allow access to the full range of memory
addresses (assuming they're addressable with 32 bits). Peripheral Component
Interconnectaccomplishes DMA by using a bus master (with the microprocessor "delegating"
I/O control to the PCI controller).
An alternative to DMA is the Programmed Input/Output (PIO) interface in which all data
transmitted between devices goes through the processor. A newer protocol for the ATA/IDE
interface is Ultra DMA, which provides a burst data transfer rate up to 33 MB (megabytes) per
second. Hard drives that come with Ultra DMA/33 also support PIO modes 1, 3, and 4, and
multiword DMA mode 2 (at 16.6 megabytes per second)
The DMA functions are:
ddi_dma_alloc_handle()
Allocate a DMA handle
ddi_dma_free_handle()
Free a DMA handle
ddi_dma_mem_alloc()
Allocate memory for a DMA transfer
ddi_dma_mem_free()

4. Free previously allocated DMA memory
ddi_dma_addr_bind_handle()
Bind an address to a DMA handle
ddi_dma_buf_bind_handle()
Bind a system buffer to a DMA handle
ddi_dma_unbind_handle()
Unbind the address in a DMA handle
ddi_dma_nextcookie()
Retrieve the subsequent DMA cookie
ddi_dma_getwin()
Activate a new DMA window
ddi_dma_numwin()
Retrieve number of DMA windows
ddi_dma_sync()
Synchronize CPU and I/O views of memory
ddi_check_dma_handle()
Check a DMA handle
ddi_dma_set_sbus64()
Allow 64-bit transfers on SBus
ddi_slaveonly()
Report whether a device is installed in a slave access-only location
ddi_iomin()
Find the minimum alignment and transfer size for DMA
ddi_dma_burstsizes()
Find out the allowed burst sizes for a DMA mapping
ddi_dma_devalign()
Find DMA mapping alignment and minimum transfer size
ddi_dmae_alloc()
Acquire a DMA channel
ddi_dmae_release()
Release a DMA channel
ddi_dmae_getattr()
Get the DMA engine attributes
ddi_dmae_prog()
Program a DMA channel
ddi_dmae_stop()

5. Terminate a DMA engine operation
ddi_dmae_disable()
Disable a DMA channel
ddi_dmae_enable()
Enable a DMA channel
ddi_dmae_getcnt()
Get the remaining DMA engine count
ddi_dmae_1stparty()
Configure the DMA channel cascade mode
ddi_dma_coff()
Convert a DMA cookie to an offset within a DMA handle