1. Direct Memory Access (DMA) allows input/output devices to directly access main memory, bypassing the CPU to speed up memory transfers. This is managed by a DMA controller. 2. During a DMA transfer, the DMA controller gains control of the address bus, data bus, and control bus from the microprocessor to transfer data directly between an I/O port and memory. 3. The DMA controller has several options for transferring data, including cycle stealing for single byte transfers, burst mode for block transfers using address sequencing, and hidden DMA which occurs transparently when the CPU is not using the bus.

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Note
IMRAN KHAN

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Md. Sumon Hossain Shahin 1#103#45
Md. Imran Khan 1#1030#5
Afroja Kabir 1#10326#
Israt Jahan 1#103308
Tania Sultana Jui 1#1#3270

3.  DMA
 Basic DMA operation
 DMA controller
 Data transfer with DMA controller
 DMA Controller options for data transfer
 Data Transfer modes
 Advantage & Disadvantage
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4. • Direct Memory Access (DMA) is a method that allows an
input/output (I/O) device to send or receive data directly to or
from the main memory, bypassing the CPU to speed up memory
operations. The process is managed by a chip known as a DMA
controller (DMAC).
DMA
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5. •DMA transfers are performed by a control circuit that is part of
the I/O device interface.
• It refer to this circuit as a DMA controller.
• The DMA controller performs the function that would normally
be carried out by the processer when accessing the main memory.
• Device wishing to perform DMA asserts the processors bus
request signal
• Processor completes the current bus cycle and then asserts the
bus grant signal to the device.
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DMA

6. • The direct memory access (DMA) I/O technique provides direct
access to the memory while the microprocessor is temporarily
disabled.
• A DMA controller temporarily borrows the address bus, data bus,
and control bus from the microprocessor and transfers the data
bytes directly between an I/O port and a series of memory
locations.
• The DMA transfer is also used to do high-speed memory-to-
memory transfers.
• Two control signals are used to request and acknowledge a DMA
transfer in the microprocessor-based system.
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8. During a block input byte transfer, the following sequence occurs as the data byte is sent from
the interface to the memory:
• The interface sends the DMA controller a request for DMA
service.
• A Bus request is made to the HOLD pin (active High) on the
8086 microprocessor and the controller gains control of the
bus.
• A Bus grant is returned to the DMA controller from the Hold
acknowledge (HLDA) pin (active High) on the 8086
microprocessor.

9. • The DMA controller places contents of the address register
onto the address bus.
• The controller sends the interface a DMA acknowledgment,
which tells the interface to put data on the data bus. (For an
output it signals the interface to latch the next data placed on
the bus.)
• The data byte is transferred to the memory location indicated
by the address bus.
• The interface latches the data.

10. • The Bus request is dropped, the HOLD pin goes Low, and the
controller relinquishes the bus.
• The Bus grant from the 8086 microprocessor is dropped and
the HLDA pin goes Low.
• The address register is incremented by 1.
• The byte count is decremented by 1.
• If the byte count is non-zero, return to step 1, otherwise stop

12. • The DMA Controller has several options available for the
transfer of data.
• They are:-
 Cycle steal
 Burst transfer
 Hidden DMA

13. 1) CYCLE STEAL
A read or write signal is generated by the DMAC, and the I/O
device either generates or latches the data. The DMAC
effectively steals cycles from the processor in order to transfer
the byte, so single byte transfer is also known as cycle stealing

14. 2). BURST TRANSFER
To achieve block transfers, some DMAC's incorporate an
automatic sequencing of the value presented on the address
bus. A register is used as a byte count, being decremented for
each byte transfer, and upon the byte count reaching zero, the
DMAC will release the bus. When the DMAC operates in burst
mode, the CPU is halted for the duration of the data transfer.

15. 3) HIDDEN DMA
It is possible to perform hidden DMA, which is transparent to
the normal operation of the CPU. In other words, the bus is
grabbed by the DMAC when the processor is not using it.
The DMAC monitors the execution of the processor, and when
it recognises the processor executing an instruction which has
sufficient empty clock cycles to perform a byte transfer, it waits
till the processor is decoding the op code, then grabs the bus
during this time. The processor is not slowed down, but
continues processing normally. Naturally, the data transfer by
the DMAC must be completed before the processor starts

16. DMA Data Transfer Modes
1. Single Transfer Mode 2. Block Transfer Mode
3. Demand Transfer Mode 4. Cascade Mode:
5. Memory to memory transfer
 Single Transfer Mode: In Single Transfer mode the device is
programmed to make one transfer only. In single mode only one
byte is transferred per request.
 Block Transfer Mode: Once the DMA controller is
granted access to the system bus by the CPU, it transfers all
bytes of data in the data block. This mode is called "Block
Transfer Mode". once a Block transfer is started, it runs until
the transfer count reaches zero

17. DMA Data Transfer Modes
 Demand Transfer Mode: Demand Mode DMA allows PC
hardware to transfer many bytes of data, via a DMA channel,
with only a single programming of the DMA controller.
 Cascade Mode: Used to cascade additional DMA
controllers Actual bus signals is executed by cascaded chip.
 Memory to memory transfer: To perform the transfer of
the block of data from one set of memory address to another
one ,this mode is used. This means data can be transferred
from one memory device to another memory device.

18. • DMA allows a peripheral device to read from/write to
memory without going through the CPU
• DMA allows for faster processing since the processor can be
working on something else while the peripheral can be
populating memory.
• DMA transfer requires a DMA controller to carry out the
operation, hence cost of the system increases.
• Cache Coherence problems.