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STM32’s DMA
Md Rayhan Tanvir
What is DMA
 DMA(Direct Memory Access)
 Direct Memory Transfer
 The peripheral data is fed directly into the
internal memory without the CPU or the internal
memory is sent directly to the external device
without the CPU.
M CPU I/O
Continue…
 Set up a channel between the peripherals and
the memory, allowing the peripherals and
memory to read and write directly to the data at
the primary processor, freeing the main
processor. The entire data transfer operation is
performed under a control called a DMA
controller.
Practical Applications
DMA Architecture (Example)
Continue…
 MCU is the company, the boss is the main
processor, employees are peripherals, the
warehouse is memory.
DMA Architecture
In the process of DMA data transfer, the use of DMA
controller is to manage and control the entire
process of data transfer and the start-up initialization
of DMA controller is controlled by CPU completely.
Continue
M CPU I/O
Block Diagram of STM32
General Purpose DMA
DMA
Controller
1
Arbiter
 Low-density: The
STM32F103x4 and
STM32F103x6 are
Low-density
devices.
 Medium-density:
The STM32F103x8
and STM32F103xB
are Medium-
density devices.
High-density: The
STM32F103xC,
STM32F103xD and
STM32F103xE are
High-density
devices.
10
Bus Arbitration
 Processor and DMA controllers both need to initiate data
transfers on the bus and access main memory.
 The device that is allowed to initiate transfers on the
bus at any given time is called the bus master.
 When the current bus master relinquishes/resign its
status as the bus master, another device can acquire
this status.
 The process by which the next device
to become the bus master is selected
and bus mastership is transferred to
it is called bus arbitration.
DMA
Controller
2
DMA Three stages Transmission
Process
DMA_CPARx or DMA_CMARx
DMA_CNDTRx
Stage 1
Stage 2 Stage 3
Data Buffer (Memory)
DMA Transmission mode
(1) DMA_Mode_Normal
- Normal mode, the DMA channel is automatically
closed when the DMA data is finished and further
DMA requests will not be satisfied.
(2) DMA_Mode_Circular
- Loop mode, which handles an circular buffer
and the configuration of the data transfer at the
end of each round is automatically updated to
the initial state and the DMA transmission is
continuous.
Note
You cannot use circular cache mode when the
specific DMA channel data is configured to
memory to memory.
DMA_Mode_Single
DMA_Mode_Circular
1 STM32's DMA.ppt

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1 STM32's DMA.ppt

  • 2. What is DMA  DMA(Direct Memory Access)  Direct Memory Transfer  The peripheral data is fed directly into the internal memory without the CPU or the internal memory is sent directly to the external device without the CPU. M CPU I/O
  • 3. Continue…  Set up a channel between the peripherals and the memory, allowing the peripherals and memory to read and write directly to the data at the primary processor, freeing the main processor. The entire data transfer operation is performed under a control called a DMA controller.
  • 6. Continue…  MCU is the company, the boss is the main processor, employees are peripherals, the warehouse is memory.
  • 7. DMA Architecture In the process of DMA data transfer, the use of DMA controller is to manage and control the entire process of data transfer and the start-up initialization of DMA controller is controlled by CPU completely.
  • 9. Block Diagram of STM32 General Purpose DMA DMA Controller 1 Arbiter  Low-density: The STM32F103x4 and STM32F103x6 are Low-density devices.  Medium-density: The STM32F103x8 and STM32F103xB are Medium- density devices. High-density: The STM32F103xC, STM32F103xD and STM32F103xE are High-density devices.
  • 10. 10 Bus Arbitration  Processor and DMA controllers both need to initiate data transfers on the bus and access main memory.  The device that is allowed to initiate transfers on the bus at any given time is called the bus master.  When the current bus master relinquishes/resign its status as the bus master, another device can acquire this status.  The process by which the next device to become the bus master is selected and bus mastership is transferred to it is called bus arbitration.
  • 12. DMA Three stages Transmission Process DMA_CPARx or DMA_CMARx DMA_CNDTRx Stage 1 Stage 2 Stage 3
  • 14. DMA Transmission mode (1) DMA_Mode_Normal - Normal mode, the DMA channel is automatically closed when the DMA data is finished and further DMA requests will not be satisfied. (2) DMA_Mode_Circular - Loop mode, which handles an circular buffer and the configuration of the data transfer at the end of each round is automatically updated to the initial state and the DMA transmission is continuous. Note You cannot use circular cache mode when the specific DMA channel data is configured to memory to memory.