Implementation of Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Implementation of Soft-core Processor on FPGADeepak Kumar
We can add a soft-core processor to a FPGA-based system after it's already designed. However, adding a hard-core processor requires either a different FPGA, or an additional chip on the board.
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Implementation of Soft-core Processor on FPGADeepak Kumar
We can add a soft-core processor to a FPGA-based system after it's already designed. However, adding a hard-core processor requires either a different FPGA, or an additional chip on the board.
Verilog code for design a specific processor to down sample a given image via a math-lab by using SPARTAN-6 FPGA. Math-lab code, results also included.
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Introduction to the Module - Fundamentals of Psychology Lecture 1Simon Bignell
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J Gregory Steffan
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A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC...IDES Editor
Modern embedded systems are built around the soft
core processors implemented on FPGA. The FPGAs being
capable of implementing custom hardware blocks giving the
advantage of ASICs, and allowing the implementation of
processor platform are resulting in powerful Configurablesystem
on chip(C-SoC)platforms. The Microchip’s PIC
microcontroller is very widely used microcontroller
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Edition (MXE) will be used simulation and functional
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Presentation made by Jose Pinilla and Alfredo Gualdrón to show the CSTAR (Canadian Surgical Technologies and Advanced Robotics) how FPGAs are being used in the Universidad Pontificia Bolivariana in Bucaramanga, Colombia.
Reconfigurable Platform for the Emulation of RISC and CISC Architectures
Published on the 2012 4th CWCAS (Colombian Workshop on Circuits and Sytems)
IEEE Catalog Number CFP12CWC-CDR
ISBN: 978-1-4673-4613-9
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Implementation of Soft-core processor on FPGA (Final Presentation)
1. Implementation of Multiple Soft-core
processor on FPGA
SARTHAK GANDHI 100090111004
NIKHIL SHAH 100090111008
DEEPAK KUMAR 100090111016
NIRMIT PATEL 100090111018
PROJECT GUIDE :
PROF. RAHUL MEHTA
Group 19
C.K.PITHAWALA COLLEGE OF ENGINEERING AND
TECHNOLOGY, SURAT
3. Definition and Motivation
Definition
Implementation of Multiple Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
Motivation
This is a Faculty Defined Project and was inspired by our guide Prof. Rahul Mehta. The idea of doing
something unique and different from others attracted us towards this topic. Backing from the department
and college made this project possible for us.
4. Literature Review
VHDL
Types of processors
Discrete, Soft-core and Hard-core Processor
Why Soft-core Processor ?
PicoBlaze
PicoBlaze Architecture
PicoBlaze Interface
PicoBlaze Instruction set
Multi-core Processors
5. VHDL
A Hardware Description Language that can be used to model a digital system.[1]
Three basic different description styles:
Structural
Dataflow
behavioural and
Combination of all is possible.
The language has constructs that enable you to express the concurrent or sequential
behaviour of a digital system with or without timing.
Easy & Simple
6. VHDL view of a digital device
Digital
System
External View
Internal Views
Model
a) Device versus device model
Device
Entity 1
Entity 2
Entity N
Device Model
1
Device Model
1
Device Model
1
Actual Hardware VHDL View
b) VHDL view of a device
Device Device Model
7. Types of Processors
Discrete Processor
A discrete microprocessor is implemented as an ASIC with a specific peripheral set along with the
processor core.
Hard-core Processor
Hard core processor is a dedicated part of the integrated circuit in FPGA.
Soft-core Processor
Soft core processor is implemented entirely in the logic primitives of an FPGA.
8. Why Soft-core Processor ?
Soft-Core
• Saves Area
• Customized Easily
• Can be Reconfigured
at run time
• Flexibility
Hard-Core
• Fixed Area
• Unable to adjust
the core
• Cannot be
configured.
• Core cannot be
added later
9. PicoBlaze Microcontroller
Xilinx has developed two main Soft-cores:
MicroBlaze And PicoBlaze
The PicoBlaze is a compact, capable, and cost-effective fully embedded 8-bit RISC
microcontroller core optimized for the Xilinx FPGA families.[2]
The MicroBlaze is entirely implemented in general-purpose memory & logic fabrics of FPGA.
Features of PicoBlaze:
16 byte-wide general-purpose data registers
1K instructions of programmable on-chip program store
Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags
256 input and 256 output ports & up to 240MHz performance
11. PicoBlaze Interface
The PicoBlaze design was originally named
KCPSM which stands for "Constant(K)
Coded Programmable State Machine“.
PicoBlaze consists of two parts:
1) The processor core (KCPSM3) and
2) The program memory from which
instructions are fetched and executed by the
processor core.
There are two VHDL files that are used to
construct the complete PicoBlaze with
program.
In_Port
Reset
interrupt
Instruction
Out_port
Port_id
Read_strobe
Write_strobe
Interrupt_ack
address
KCPSM3
addr
instruction
Instruction
ROM
clk
Interface to
logic
clk
13. Multi-core Processors
More than one PicoBlaze core can be implemented on FPGA and communication between
them can be made using any effective handshake technique.
The major Handshake Techniques are as follows:
Direct handshake
Handshake Based on Reconfigurable Mesh[8]
Master-Slave technique[7]
Wrap technique
15. Direct Handshake
First Processor interrupts second Processor to send data.
If the second processor gives acknowledgment of interrupt indicating it is free to accept the
data from first processor.
Then Processor 1 sends data to Processor 2.
Similarly, the process occurs from Processor 2 to Processor 1.
16. RMESH
Configurable switch is required to design.
Configurable switch are communicating with more
than one PicoBlaze and will reply to the condition
given.
Here the structure of switching matrix is designed such
a way at a time two PicoBlazes can communicate with
each other.
18. Master Slave Technique
One device or process(Master) has unidirectional control over one or more other devices or
process(Slave).
The direction of control is always from the master to the slave.
Master PicoBlaze receives all commands and Slave PicoBlazes follows the commands.
Requires good amount of work distribution.
20. Wrap Technique
Traditional reconfigurable mesh implementations use large-scale meshes of simple 1-bit
processing elements.
Switch elements are scalable in their bit-width, different processors can be easily employed.
Provide appropriate wrappers that encapsulate the processors and provide the interface to the
network.
21. Wrap Technique
a) A network node consisting of a processing element (PE), a switch
element (SE), and corresponding wrappers.
24. Xilinx Project Navigator
Project Navigator organizes your design files and runs processes.
It allows us to do the following:
Add and create design source files, which appear in the Sources window.
Modify your source files in the Workspace.
Run processes on your source files in the Processes window.
View output from the processes in the Transcript window.
25. Xilinx ISE Simulator (ISim)
ISim provides a complete, full-featured HDL simulator integrated within ISE.
Features:
Xilinx simulation libraries “built-in”
Supports VHDL-93 and Verilog 2001
Standalone Waveform viewing capabilities
Debug capabilities
Easy to use - One-click compilation and simulation
Single click re-compile and re-launch of simulation
26. FPGA
Field-programmable gate array (FPGA)
An integrated circuit designed to be configured by a designer after manufacturing - hence "field-
programmable".
The FPGA configuration is generally specified using a hardware description language (HDL).
Overview of the Xilinx Spartan-3E devices:
The most basic element is a logic cell (LC), which contains a four-input LUT and a D Flip-Flop.
Two logic cells group to form a slice
Four slices group to form a configurable logic block (CLB).
28. Work Plan
Phase 1
Basic Study of VHDL.[1]
Literature Study of Soft-core processor.
Implementation of basic program in Xilinx & to observe their Waveform.
Basic study of KCPSM3 assembler.
Implementation of Soft-core in Xilinx.
To study different handshaking techniques between two processor.
Load basic program of PicoBlaze on Spartan-3e Board.
29. Work Plan
Phase 2
Selecting the most efficient technique of handshaking.
Implementation of handshaking method.
Load the entire program on FPGA.
Debugging the program and generating synthesis report
Creating an application using the multi-core processor.
30. Work done in Phase I
Thorough study of digital device modelling using VHDL.
Thorough study of PicoBlaze (KCPSM3) architecture, features, instructions and requirements.
Learnt to use KCPSM3 assembler.
Learnt to use Xilinx Project Navigator and ISE Simulator(ISim).
Successfully interfaced 1K ROM with KCPSM3.
Successfully designed a simple program to glow LEDs using ONE PicoBlaze.
Learnt how to download a program onto FPGA.
Successfully loaded the program on FPGA for testing.
Designed another program to glow LEDs using TWO PicoBlazes.
Learnt the design summary to get information about the utilization of FPGA slices.
Finding an appropriate method of handshaking between multiple processors to be implemented.
31. Study of KCPSM3 Assembler
Very simple 8-bit microcontroller.
Totally embedded into the device and requires no external support.
Features of KCPSM3:
16 general purpose registers of 8 bits
Arithmetic Logic Unit(ALU) provides many simple operations expected in an 8-bit processing unit
256 input ports and 256 output ports
64-byte scratchpad memory
32. Study of PicoBlaze
Referred to as soft core processor.
Synthesized from an HDL.
Uses the programmable logic and routing resources of an FPGA for their implementation.
It consists of two parts:
The processor core (KCPSM3)
The program memory from which instructions are fetched and executed by the processor core
35. Steps to setup PicoBlaze on FPGA
Download the PicoBlaze IDE . Extract PicoBlaze and the PicoBlaze IDE which will provide KCPSM3 assembler .
Write assembly program. Save it with extension <filename>.psm.
Assemble the program, this will generate a VHDL file in which block RAM and its initial contents are define using
KCPSM3.exe assembler.
The assembler will generate vhdl, verilog, hex files etc.. Add the new VHDL file to the project in Xilinx.
PicoBlaze should be used as a component. The KCPSM3.vhd also had to be added in Xilinx project.
Same way the ROM file named<filename>.vhd which is generated by KCPSM3 assembler is to be added in Xilinx
Project.
Link or map the new VHDL module created by the assembler to your source file as a ROM and KCPSM3.
As done in assembler write corresponding VHDL code in source file that should map all inputs and outputs.
Write an implementation constraint file to map input and outputs of FPGA IO with Program IO.
Once mapping is done then Simulate, Synthesis and generate bit file to load file on Spartan 3E.Build and download the
VHDL to the FPGA.
36. Work done in Phase II
Selected Direct Handshaking method to communicate between processors.
Developed the method which includes exchange of Interrupt and Interrupt Acknowledge
signals.
Implemented one-way handshaking method.
Implemented two-way handshaking between 2 PicoBlazes.
Loaded the full program on FPGA with the switch-LED example to demonstrate the working of
multiple PicoBlazes.
Created an application using this processor.
Stepper motor controller
38. Algorithm
1
• Processor1 generates and sends an Interrupt signal to Processor2.
2
• Processor2 waits till all its processes end and becomes free.
• Once Free, Processor2 acknowledges Processor1 by sending
Intr_ack signal.
3
• On reception of Intr_ack signal, Processor1 sends the data to
Processor2.
39. -- Your Program Here--
ADDRESS 3FF
JUMP isr
Example of Interrupt Flow in PicoBlaze
main: -- Your Program Here--
ENABLE INTERRUPT
INPUT s0, 00
INPUT s1, 01
-- Your Program Here--
OUTPUT s0, 00
-- Your Program Here--
CALL critical timing
-- Your Program Here--
JUMP main
critical timing: DISABLE INTERRUPT
-- Your Program Here--
ENABLE INTERRUPT
RETURN
isr: TEST s7, 02
-- Your Program Here--
RETURNI ENABLE
ADDRESS 000
1
2
3
4
5
6
• The interrupt input is not recognized until the
INTERRUPT_ENABLE flag is set.
• INTERRUPT Input asserted at (2).
• In timing-critical functions or areas where absolute predictability is
required, temporarily disable the interrupt.
• Re-enable the interrupt input when the time-critical function is
complete.
• The interrupt vector is always located at the most-significant
memory location, where all the address bits are ones.
• Jump to the interrupt service routine.
• The interrupt input is automatically disabled.
• Use the RETURNI instruction to return from an interrupt.
44. Result
Synthesis report generated shows that only 10% of Spartan-3E slices are used while
implementing TWO PicoBlazes, this shows that we can load simultaneous10 PicoBlazes on a
single FPGA.
Fig (i) i.e. the Output Waveform shows how data is transfer from one PicoBlaze to another
with use of interrupt.
Fig (ii) shows the time-delay between the interrupt send by 1st PicoBlaze and the interrupt
acknowledge received by it is 2500ns.
A single PicoBlaze can interrupt 64 PicoBlazes(ONE at a time).
53. References
1. J. Bhasker “ A VHDL-Primer ”, Third Edition.
2. PicoBlaze 8-bit Embedded Microcontroller User Guide
http://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf
3. Mehta Rahul V. “Implementation of PicoBlaze on Xilinx's Spartan 3E FPGA”, International Journal
of Computer and Electronics engineering Volume 4 Number 2(July-Dec 2012).
4. Volnei A. Pedroni “Circuit Design with VHDL”, Massachusetts Institute of Technology, 2004.
5. Download PicoBlaze reference designs and additional files.
http://www.xilinx.com/ipcenter/processor_central/picoblaze
6. http://www.eng.auburn.edu/~strouce/class/elec4200/ KCPSM3_Manual.pdf
7. Rahul V. Mehta, Pinal J. Engineer, Milind S. Shah, “Multiple PicoBlazes – Review And
Implementation”.
8. Heiner Giefers and Marco Platzner “A Many-core Implementation Based On The
Reconfigurable Mesh Model ”, University of Paderborn.
55. Built Applications
OpenRISC was first fabricated into a commercial standalone ASIC by Flextronics in 2003.
More recently it has been used by Samsung in their set top box processors, starting with the SDP -83 ‘B’
series through to the SDP-1003 and SDP-1006 ‘E’ series.
A fault-tolerant version of OpenRISC was developed by the Swedish space and defense company ÅAC
Microtec, and flew in NASA’s TechEdSat last year.
One of its BA family of processors, derivative from the original OpenRISC, was used by NXP in its JN5148
ultra-low power Zigbee transceiver chip.
LEON has been used for many space based projects by both the European Space Agency and NASA.
Complete Verilog implementation of a 2D/ 3D graphics processor capable of OpenGL and D3D with full
test suite.
56. PicoBlaze Merits/Demerits
Merits Demerits
• Easy to program, excellent for control and
state machine applications
• Resource requirements remain constant
with increasing complexity
• Re-uses logic resources, excellent for
lower-performance functions
• Executes sequentially
• Performance degrades with increasing
complexity
• Program memory requirements increase
with increasing complexity
• Slower response to simultaneous inputs