The document outlines the implementation of a soft-core processor on FPGA, highlighting the advantages of soft-core over hard-core processors, such as flexibility and the ability to modify designs post-implementation. It details the phases of the project, including VHDL programming, handshaking methods for multi-core implementation, and utilizes the Picoblaze microcontroller as a case study. The document also provides references for further reading and resources related to the Picoblaze microcontroller and its application on FPGA.

1. Implementation of
Soft-core Processor
on FPGA
GROUP 8:
NIKHIL SHAH
NIRMIT PATEL
SARTHAK GANDHI
DEEPAKKUMAR PRAJAPATI
Project Guide:
Rahul V Mehta

2. Abstract
• Hard-core processor are fixed and cannot be changed while soft-core processors Can be easily
modified and tuned to specific requirements, more features, custom instructions, etc.
• In soft-core processor Multiple cores can be used.
• We can add a soft-core processor to a FPGA-based system after it's already designed. However,
adding a hard-core processor requires either a different FPGA, or an additional chip on the board.
• All the major FPGA vendors have soft-core processors in their product offerings and there are
also a number of companies and organizations developing soft-core processors and can be
implemented in any FPGA design.
• Thus, due to following advantages of Soft-core processor over other types of processors we
have decided to work on Soft-core processor.
Implementation of Soft-Core Processor on FPGA

3. Phase I (Language Survey)
• Study of Basic VHDL Programming Language.
• Learn the basics of Xilinx and implement simple programs to
understand the working of each stage.
• Study of Soft-core Processor – PicoBlaze.
• The KCPSM3 Assembler.
• Study the methods of Handshaking to implement multi-core processor
and decide one of them.
Implementation of Soft-Core Processor on FPGA

4. Phase II
• Implement the selected method of Handshaking on FPGA Board
Spartan 3E.
• Make an application of the soft-core processor. For eg. Graphical LCD,
Stepper Motor or Sensor Interfacing.
Implementation of Soft-Core Processor on FPGA

5. Why VHDL?
• Is an IEEE and ANSI standard .
• Three basic different description styles: structural, dataflow, and
behavioral.
• The language supports hierarchy.
• Wide range of abstraction levels.
• Easier large scale design modeling.
• Test benches can be written.
• Precise simulation semantics are defined.
• Capability of defining new data types.
Implementation of Soft-Core Processor on FPGA

6. PicoBlaze
• The most popular and widely-used cores (of Xilinx Incorporated) are
the MicroBlaze and PicoBlaze soft-core processors.
• The PicoBlaze microcontroller is a compact, capable, and cost-
effective fully embedded 8-bit RISC microcontroller core optimized
for the Xilinx FPGA families.
• The KCPSM3 version used in this project occupies just 96 FPGA slices
in a Spartan-3 Generation FPGA (which is only 12.5% of an XC3S50
device).
• The PicoBlaze microcontroller performs a respectable 44 to 100
million instructions per second (MIPS) depending on the target FPGA
family and speed grade.
Implementation of Soft-Core Processor on FPGA

7. PicoBlaze
Key Features
• Supports Virtex-7, Kintex-7, Spartan-3E and older Xilinx FPGA families
• 16 byte-wide general-purpose data registers
• 1K instructions of programmable on-chip program store
• Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator
flags
• 256 input and 256 output ports & up to 240MHz performance
• Highly integrated for implementing non-time critical state machine
• Predictable fast interrupt response
Implementation of Soft-Core Processor on FPGA

8. Interface Of PicoBlaze
KCPSM = Constant(K) Coded Programmable State Machine
• PicoBlaze consists of two parts: 1) the processor core and 2) the
program memory from which instructions are fetched and executed
by the processor core.
Implementation of Soft-Core Processor on FPGA

9. KCPSM3 Assembler Files
Implementation of Soft-Core Processor on FPGA

10. PicoBlaze Instructions
Implementation of Soft-Core Processor on FPGA

11. Multi-core PicoBlaze
• More than one PicoBlaze core can be implemented on FPGA and
communication between them can be made using any effective
handshake technique.
• The major Handshake Techniques are as follows:
Direct handshake
Handshake Based on Reconfigurable Mesh
Master-Slave technique
Wrap technique
Implementation of Soft-Core Processor on FPGA

12. References
• Download PicoBlaze reference designs and additional files.
http://www.xilinx.com/ipcenter/processor_central/picoblaze
• Xilinx System Generator User Guide: “Designing PicoBlaze Microcontroller Applications”
http://www.xilinx.com/support/sw_manuals/sysgen_ug.pdf
•Mehta Rahul V. “Implementation of PicoBlaze on Xilinx's Spartan 3E FPGA”, International
Journal of Computer and Electronics engineering Volume 4 Number 2(July-Dec 2012).
•J. Bhaskar “A VHDL Primer”.
•Volnei A. Pedroni “Circuit Design with VHDL”, Massachusetts Institute of Technology, 2004.
•Heiner Giefers and Marco Platzner “A Many-core Implementation Based On The
Reconfigurable Mesh Model ”, University of Paderborn.
Thanks for your attention.

13. Queries OR Suggestions