Microblaze

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Microblaze

  1. 1. Prepared By: Krunal Siddhapathak(10BEC097)
  2. 2. 1. Introduction 2. MicroBlaze Core Block Diagram 3. MicroBlaze Architecture 4. Features 5. Advantages 6. Architecture limitations of MicroBlaze 7. Conclusion
  3. 3. » The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. » embedded processor soft core is a reduced instruction set computer (RISC) . » A soft microprocessor (also called soft core microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis.
  4. 4. » Supports two Bus Standards. 1) PLB V46 (PROCESSOR LOCAL BUS) 2) XILINX LOCAL MEMORY BUS » LMB designed to interface local PLBs block designed in FPGA. » PLB V46 designed for High speed and High Bandwidth peripherals. » PLB V46 supports 128bits of data and 36 bits of address.
  5. 5. » MicroBlaze By default do not supports any Cache blocks. » When it gets activated by EDK(Embedded development Kit) cache block also gets activated through BLOCK RAM. » There are mainly Two Types of RAMS 1) BLOCK RAM 2) Distributed RAM » Supports FAST Simplex Link (FSL). » FSL is used for Custom Function like large multiplication etc.
  6. 6. » Supports Tightly coupled OFF chip FLSH/SRAM Memory. » Used to provide low latency memory access that is known as Cache link with interfering PLB V46 » Some embedded system like Power PC contains 1) PLB V46 master bus 2)PLB V46 slave bus. » Less time intensive task can be off loaded to slave bus that is also connected to MicroBlaze core.
  7. 7. » highly configurable processor, allowing you to select a specific set of features required by your design. » The fixed feature set of the processor includes: ˃ Thirty-two 32-bit general purpose registers ˃ 32-bit instruction word with three operands and two addressing modes ˃ 32-bit address bus ˃ Single issue pipeline In addition to these fixed features, the MicroBlaze processor is parameterized to allow selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze support a subset of the optional features. Only the latest (preferred) version of MicroBlaze (v7.1) supports all options.
  8. 8. » In terms of its instruction-set architecture, MicroBlaze is very similar to the RISC-based DLX architecture. » The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. » A newer version of the MicroBlaze, supported in both Spartan- 6 and Virtex-6 implementations, as well as the 7- Series, supports the AXI specification. » The majority of vendor-supplied and third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) » For access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses. » User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). » The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
  9. 9. » Easy to use with EDK ˃Linux/GCC support (with limitations) » High “performance” soft core processor ˃Most of instructions can be completed with 1 cycles ˃Shorter pipeline, higher working frequency (>100 MHz on Virtex-II ) + LEON3 7-stage pipeline, 5000 LUTs @ 90MHz on Virtex-II ˃FPGA optimized implementation + Fast carry chain MUX, hardware multiplier + RLOC placement constraints
  10. 10. » MicroBlaze Core Features and Options ˃Low Latency Interrupt Mode ˃Fault Tolerance, including Error Correction Codes (ECC) and Lockstep support ˃LMB BRAM memory ˃Parity protection on internal BRAMs and caches ˃Floating Point Unit (FPU) ˃IEEE 754 compatible ˃Single precision ˃Memory Management Unit (MMU) ˃Full MMU with Virtual Memory supported by Linux ˃MPU mode for region protection for secure RTOS applications ˃Instruction and Data Caches ˃Cache size configurable: 2kB - 64kB (Block RAM based)
  11. 11. » New version 8 features expand MicroBlaze capabilities even further ˃Relocatable base vector addresses for maximum memory sharing flexibility when using MicroBlaze in Zynq-7000 AP SoC devices ˃New Sleep instruction enhances MicroBlaze low-power performance ˃IO Module enhancements add GPI interrupts, and programmable UART baud rate. Can be used with either MicroBlaze_MCS or full MicroBlaze ˃LMB BRAM interface controller now supports multiple LMB busses ˃New low latency interrupts where the controller directly supplies the interrupt vector for each individual interrupt, lowering latency response by as much as 10X depending on system design. ˃Embedded designers can now add a new AXI System Cache soft- peripheral to any memory controller-based design. MicroBlaze then uses this peripheral as Level 2 cache increasing system performance even further. ˃New byteswap instructions to further increase Ethernet performance when using AXI. »
  12. 12. » Simplify your life - MicroBlaze Configuration Wizard ˃ Extreme configurability is at the heart of Micro Blaze’s flexibility, but you don’t have to memorize a manual to learn how to configure MicroBlaze. ˃ Through the MicroBlaze Configuration Wizard included in Xilinx Platform Studio – a few mouse clicks lets you quickly select between six common microprocessor use models. ˃ The configuration wizard delivers instant feedback through a meter display on resource utilization and performance, and runs in wizard mode for fast setup, or advanced mode for access to the lowest level details. » Smaller, but still powerful - MicroBlaze Microcontroller System ˃ Xilinx also offers the power of MicroBlaze in an even smaller package - MicroBlaze Micro Controller System . ˃ MicroBlaze MCS consists of MicroBlaze in a fixed 3-stage pipeline configuration for the smallest footprint surrounded by a system of common embedded design peripherals. ˃ it can run from IDS Logic Edition without the need for a full embedded design license.
  13. 13. » No MMU support ˃no protection among processes ˃Can’t run full version Linux. » No double precision floating point ˃no full floating point libraries support in libC » No atomic instructions ˃hard to implement lock ˃non-blocking FIFO instruction problem. » No cache coherent support
  14. 14. » Xilinx's EDK (Embedded Development Kit) is the development package for building MicroBlaze (and PowerPC) embedded processor systems in Xilinx FPGAs. » Designers use XPS (Xilinx Platform Studio) to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) » The XPS converts the designer's platform specification into a synthesizable RTL description (Verilog or VHDL), and writes a set of scripts to automate the implementation of the embedded system (from RTL to the bitstream-file.) » For the MicroBlaze core, the EDK normally generates an encrypted (non human-readable) netlist, but the processor description (written in VHDL) can be purchased from Xilinx.
  15. 15. » MicroBlaze™ is the industry-leader in FPGA- based soft processors, with advanced architecture options like AXI or PLB interface, Memory Management Unit (MMU), instruction and data-side cache, configurable pipeline depth, Floating- Point unit (FPU), and much more.
  16. 16. » http://www.xilinx.com/support/documentation/sw_m anuals/mb_ref_guide.pdf » http://www.wiki.xilinx.com/MicroBlaze » http://www.smdp2vlsi.gov.in/smdp2vlsi/downloads/ mb_tutorial.pdf

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