This document provides an overview of application specific integrated circuits (ASICs). It discusses the main types of ASICs including full custom, semi-custom (standard cell-based and gate array-based), and programmable. For semi-custom, it describes standard cell-based ASICs using predesigned logic cells and different types of gate arrays including channeled, channelless, and structured. The document also covers the design flow, economics, merits like improved speed and power consumption, and demirts such as high costs for redesigns.

1. APPLICATION SPECIFIC INTEGRATED
CIRCUIT
By: AVNISH KUMAR(1EP10EE006)
Under the guidance of- Prof. BHARATH V S

2. CONTENTS
 INTRODUCTION
 TYPES OF ASIC
 FULL CUSTOM
 SEMI-CUSTOM
 PROGRAMMABLE
 DESIGN FLOW
 MERITS
 DEMIRITS
 REFERENCES

3. INTRODUCTION
 It is non-standard integrated circuit.
 Designed for a specific use or application.
 A Structured ASIC falls between an FPGA and a
Standard Cell-based ASIC.
 Structured ASIC’s are used mainly for mid-
volume level designs.
 It contains very large part of the electronic
needed on a single integrated circuit.

4. TYPES OF ASICs

5. FULL CUSTOM
 A Full custom ASIC is one which includes some (possibly
all) logic cells that are customized and all mask layers
that are customized.
 A microprocessor is an example of a full-custom IC
 Full-custom ICs are the most expensive to manufacture
and to design.
 The manufacturing lead time (the time required just to
make an IC not including design time) is typically eight
weeks for a full-custom IC.

6. SEMI-CUSTOM
 ASICs , for which all of the logic cells are predesigned and
some (possibly all) of the mask layers are customized are
called semi custom ASICs.
 Using the predesigned cells from a cell library makes the
design , much easier.
 There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii) (ii)Gate-array–based ASICs.

7. STANDARD CELL BASED
 One can apply the term CBIC to any IC that uses cells, but it
is generally accepted that a cell-based ASIC or CBIC means
a standard-cell based ASIC.
 A cell-based ASIC (cell-based IC, or CBIC pronounced sea-
bick) uses predesigned logic cells (AND gates, OR gates,
multiplexers, and flip-flops, for example) known as standard
cells.
 A cell-based ASIC (CBIC) die with a single standard-cell area
(a flexible block) together with four fixed blocks.
 The advantage of CBICs is that designers save time, money,
and reduce risk by using a predesigned, pretested, and pre
characterized standard-cell library.

8. GATE ARRAY BASED
 In a gate array (sometimes abbreviated GA) or gate-array
based ASIC the transistors are predefined on the silicon
wafer.
 The designer chooses from a gate-array library of
predesigned and pre-characterized logic cells
 There are three types of Gate Array based ASICs.
Channeled gate arrays.
Channel less gate arrays.
Structured gate arrays.

9. CHANNELED GATE ARRAY
 The channeled gate array was the first to be developed . In
a channeled gate array space is left between the rows of
transistors for wiring.
 A channeled gate array is similar to a CBIC. Both use the
rows of cells separated by channels used for interconnect.
 Only the interconnect is customized. The interconnect uses
predefined spaces between rows of base cells.
Manufacturing lead time is between two days and two
weeks.

10. CHANNELLESS GATE ARRAY
 This channel less gate-array architecture is now more widely
used . The routing on a channel less gate array uses rows of
unused transistors.
 The interconnect uses predefined spaces between rows of
base cells.
 Only the interconnect is customized.
 When we use an area of transistors for routing in a channel
less array, we do not make any contacts to the devices lying
underneath , we simply leave the transistors unused.

11. STRUCTURED GATE ARRAY
 This design combines some of the features of CBICs and
MGAs. It is also known as an embedded gate array or
structured gate array(also called as master slice or master
image).
 One of the limitations of the MGA is the fixed gate-array
base cell. This makes the implementation of memory,
difficult and inefficient.
 Custom blocks (the same for each design) can be embedded.
 An embedded gate array gives the improved area efficiency
and increased performance of a CBIC but with the lower
cost and faster turn around of an MGA.

12. PROGRAMMABLE
 Programmable logic devices ( PLDs ) are standard ICs that
are available in standard configurations.
 PLDs use different technologies to allow programming of the
device.
 No customized mask layers or logic cells
 A single large block of programmable interconnect
 Fast design turnaround
 A matrix of logic macro cells that usually consist of
programmable array logic followed by a flip-flop or latch

13. COMPASRISON
CPLD FPGA
 Architecture: PAL-like Gate Array-like
 Density: Low to Medium
12 22V10s or more
Medium to High
Up to 1 million
gates
 Speed: Fast, Predictable Application
dependent
 Interconnect: Crossbar Routing
 Power
Consumption:
High Medium

14. DESIGN FLOW

15. ECONOMICS OF ASICs

16. MERITS
 ASIC has a miniaturized embodiment size.
 ASIC can improve speed.
 ASIC needs less electric power to operate.
 Big reduction in power consumption.
 Better control of electrical parameter.
 Big saving in space.
 Better control of electrical parameters.

17. DEMERITS
 The cost per a unit can be high when producing a small
number of units because of cost in producing a photo mask.
 They can be hard to design and it is expensive and waste of
time if they need to be redesigned.
 The time of manufacturing process can be long.
 Testing and debugging are very difficult on an ASIC.

18. REFERENCES
 Application-Specific Integrated Circuits- Michael John
Sebastian Smith , Addison Wesley Longman, Inc.
 T. Okamoto, T. Kimoto, N. Maeda, “Design Methodology and
Tools for NEC Electronics - Structured ASIC ISSP", [p. 90]
Proceeding of the 2004 international symposium on Physical
design.
 B. Zahiri, “Structured ASICs: Opportunities and Challenges,”
Proceedings of the 21st International Conference on
Computer Design (ICCD’03).
 K. Wu, Y. Tsai, “Structured ASIC, Evolution or Revolution?,”
Faraday Technology Corporation, Proceedings of the 2004
International Symposium on Physical Design.

19. THANK YOU…