This document summarizes a presentation given at the London Open Source Meetup for RISC-V on April 19, 2021. The presentation introduced the RISC-V Online Tutor, an online course for learning RISC-V fundamentals from digital logic to C programming. It provided an overview of the course structure and lessons, which take students through RISC-V assembly, processor design, and application development. It also demonstrated the online learning platform and its ability to interact with remote FPGA hardware during lessons. The goal is to invite community participation and collaboration to further develop the Online Tutor.
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there's no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex-A53KarthiSugumar
This presentation focuses on the architectural exploration of RISC-V ISA based processor for networking applications such as a Router, using the trade-off between power consumption and performance. The optimized architecture is compared against commercially available RISC processors from ARM. A model of RISC-V based Solid-State Drive is also proposed.
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there's no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex-A53KarthiSugumar
This presentation focuses on the architectural exploration of RISC-V ISA based processor for networking applications such as a Router, using the trade-off between power consumption and performance. The optimized architecture is compared against commercially available RISC processors from ARM. A model of RISC-V based Solid-State Drive is also proposed.
In this deck from the 2016 Stanford HPC Conference, Kurt Keville from R&D Labs at MIT presents: Introduction to RISC-V.
"Today’s server systems provide many knobs which influence energy efficiency and performance. Some of these knobs control the behavior of the operating systems, whereas others control the behavior of the hardware itself. Choosing the optimal configuration of the knobs is critical for energy efficiency. In this talk recent research results will be presented, including examples of big data applications that consume less energy when dynamic tuning is employed."
Kurt works on optimizing HPC codes for educational and institutional (R&D labs) purposes at MIT. He assesses new supercomputing hardware as part of his responsibilities. He has published in IEEE conferences and journals and he teaches embedded programming once a year. Kurt has a BS from West Point and an MS from MIT.
Learn more: http://soc.mit.edu
Sign up for our insideHPC Newsletter: http://insideHPC.com/newsletter
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
SFO15-TR9: PSCI, ACPI (and UEFI to boot)
Speaker: Bill Fletcher
Date: September 24, 2015
★ Session Description ★
An introductory session of a system-level overview at Power State Coordination
- Focus on ARMv8
- Goes top-down from ACPI
- A demo based on the current code in qemu
- The specifications are very dynamic - what’s onging for ACPI and PSCI
★ Resources ★
Video: https://www.youtube.com/watch?v=vXzPdpaZVto
Presentation: http://www.slideshare.net/linaroorg/sfo15tr9-psci-acpi-and-uefi-to-boot
Etherpad: pad.linaro.org/p/sfo15-tr9
Pathable: https://sfo15.pathable.com/meetings/303087
★ Event Details ★
Linaro Connect San Francisco 2015 - #SFO15
September 21-25, 2015
Hyatt Regency Hotel
http://www.linaro.org
http://connect.linaro.org
How to create SystemVerilog verification environment?Sameh El-Ashry
Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
This slide provides a basic understanding of hypervisor support in ARM v8 and above processors. And these slides (intent to) give some guidelines to automotive engineers to compare and choose right solution!
Embitude's Linux SPI Drivers Training Slides. Contains the details of AM335X specific low level programming, SPI components such as SPI Master Driver, SPI Client Driver, Device Tree for SPI
Archiver pilot phase kick off Award CeremonyArchiver
In the framework of the ARCHIVER pre-commercial procurement tender, between December 2020 and August 2021 three consortia worked on innovative, prototype solutions for Long-term data preservation, in close collaboration with CERN, EMBL-EBI, DESY and PIC. The selection process for proceeding to the next phase is over and the consortium/a selected to continue with the pilot phase were officially announced at a public ceremony on the 29th of November 2021
Archiver pilot phase kick off Award CeremonyArchiver
In the framework of the ARCHIVER pre-commercial procurement tender, between December 2020 and August 2021 three consortia worked on innovative, prototype solutions for Long-term data preservation, in close collaboration with CERN, EMBL-EBI, DESY and PIC. The selection process for proceeding to the next phase is over and the consortium/a selected to continue with the pilot phase were officially announced at a public ceremony on the 29th of November 2021
In this deck from the 2016 Stanford HPC Conference, Kurt Keville from R&D Labs at MIT presents: Introduction to RISC-V.
"Today’s server systems provide many knobs which influence energy efficiency and performance. Some of these knobs control the behavior of the operating systems, whereas others control the behavior of the hardware itself. Choosing the optimal configuration of the knobs is critical for energy efficiency. In this talk recent research results will be presented, including examples of big data applications that consume less energy when dynamic tuning is employed."
Kurt works on optimizing HPC codes for educational and institutional (R&D labs) purposes at MIT. He assesses new supercomputing hardware as part of his responsibilities. He has published in IEEE conferences and journals and he teaches embedded programming once a year. Kurt has a BS from West Point and an MS from MIT.
Learn more: http://soc.mit.edu
Sign up for our insideHPC Newsletter: http://insideHPC.com/newsletter
What are the different opportunities for a VLSI Front end Verification engineer? What career path exists and how to build a career path in Verification of VLSI chip designs?
Sharing my experiences and Career journey as Verification Engineer
SFO15-TR9: PSCI, ACPI (and UEFI to boot)
Speaker: Bill Fletcher
Date: September 24, 2015
★ Session Description ★
An introductory session of a system-level overview at Power State Coordination
- Focus on ARMv8
- Goes top-down from ACPI
- A demo based on the current code in qemu
- The specifications are very dynamic - what’s onging for ACPI and PSCI
★ Resources ★
Video: https://www.youtube.com/watch?v=vXzPdpaZVto
Presentation: http://www.slideshare.net/linaroorg/sfo15tr9-psci-acpi-and-uefi-to-boot
Etherpad: pad.linaro.org/p/sfo15-tr9
Pathable: https://sfo15.pathable.com/meetings/303087
★ Event Details ★
Linaro Connect San Francisco 2015 - #SFO15
September 21-25, 2015
Hyatt Regency Hotel
http://www.linaro.org
http://connect.linaro.org
How to create SystemVerilog verification environment?Sameh El-Ashry
Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
This slide provides a basic understanding of hypervisor support in ARM v8 and above processors. And these slides (intent to) give some guidelines to automotive engineers to compare and choose right solution!
Embitude's Linux SPI Drivers Training Slides. Contains the details of AM335X specific low level programming, SPI components such as SPI Master Driver, SPI Client Driver, Device Tree for SPI
Archiver pilot phase kick off Award CeremonyArchiver
In the framework of the ARCHIVER pre-commercial procurement tender, between December 2020 and August 2021 three consortia worked on innovative, prototype solutions for Long-term data preservation, in close collaboration with CERN, EMBL-EBI, DESY and PIC. The selection process for proceeding to the next phase is over and the consortium/a selected to continue with the pilot phase were officially announced at a public ceremony on the 29th of November 2021
Archiver pilot phase kick off Award CeremonyArchiver
In the framework of the ARCHIVER pre-commercial procurement tender, between December 2020 and August 2021 three consortia worked on innovative, prototype solutions for Long-term data preservation, in close collaboration with CERN, EMBL-EBI, DESY and PIC. The selection process for proceeding to the next phase is over and the consortium/a selected to continue with the pilot phase were officially announced at a public ceremony on the 29th of November 2021
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
How to run Linux on RISC-V (FOSS North 2020)Drew Fustini
Title:
How to run Linux on RISC-V (with open hardware and open source FPGA tools)
Abstract:
Want to run Linux with RISC-V on Open Source Hardware?
This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge using only open source tools thanks to Project Trellis, yosys and nextpnr. I will explain what migen and LiteX are, and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux on VexRiscv.
In conclusion, I will explore the landscape of open source chip designprojects and the Linux-capable RISC-V silicon chips on horizon for 2020, and talk about my desire to collaborate on an affordable (<$100?) OSHW Linux RISC-V board.
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Slides for my presentation on RISC-V and open source chip design at PumpingStation1 hackerspace tonight https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
Embedded Linux Conference 2020:
Linux on RISC-V with open source hardware and open source FPGA tools
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, the Reform laptop and more.
I will also talk about the importance of the open RISC-V instruction set and free software FPGA toolchains. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a SoC capable of running Linux.
Finally, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Opencast is a free, flexible, open-source video management solution to meet the many needs academic institutions have with respect to video.
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91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
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• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
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Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
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Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
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Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
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1. Insights into SAP testing best practices
2. Heatmap utilization for testing
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4. Demo
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Orchestrator execution result
Defect reporting
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RISC-V Online Tutor
1. London Open Source Meetup for RISC-V 19 April 2021
1
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Online Tutor
Fearghal Morgan1, Arthur Beretta2, Ian Gallivan1, Joseph Clancy1, Frédéric Rousseau2, Roshan George1, László Bakó3, Frank Callaly1
1 National University of Ireland, Galway, Ireland (NUI Galway)
2 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA
3SAPIENTIA - Hungarian University of Transylvania, Targu-Mures/Corunca
Links
1. Register www.vicilogic.com/register
2. Download presentation / access demos
3. Publications
2. London Open Source Meetup for RISC-V 19 April 2021
2
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• Introductory demos
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online Tutor application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
3. London Open Source Meetup for RISC-V 19 April 2021
3
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Lessons interact with remote hardware
Course homepage
4. London Open Source Meetup for RISC-V 19 April 2021
4
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Lesson/Framework Demo
• Register-immediate instruction
Demo 1 Demo 2
• Guided lessons
• Widgets in view on left side
link to remote RISC-V hardware
• * * * highlight active datapaths
• Transparent FPGA allocation,
FPGA configuration,
browser-FPGA interaction
• Browse course (top left)
• (top right)
ALU
Arithmetic
Logic Unit
RB Register Bank x0-x15 x10/x11 LED display
5. London Open Source Meetup for RISC-V 19 April 2021
5
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
About
• Free, open Instruction Set Architecture (ISA) (Berkeley 2010)
• Growing community (RISC-V International, industry, university)
• Enabling new era of processor innovation
• through open standard collaboration
• Freedom in developing extensible software and hardware
• Custom ICs based on RISC-V will enable cost-effective IoT product differentiation
• Building custom chips becoming practical, due to evolution of electronic design
tools, and lower market entry to semiconductor manufacturing industry
• Sustainable choice for building custom chips, thanks to adoption/promotion
by major technology companies, industrial organisations, governments
(Gartner Report, June 20)
6. London Open Source Meetup for RISC-V 19 April 2021
6
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
International
• Bare Metal & Real-time OS on RISC-V
• Compliance & Verification
• Debug & Trace
• Formal Specification
• Physical Memory Protection
• The RISC-V Memory Model
• RISC-V Toolchain & Kernel Development
• RISC-V Academia & Training committee (biweekly meetings, Thurs)
Participation welcome
Training: Call For Participation
riscv.org
7. London Open Source Meetup for RISC-V 19 April 2021
7
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online Tutor application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
8. London Open Source Meetup for RISC-V 19 April 2021
8
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Visualising RV32I RISC-V Architecture
Single cycle datapath diagram Online Tutor datapath diagram
memory
PCPlus4
selB
ra/x1
sp/x2
gp/x3
tp/x4
t0/x5
t1/x6
t2/x7
4
extImm
zero/x0
WBDat
3
selWB
0
1
2
2
selDToM
sel
s1/x9
a0/x10
a1/x11
a2/x12
a3/x13
a4/x14
a5/x15
s0/fp/x8
2
rs1D
MWr selDFrM selWBD
MToWB
DToM
ALUOut
extImm
rs2D
ALUOp
branch
15 BGEU
14 BLTU
13 BGE
12 BLT
11 BNE
10 BEQ
9 SLTU
8 SLT
7 SRA
6 SRL
5 SLL
4 XOR
3 OR
2 AND
1 SUB A–B
0 ADD
ALU
add
sel
1
0
PC
selA
ALUBSrc
WB
MRd
selLdSlice
(15:0)
(7:0)
(7:0)
(15:0)
2 lb
0 lw
1 lh
4 lbu
3 lhu
24{7}
16{15}
24{’0'}
16{’0'}
DFrM
auipc
A
B
1
0
PC
1
0
jalr
+
base
offset
2 sb
0 sw
1 sh
(15:0)
(7:0)
16{’0'}
24{’0'}
rs2D
jalr
sel
PCSrc
brAdd
selDToM
2
selStSlice
rs2
rs1
5 5
RWr
RB
WBDat
DEC
rd
5
32-bit RISC-V processor
IM
instruction
PC
brAdd
0
1
selPCSrc
PCPlus4
4
+
PCCU
nPC
clk
rst
WB
ID EX MEM
IF
genBrAdd
EX
WB
IF ID EX MEM WB
memory
access
writeback
execute, address
calculation
decode
instruction instruction
fetch
[11] John Hennessy/David Patterson
9. London Open Source Meetup for RISC-V 19 April 2021
9
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Online Tutor: Audience/Strategy
• Target audience
• Professors/Students, Embedded Systems/IP Developers, Programmers
... interested in RISC-V Fundamentals; what’s Inside a RV32I RISC-V processor?
• Integrated training and practice (15 hours online, excluding labs)
• From RISC-V digital logic hardware to C programming
• Lesson strategies
• Online, self-paced
• Integrated with remote RISC-V hardware
• Interactive, learn-by-doing experience, visually-rich
• Guided-learning, sandboxes, knowledge checks
10. London Open Source Meetup for RISC-V 19 April 2021
10
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Course Structure
From RISC-V digital logic hardware to C programming
A. Front: introduction, resources, references
B. Tools tutorials
• Assembly language Venus [8] online simulator
• Remote RISC-V hardware: program instruction upload, execute, hardware debug
C. RV32I assembly instruction-by-instruction -- processor hardware support
D. RV32I RISC-V hardware design-to-prototype (HDL-based), with memory-mapped
peripherals, using industry-standard tools / hardware description language (HDL)
E. Assembly program applications (including games)
F. Advanced Topics: pipelining/hazards, C-to-assembly
Course homepage
11. London Open Source Meetup for RISC-V 19 April 2021
11
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Detailed Course Structure
Section/Topics Duration (min)
1. Intro, resources, references, application demos
+ 1. Introduction: RISC-V Processor Architecture & Applications 90
2. Learning Outcomes RV32I RISC-V instruction generator and viewer
2. RV32I RISC-V instruction generator and viewer
3. RISC-V references
4. Tour of vicilogic online learning and prototyping platform
+ 5. Game application demos (executing on remote RISC-V)
2. addi register-immediate instruction 120
3. Tools: Assembly program capture/simulation.
Program upload to remote hardware, execute and debug 120
4. RV32I instruction set index and supporting hardware architecture
+ 1. add/sub register-register 40
+ 2. Register-immediate addi, xori, ori, andi, slti, sltiu 60
+ 3. Register-register add, sub, xor, or, and, slt, sltu 20
+ 4. Constant-shift slli, srli, srai, register-shift sll, srl, sra 35
+ 5. lui load upper immediate 15
+ 6.beq, bne, blt, bge, bltu, bgeu branch
Program: delay loop 50
+ 7.Program: shift x10 register left each sec lui, add, addi, slli, bne 25
+ 8. Store/load to/from memory sw, sh, sb, lw, lh, lb, lhu, lbu 60
+ 9. auipc add upper immediate to PC 20
Section/Topics Duration (min)
5 RV32I Processor hardware design (HDL capture-to-prototype)
memory-mapped peripherals
Hardware Description Language model capture, simulation, logic synthesis
+ 1. Bldg blocks IF PCCU/IM, ID DEC/RB, EX EX/ALU, MEM memory, WB writeback 35
+ 2. RV32I processor HDL model - prototype on vicilogic remote FPGA hardware maj lab
+ 3. Memory-mapped peripheral components applications 45
Custom instruction addition (future work)
6. Assembly program applications (game app development)
+ 1. Functions and stack handling 40
+ 2. Game application development Major lab
7. Advanced Topics (pipelining/hazards, C-to-assembly)
+ 1. Pipelined RV32I RISC-V processor architecture, handling hazards 60
+ 2. C program compilation to RISC-V assembly 30
12. London Open Source Meetup for RISC-V 19 April 2021
12
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online Tutor application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
13. London Open Source Meetup for RISC-V 19 April 2021
13
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Online Learning/Prototyping/Course Builder
PYNQ-Z2
DE10-Nano
• Use remote (FPGA) hardware [20.3]
• ARM Processing System (controller)
and Programmable Logic (PL) (entity)
PL
Programmable
Logic
AXI
Client
Controller Entity
14. London Open Source Meetup for RISC-V 19 April 2021
14
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
• Architecture supports
• Centralised vicilogic FPGA resources
• Distributed FPGA resources
• Locally-connected FPGAs
Online Learning/Prototyping/Course Builder
[3]
15. London Open Source Meetup for RISC-V 19 April 2021
15
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
User Design (UD) RTL development
parse/wrap UD
Upload UD project to server
Create User Design view
Create UD lesson step
Include step in course
Execute course step
Generate FPGA config
bitstream and UD metadata
Online course builder (admin)
Online Course Builder Steps
UD User Design
HDL capture, simulation, logic synthesis
Wrapped UD
Probe
register
Control
register
AXI
Client
browser
vicilogic
server
Projects
Views
Lessons
Courses
Users
Groups
Controller
/entity
(cfg bitstream,
metadata)
Connect internal signals
to probe register
16. London Open Source Meetup for RISC-V 19 April 2021
16
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Online Course Builder Demo
Demo video: 4-bit counter
User Design (UD) RTL development
parse/wrap UD
Upload UD project to server
Create User Design view
Create UD lesson step
Include step in course
Execute course step
Generate FPGA config
bitstream and UD metadata
Online course builder (admin)
Uses lesson in course
Digital Systems Design and FPGA Prototyping:
Course builder
commands
Fundamentals, HDL and EDA tools
17. London Open Source Meetup for RISC-V 19 April 2021
17
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
18. London Open Source Meetup for RISC-V 19 April 2021
18
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Memory Store/Load Instructions Demo
• Memory store/load
• Demonstrates
• Store/load data transfer
• Signal widget highlighting
memory
Register Bank
Instruction
memory
ALU
Program Counter
Control Unit
(PCCU)
19. London Open Source Meetup for RISC-V 19 April 2021
19
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
5-Stage Pipeline reg-imm Instruction Demo
• 5-stage RV32I pipeline
execution
instruction addi x1, x0, 0x35
• Demonstrates
• Pipelined register operation
• Interactive timing diagram
• Instruction stage execution
in pipeline table
Pipeline registers
Pipeline table
Timing diagram
ID
MEM
WB
IF
EX
20. London Open Source Meetup for RISC-V 19 April 2021
20
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Game Application Demos
• Game applications
• Assembly language
• Peripherals
• RNG counter
• In/out ports
• RISC-V debug interface
• Future
• extend peripherals for
development of range
of low-end embedded
applications
21. London Open Source Meetup for RISC-V 19 April 2021
21
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
5. RV32I Processor hardware design (HDL capture-to-prototype),
memory-mapped peripherals
Hardware Description Language model capture, simulation, logic synthesis
+ 1. Building blocks IF PCCU/IM, ID DEC/RB, EX EX/ALU, MEM memory, WB writeback
+ 2. RV32I processor HDL model - prototype on vicilogic remote FPGA hardware
+ 3. Memory-mapped peripheral components applications
Custom instruction addition (future work)
Hardware Design / RTL - Prototype
ALU
WB
PCCU
EX
memory
22. London Open Source Meetup for RISC-V 19 April 2021
22
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Top
RISCV0
RISCV1
IF
EX
WB ID
MEM
RISCV0
EX
WB
• Design hierarchy (dual core RV32I)
Hardware Design / RTL - Prototype
Electronic Design Automation EDA toolsuite
23. London Open Source Meetup for RISC-V 19 April 2021
23
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online Tutor application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
24. London Open Source Meetup for RISC-V 19 April 2021
24
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
User Experience / Feedback
• Course lesson ratings (1-10), 79%–84%, # respondents
Sep-Dec 2020
End of lesson surveys
25. London Open Source Meetup for RISC-V 19 April 2021
25
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
User Comments
• ”labs and exercises”
• ”interactive diagrams / coloured widgets”
• ”visualising internal signals and registers”
• ”combination of view and lesson text”
• ”video demos”
• ”breakdown of instruction step-by-step / thorough coverage”
• ”sandboxes”
• ”knowledge checks and challenges”
• ”example assembly program descriptions and demos”
• ”worked examples”
• ”good flow between reading text and understanding what was happening on hardware”
• ”instruction generator/viewer is really useful”
• ”star widgets highlighting active datapath (indicating where to look)”
• ”signals being shown at the top of the screen (to aid bit-level activity)”
• ”good pace. Being able to prove that I know this stuff”
What element(s) of the lessons did you find most useful?
26. London Open Source Meetup for RISC-V 19 April 2021
26
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
FPGA Usage Stats
• No. of remote FPGA sessions (45 users)
• 3 week period (Fri 23 Oct–Thu 12th Nov 2020)
• Each column colour segment highlights the
level of configuration/use of a specific FPGA
• b), c) contribution of individual users
• a) combined contribution of all users
• 112,000 FPGA configurations since Feb 2018
200
300
100
b)
c)
23Oct
a)
12Nov
No. of remote FPGA sessions
27. London Open Source Meetup for RISC-V 19 April 2021
27
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Presentation Overview
• RISC-V introduction
• RISC-V Online Tutor course strategy and demo
• vicilogic Online learning, remote FPGA prototyping, course builder
• RISC-V Online Tutor application program demos
• RISC-V Online Tutor user experience and feedback, FPGA usage stats
• Inviting Community participation and collaboration / Future Work
28. London Open Source Meetup for RISC-V 19 April 2021
28
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
• Access courses vicilogic.com/register/ (please share links)
• Available courses vicilogic.com/vicilearn/course/
•
• Digital Systems Design and FPGA Prototyping:
Fundamentals, HDL and EDA tools
• Callorate on course creation, e.g,
• RISC-V extensions
• Cache memory architectures
• other
Inviting Community Participation/Collaboration
29. London Open Source Meetup for RISC-V 19 April 2021
29
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
• Extend RISC-V peripherals, enabling low-end remote embedded apps
Future Work
AXI
Client
browser
inport
outport
Signal generators
Physical Peripherals
Sensors, actuators
VGA, I2C, SPI
Switch/LED
Peripheral
emulation
30. London Open Source Meetup for RISC-V 19 April 2021
30
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
• Embedded online assembler
• Integrate with courseware, with
• editor auto-load
• Assembler
• Program upload
• Debug UI
• Enable user remote hardware prototyping and UI creation
• Addition of custom instructions / hardware
• Extend C-to-assembly course content
Future Work
31. London Open Source Meetup for RISC-V 19 April 2021
31
fearghal.morgan@nuigalway.ie
Presentation https://tinyurl.com/BCSRISCVOnlineTutor
Thankyou
fearghal.morgan@nuigalway.ie