This document discusses the development of a soft-core processor system utilizing a MicroBlaze processor on a Virtex-5 FPGA, transitioning from traditional hard-core designs. It outlines the implementation of various peripherals and the integration of a software development kit (SDK) for streamlined design processes, emphasizing the flexibility and configurability of soft-core systems for embedded applications. The paper also details design flows, testing methodologies, and results from testing various system components.

1. Development of Soft-Core Processor System on
FPGA
A. Dr. M. Kamaraju 1
, B. Sk. Parveen2
, and C. T. Jaya Prakash3
1
Gudlavalleru Engineering College/Electronics & Communication Engineering, Gudlavalleru, Andhra Pradesh, INDIA
Email: madduraju@yahoo.com
2
Gudlavalleru Engineering College/Electronics & Communication Engineering, Gudlavalleru, Andhra Pradesh, INDIA
Email: parveenshaik90@gmail.com
3
Electronics Corporation of India Limited/Corporate Research & Development, Hyderabad, Andhra Pradesh, INDIA
Email: tjayaprakash@ecil.co.in
Abstract— In this paper, proposed a novel implementation of a Soft-Core system using
micro-blaze processor with virtex-5 FPGA. Till now Hard-Core processors are used in
FPGA processor cores. Hard cores are a fixed gate-level IP functions within the FPGA
fabrics. Now the proposed processor is Soft-Core Processor, this is a microprocessor fully
described in software, usually in an HDL. This can be implemented by using EDK tool. In
this paper, developed a system which is having a micro-blaze processor is the combination
of both hardware & Software. By using this system, user can control and communicate all
the peripherals which are in the supported board by using Xilinx platform to develop an
embedded system. Implementing of Soft-Core process system with different peripherals like
UART interface, SPA flash interface, SRAM interface has to be designed using Xilinx
Embedded Development Kit (EDK) tools.
Index Terms— SOPC system, EDK tool, FPGA, Micro-Blaze, Soft-core processor.
I. INTRODUCTION
In the present days technology FPGA’s are used in every application area for the replacement of discreet
logic and implementation on system on programmable chip (SOC). With the SOC system all the peripherals
and glue logic in a bigger design area can be accommodated in a single FPGA.
Field programmable gate arrays [11] provide designers with the ability to quickly create hardware circuit
designs. Increases the logic capacity of FPGA and decreasing cost of FPGA have enabled designers to more
readily incorporate with FPGAs to design. FPGAs have providing configurable soft processor cores, which
can be synthesized onto FPGA supporting boards. While FPGAs with soft-core processor provide designers
with highly increased flexibility, such processors have degraded performance and energy consumption
compared to hard-core processors [2].
The aim of the paper is to implement and development of micro-blaze system [12] with FPGA. Some of the
decisions and design tradeoffs which must be made during the design process like System on Programmable
Chip (SOPC) based on Virtex-5 FPGA which is developed using micro-blaze RISC soft-core processor.
Creation of different peripherals like UART interface, SPA flash interface, SRAM interface has to be
designed using Xilinx Embedded Development Kit (EDK) tools. The scope of the paper the SOPC system
DOI: 02.ITC.2014.5.14
© Association of Computer Electronics and Electrical Engineers, 2014
Proc. of Int. Conf. on Recent Trends in Information, Telecommunication and Computing, ITC

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can be implemented very easily and new peripherals can be added at any time.
The rest of the paper is as follow. In Section 2, explain the proposed setup of the system i.e., the hardware
description. Section 3 explains the Proposed Soft-Core Processor. Section 4 explains the implementation of
the system Section 5 explains the design flow and working of the SOPC system. Finally conclude the paper
describing accomplishments.
II. HARDWARE DESCRIPTION
The Hardware consists of different components, which are interfacing to a Soft-Core process system.
As shown in fig.1, The various components in the hardware are Virtex-5 FPGA , SDRAM (256 MB), SRAM
(1 MB), Linear Flash (32 MB), Compact Flash, Platform based Flash, SPI-Flash, JTAG interface, External-
clocking , USB - host and peripheral, PS/2 - keyboard, mouse, RJ-45 - 10/100 Networking, RS-232 - serial
port, Audio In - line, microphone, Audio Out - line, amp, SPDIF, piezo speaker, Video Output, Single-ended
I/O expansion and differential I/O expansion, GPIO DIP switch, GPIO LEDs, GPIO push buttons.
Figure 1. Hardware Board
III. PROPOSED SOFT-CORE PROCESSOR
In reconfigurable systems [1], hardware implements performance critical parts of the application. Since
various systems are inclined to use most common algorithms, many of the developed components can be
reused. These Reusable components come under intellectual property (IP) cores. To build a larger or more
complex system an IP is used, which is a standard block of data or logic. IP cores are divided into three
categories, based on the level of optimization, and flexibility of reuse: soft cores, firm cores, and hard cores
[3].
A soft-core is a microprocessor fully described in software, usually in Hardware Description Language,
which can be synthesized in programmable hardware, such as FPGAs. A soft processor core targeting FPGAs
is flexible because, by reprogramming the device, its parameters can be changed at any time. Traditionally,
systems have been built using general-purpose processors, which are implemented as Application Specific
Integrated Circuits (ASIC), and placed on printed circuit boards that may have included FPGAs if flexible

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user logic was required. Using soft-core processors, such systems can be integrated on a single FPGA chip as
shown in fig.2, that the soft-core processor provides tolerable performance [1]. Recently, two commercial
soft-core processors have become available: Nios [4] from Altera’s Corporation, and Micro-Blaze [5] from
Xilinx.
The proposed Micro-Blaze Soft-Core processor is shown in fig. 2.
Figure 2. Proposed Micro-Blaze Soft-Core Processor
Soft-core processors are one aspect of the trend in architecture commonly known as reconfigurable
computing. Recent developments in FPGA technology made FPGAs as a best target for processor
implementations. By the reprogramming of FPGAs the processor parameters can be changed during the
lifetime of the product, if the need arises. However, an FPGA implementation of a soft-core processor will
typically provide lower performance than the corresponding ASIC design [1].
A soft-core is usually a synthesizable Hardware Description Language specification [13] that can be
retargeted to various semiconductor processes. A firm-core is commonly specified as a gate-level net-list,
suitable for placement and routing, while a hard-core also includes technology-dependent information like
layout and timing. Generally, soft-cores provide the highest flexibility, allowing many core parameters to be
changed before synthesis, while hard-cores provide slight or no flexibility [1].
IV. IMPLEMENTATION
A. Hardware Platform using XPS (XPS using EDK)
Xilinx technology allows FPGA (Field Programmable Gate Array) to customizing the hardware logic in
subsystems of a processor. Such customization is not possible using standard microprocessor or controller
chips.
Hardware platform is a flexible, embedded processing subsystem which creates with Xilinx technology for
embedded application. This consists of one or more processors and peripherals connected to the processor
buses. EDK captures the hardware platform using the Xilinx Platform Studio in the Microprocessor
Hardware Specification (MHS) file [6].

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The MHS file is the primary source file that maintains the hardware platform description represents in ASCII
text and the hardware components of embedded system. When the hardware platform description is
complete, then the hardware design can be exported for use by Software Development Kit (SDK) [6].
B. Software Platform using Software Development Kit (SDK using EDK)
A software platform is a collection of software drivers, optionally the OS (operating system) on which to
build for the application. The created software image consists only of the portions of the Xilinx library which
is used in embedded design [6]. EDK captures the software platform using Software Development Kit in the
Microprocessor Software Specification (MSS) file as shown in fig.3, which gives the information about
Embedded Soft-core System design process flow and the functions of EDK.
Figure 3. Embedded Soft-Core System design process flow
C. Functions of EDK
These are following four functions for adding Custom peripherals to System in EDK [7].
Determining Interface Identify the bus interfaces like OPB or PLB to implement the custom peripherals, so
that it can be attached to that bus in the processor system.
Functionality Implementation and Verification: Implement custom functionality, reuse the common
functionality already available from EDK peripheral libraries as much as possible, and verify peripheral as a
stand-alone core.
Import to EDK: Copy the Custom peripheral to an EDK recognizable directory structure and create the PSF
interface files (.mpd/.pao) so that other EDK tools can access those peripheral.
Add to System: Add that peripheral to the processor system in EDK.
V. SOPC DESIGN FLOW
Traditional system-on-chip (SoC) designs require the development of a custom Integrated Circuits (IC) or
application Specific Integrated Circuits (ASIC) [9]. Unfortunately, ASIC costs have raised dramatically in
recent years along with the huge improvements in feature size and transistor counts of VLSI technology.
Current ASIC trade development costs run several million dollars per device. Only a few high level
embedded products can support long ASIC development times and high costs.
A capable new alternative technology has developed that enables designers to operate a large FPGA that
contains both memory and logic elements along with an intellectual property (IP) processor core to quickly
implement a computer and custom hardware for SoC embedded systems [10]. This methodology is called
system-on-programmable-chip (SoPC) [8].
The SOPC Builder also generates a Software Development Kit (SDK) customized for the generated system.
The generated SDK form is a foundation for the software development of a system. If the system includes
more than one processor, a custom SDK form is generated for each of the processors, since different
processors may support different instruction sets and use different peripherals [1].

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The SDK generated by the SOPC builder contains routines and drivers of EDK library for standard system
components [1]. Users must provide drivers and library code for any custom peripherals used in the system.
Driver and library code development is generally done in low-level C or assembly language.
Figure 4.Working of Xilinx based Embedded SoPC Design flow
Working of Xilinx based Embedded System on Programmable Chip design flow is shown in fig. 4. After
giving the initial system specification, the design flow is divided into two parts like, a hardware development
and software development. Properties of Processor, memory and peripherals are defined during the hardware
development process. In Software Development process user programs and other system software’s are
developed and built. The software development depends on the hardware development results, because
Software Development Kit (SDK), customized for the system, is desired to build the system software. The
SDK defines library routines and drivers used in the software development process. After both the system
hardware and software have been built, the system prototype is tested on a development board. If the system
meets its specification, the system design completed successfully. Otherwise, either hardware or software
needs to be redesigned.
VI. RESULTS
Hardware is ML-501 board that contains Virtex-5 FPGA and all the components that are communicated with
FPGA like SDRAM (256 MB), SRAM (1 MB), Linear Flash (32 MB), Compact Flash, Platform based Flash,

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SPI-Flash, JTAG interface, External-clocking , USB - host and peripheral, PS/2 - keyboard, mouse, RJ-45 -
10/100 Networking, RS-232 - serial port, Audio In - line, microphone, Audio Out - line, amp, SPDIF, piezo
speaker, Video Output, Single-ended I/O expansion and differential I/O expansion, GPIO DIP switch, GPIO
LEDs, GPIO push buttons. And that hardware is interface with Software through UART and JTAG.
Xilinx Platform Studio is used to construct both hardware and software project that will control various user
input/output devices on the supported FPGA board.
XPS is a GUI that helps to specify the system, which processors, memory blocks and other soft IPs
(Peripherals) to use. Interconnection of different IPS and the memory map (addresses for memory mapped
I/O peripherals). XPS also interfaces the tools used all over the design flow that consisting of the components
like a Micro-Blaze Processor, a UART (serial port) and a memory block.
To start a project in XPS start->all programs->Xilinx ISE design suite 13.2->Embedded Development Kit->
Xilinx Platform Studio.
Navigate to C:WorkshopSoftcore_Processor_XPSXPS. Double click on system.xmp to open the project in
Xilinx Platform Studio (XPS). Each XPS project is composed to two parts. The first defines the hardware
configuration which describes the layout of the various IP cores in logic and the bus connections that enable
data transfer between IPs. The software half describes the code that will run in Embedded Development Kit
(EDK).The instructions for EDK are stored in Block RAMs (BRAM). Once the bit-stream for the hardware
part has been generated, it needs not to be updated during C-code iteration.
To create a new design selects the requirement of hardware architecture shown in table I.
TABLE I: ARCHITECTURE OF HARDWARE
ARCHITECTURE DEVICE PACKAGE SPEED GRADE
VIRTEX XC5VLX50 FF676 -3
Connect all the board components that are interfaces to the project like LEDs, LCD, Buttons, Switches, and
Memories etc. Then select the location of software and the mapping of STD IN/OUT. Keep the RS232
(UART) for both STDIN and STDOUT. The partial lists of all the buses that are used in project are shown in
table II. Make all the applications have their data and instructions those are mapped into local on-chip
memories (accessed through ILMB_CTRL and DLMB_CTRL controllers).
TABLE II: PARTIAL LIST OF BUSES THAT ARE USED IN PROJECT
LMB LOCAL MEMORY BUS CPU <-> MEMORY BUS (POINT TO POINT BUS)
PLB PROCESSOR LOCAL BUS CPU <-> PERIPHERAL BUS (SHARED BUS)
GPIO GENERAL PURPOSE IO GLUE LOGIC FOR THE BUTTONS LEDS ON THE BOARD
RS232 SERIAL PORT USED FOR TEXT INPUT/OUTPUT OF APPLICATION
XPS window contains three tabs like Project tab, Application tab and IP Catalog tab. Project tab contains
general system files as well as LOG files. Application tab contains the software parts of the system, and
finally IP catalog contains all the IP components that can use to build the system.
Xilinx Platform Studio which gives information of Bus interfaces of Peripherals which are using in the
system, information of ports that the Peripherals are connected in the processor system and gives addresses
for the Peripherals which are using in the system. These addresses are generated directly by the system.
Then build the system through XPS by the tool; device configuration -> update bit-stream. This tool build
whole system that is synthesizes the hardware as well as compiles the software and prepares the
configuration file for fpga.
XPS automatically configures and generates the library code for the system. Then generate bit-stream for the
system by the tool; hardware -> generate bit-stream. Then this generated bit-stream contains hardware
synthesis like create the logic circuit (net-list), create the fpga configuration (bitmap).
During the hardware synthesis, the tools use a user constraint file (UCF), which can be found in the left
frame in the project tab. UCF file binds external ports in the design to physical pins on the fpga.
Downloading the configuration to the fpga is to merge software binaries and the bit stream from the hardware
synthesis, run device configuration -> Update bit-stream. This places the executable in the on-chip memory,
making the configuration file ready to be downloaded on the fpga.
To run the final implementation of fpga, go to the hyper-terminal through start->all programs->accessories->
communications-> hyper-terminal.

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Give the new connection a new name and chose com1 in connect using frame. Port settings are used
according to the uart parameters shown in table III.
TABLE III: UART PORT SETTINGS
BITS PER SECOND 9600
DATA BITS 8
PARITY NONE
STOP BITS 1
FLOW CONTROL NONE
Finally, click the program button to download the configuration to the FPGA. Then hardware system is
transferred to software development kit to link both hardware and software. It will generate embedded linked
file (.Elf file) which is the linked file of both hardware and software. Then give the I/O connections and baud
rate for the hyper-terminal to execute the system. Finally the embedded linked file is transfer to FPGA which
includes both hardware and software along with ucf file.
Then the hyper-terminal gives the output of system as the menu of testing peripherals that are communicates
with the embedded system. Testing of various devices are done and found that successfully implemented.
Tests are i) Testing of SDRAM: SDRAM tests, where the given data is either having data errors or address
errors. And gives the information about how much amount of data is passed through the memory in bytes,
half-words and words. ii) Testing of SRAM: where the given data is either having data errors or address errors
by stuck at zero and stuck-at-one logic and passes the information in bytes only.iii) Testing of LEDs: LED’s
are glow by the given logic. In this project LED’s are move in a pattern. iv) Push buttons test: Push Buttons
are used to give and change the information from one mode to another mode of flash memory. These buttons
have delay of time. v) Testing of LCDs: By using LCD user can read write the characters in the memory by
using ASCII values. vi) Testing of Flash Memory: This memory can be modify and erase the contents in
linear flash. According to the modes of Flash Memory we can modify or erase the data and store new data in
that mode and access it. vii) IIC EEPROM test: IIC EEPROM gives addresses 0X4C1 to 0XFFF are available
for user use. Addresses 0X000 to 0X4C0 are reserved for Xilinx use. This memory passes the data through
IIC bus which is electrically erasable and modified. viii) Piezo test; Piezo test is also called as alarm test. If
any error occurs in hardware or software it gives an alarm which is a beep sound to alert.
VII. CONCLUSION AND FUTURE WORK
By using the EDK Tool developed a soft-core system using micro-blaze processor, which is used to
communicate and control all the peripherals like UART interface, JTAG interface, LED’s, LCD’s and
memories like SRAM memory, SDRAM memory, IICEEPROM on the Hardware board. As well as it
includes external new peripherals by using Intellectual Property (IP) at any time.
This logic can be developed for all the peripherals and it can also implement on USB bus, So that the system
completes a universal processor.
ACKNOWLEDGEMENT
I Sk. Parveen glad to express my deep sense of gratitude to Dr. M. KAMARAJU, Professor and HOD,
Electronics and Communications Engineering Department, for his guidance, co-operation and encouragement
in completing this project. Through this I want to convey my sincere thanks to him for inspiring assistance
during my project.
I Sk. Parveen wish to express my deep sense of gratitude to Mr. T. JAYAPRAKASH, Technical Manager,
Corporate research & development, Electronics Corporation Of India Ltd, Hyderabad for giving me
opportunity to do project in ECIL and for providing facilities to complete the project.
REFERENCES
[1] Franjo Plavec, “SOFT-CORE PROCESSOR DESIGN” Master of Applied Science Graduate Department of
Electrical and Computer Engineering University of Toronto 2004. Available
HTTP:://citeseerx.ist.psu.edu/messages/downloadsexcedded.html.
[2] Petar Borisov Minev and Valentina Stoianova Kukenska, “IMPLEMENTATION OF SOFT-CORE PROCESSORS
IN FPGAs” in International Scientific Conference on 23 – 24 November 2007, Gabrovo.

8. 291
[3] R. K. Gupta and Y. Zorian, “Introducing Core-Based System Design,” IEEE Design and Test of Computers, vol. 14,
no. 4 (October-December 1997), pp 15-25.
[4] Altera Corporation, “Nios Embedded Processor System Development,” [Online Document, Cited 2004 February 2],
Available HTTP: http://www.altera.com/products/ip/processors/nios/nio-index.html.
[5] Xilinx, Inc., “Micro-Blaze Soft Processor,” [Online Document, Cited 2004 February 2], Available HTTP:
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=microblaze.
[6] Xilinx, Inc., “Embedded System tools reference manual,” [Online Document (v 14.3) October 16, 2012]. Available
HTTP: http://www.xilinx.com/suppot/documentation/sw_manuals/edk10_est_rm.
[7] Micro-blaze Tutorial by Rod Jesman, Fernando Martinez Vallina Jafar Saniie, “Creating a simple embedded system
and adding custom peripherals using Xilinx EDK software tools”. Available HTTP:
http://ecasp.ece.iit.edu/tutorials/microblaze_tutorial.pdf.
[8] J. O. Hamblen and T. S. Hall, International Journal of Computer Application, “Using System-on-a-Programmable-
Chip Technology to Design Embedded Systems” retrieved vol.13, No.3, Sept. 2006.
[9] H. Chang, L. R. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd, Surviving the SOC Revolution a Guide to
Platform-Based Design, Kluwer Academic Publishers, 1999.
[10] C. Snyder, “FPGA Processor cores get serious,” in Cahners Microprocessor Report, http://www.MPRonline.com/,
Sept. 2000.
[11] Niklaus Wirth. "The Design of RISC Architecture and its Implementation with an FPGA". Retrieved 6 Sep 2012.
[12] "GCC 4.6 Release Series Changes, New Features, and Fixes". 2011-03-15. Retrieved 2011-03-15. "Support has been
added for the Xilinx Micro-Blaze soft-core processor (micro-blaze-elf) embedded target."
[13] Tim Erjavec, White Paper, "Introducing the Xilinx Targeted Design Platform: Fulfilling the Programmable
Imperative." February 2, 2009. Retrieved February 2, 2009.