1) The document presents designs for reversible logic gates and their applications in low power circuits. It proposes an improved design for a reversible programmable logic array (RPLA) using multiplexer and Feynman gates that is more efficient than existing designs. 2) It also proposes a method for structuring a reversible arithmetic logic unit (ALU) using reversible logic gates instead of traditional gates, achieving the same functionality with reduced information loss. 3) The RPLA design is demonstrated by implementing reversible 1-bit full adders and subtractors. Simulation results show the proposed design optimizes the number of reversible gates used.

1. COST-EFFECTIVE DESIGN OF REVERSIBLE LOGIC GATES
AND ITS INDUSTRIAL APPLICATIONS
Presented designed by
AMITH BHONSLE
Masters of Technology [ VLSI Design]
VTU,Belgaum.

2. INTRODUCTION
Designing of a complex digital system which dissipates low power is a competitive topic in the research field
of hardware design. Heat dissipation in the circuit has become the critical limiting factor .
Rolf Landauer introduced that losing of bit in circuits causes the smallest amount of heat in computation and
the theoretical limit of energy dissipation for losing of one bit computation is KTln2
Even C.H. Bennett in 1973 also showed that the dissipated energy directly correlated to the number of lost bits

3.  kTln2 energy dissipation would not occur, if a computation is carried out in a reversible way .
 This is so because reversible computation does not require erasing any bit of information.
 The amount of energy dissipated in a system bears a direct relationship to the number of bits erased
during computation.
 Voltage-coded logic signals have energy of Esig = ½CV2, and this energy gets dissipated whenever
switching occurs in conventional (irreversible)
logic implemented in modern CMOS technology.
 In recent past reversible computation has emerged as a
promising technology having applications in low power
CMOS, nanotechnology, optical computing, optical
information processing, DNA computing,
bioinformatics, digital signal processing etc.
 Reversible circuits are of high interest in low-power
CMOS design, optical computing, quantum computing
and nanotechnology.

4.  With miniaturization it faces two issues
i) A considerable amount of energy gets dissipated in VLSI circuits.
ii) The size of the transistors are approaching quantum limits where tunnelling and other quantum phenomena are
likely to appear.
 Reversible computation does not require erasing any bit of information. Consequently, it does not dissipate any
energy for computation.
 These circuits can generate unique output vector from each input vector, and vice versa, that is, there is a
one-to-one mapping between input and output vectors.
 The second problem can be solved by doing computation with quantum resources. When we do so then it is
called quantum computing
 In quantum computing we use quantum logic gates with qubits as input state and in classical reversible
computing we use reversible logic gates and bits as input state similar to digital circuits

5.  Quantum teleportation, infinitesimally secured cryptography and super dense-coding do not have any classical
analogue.
 Now we may list the basic problems of reversible and quantum circuit designing as below:
-We need efficient circuit synthesis algorithms to design new circuits for some meaningful purposes.
-To improve an existing circuit in terms of circuit cost, quantum cost, delay, garbage count and other
quantitative measures we need to optimize the cost metrics.
 Programmable logic arrays (PLAs) have a number of medical and industrial applications, such as ultrasonic
flaw detection
 The reasons stem from the fact that PLAs are considerably faster than high end DSPs.
 They provide the cost effective solution to the exponentially increasing needs of industrial electronics.

6. REVERSIBLE LOGIC
The logical reversibility means there should be same number of output lines as the number of input lines i.e. the
number of input lines and output line must be same or there should be one to one mapping between the input and
output.
The gate must be run forward and backward i.e. the input can also be recovered or retrieved from the output.
When the device obeys these two conditions then the second law of thermodynamics guarantees that it
dissipates no heat.
For logical reversibility in the digital logics there are two conditions as follows.
1. Fan-Out is not permitted
2. Feedback is not permitted

7.  Reversible circuit is composed of reversible logic gates.
 Using reversible logic we can obtain full knowledge of inputs from the outputs.
 The boolean function that maps the input to output is bijective.
 Feedback in a reversible circuit cannot be visualized in the sense in which feedback is visualized in a
conventional irreversible circuit.
 Once a reversible circuit or quantum circuit is synthesized we need to evaluate its quality. Different cost
metrics such as gate count (circuit cost), number of garbage bits, quantum cost
(total number of elementary quantum gates), transistor cost and
delay are proposed

8. Quantitative measures of circuit costs
There exist several heuristic algorithms for synthesis of classical reversible circuits and quantum circuits.
1.Gate Count [Circuit cost].
Gate count is the total number of gates in a circuit.
2.Quantum Cost
The quantum cost of a reversible gate is the number of elementary quantum gates needed to implement the
gate. It is the number of reversible gates (1×1 or 2×2) to realize the circuit.
3.Garbage bits
Garbage bits are the additional outputs that makes a function reversible and is not used for further
computations. It is the number of outputs that are not primary. Miller has shown that addition of new working
lines (i.e. essentially additional garbage bits) may be helpful to reduce quantum cost of a circuit.
4.Transistor Cost
The TrC [Transistor Cost] of a circuit is the total number of transistors required to implement the circuit.

9. 5. Total Cost
It is often observed that reduction of circuit cost leads to increase in garbage bits and reduction of quantum
cost leads to increase in circuit cost. Total cost (TC) is the sum of gate count of an optimized circuit, number
of garbage bits and quantum cost. It is the count of the XOR, AND, NOT logic in the output circuit.
5. Delay
A reversible circuit design can be visualized as a sequence of discrete time slices and depth is summation of
total time slices.

10. REVERSIBLE GATE STRUCTURES
1.Fredkin Gate
3×3 Fredkin gate structure. Quantum cost of a fredkin gate is 5.
Fredkin as a. OR function b. AND function

11. 2. Feynman Gate
2×2 reversible gate called Feynman gate [5]. Feynman gate is also recognized as controlled- not gate
(CNOT). Quantum cost of a Feynman gate is 1.
Feynman gate as a. Not gate b. Data Copier

12. 3. Toffoli Gate
3x3 Toffoli gate. Quantum cost of a Toffoli gate is 5

13. 4. MUX Gate
3x3 Mux gate, it’s Quantum cost is 4
MUX gate as a. AND Gate b. OR Gate

14. RPLA Block Implementation
 The reversible AND plane is designed by the MUX & Feynman gates to produce the required product terms
and to prevent of fan-out .

15. The design of reversible AND Plane of proposed RPLA

16. The design of reversible OR Plane of proposed RPLA

17. Quantized evaluation of parameters in proposed RPLA implementation
Total Logical calculation (T)
Assuming
α = A two input XOR gate calculation
β = A two input AND gate calculation
δ = A NOT gate calculation
T = Total logical calculation
MUX gate has three XOR gate and two AND gate and one NOT gate in the output expression.
Therefore (𝑀) = 3α+2β+δ.
the total logical calculation for reversible AND plane is: T = 16× (3α+2β+δ)( for MUX gate)+ 21×1α(for
Feynman gate) = 69α + 32β+16δ.

19. SIMULATION RESULTS
Simulated result of reversible AND plane

20. Simulated result of reversible OR plane

21. The designed 3 input RPLA is used to implement the 1 bit full adder and 1-bit subtractor. The 1-bit full adder as shown
below is implemented using the 3 input RPLA by generating the product terms in the full adder truth table through the AND
array, and then appropriately combining the product terms through the reversible OR array to finally generate the required
SUM and CARRY output functions. Similarly, the 1-bit subtractor is implemented to generate the Difference and Borrow
output
functions.
Realization of Full Adder :-

22. Realization of Full Subtractor

23. • Now I propose a design constructing the Arithmetic Logic Unit(ALU) by using reversible logic gates instead of using
traditional logic gates. A reversible ALU whose function is the same as the traditional ALU is constructed. The
presented reversible ALU reduces the information bits use and loss by reusing the logic information bits logically and
realizes the goal of lowering power consumption.
-This figure depicts the frame of an n-bit
reversible ALU. The multi-function ALU based
on reversible logic gates mainly contains the
reversible function generator (FUNC) and the
reversible controlled unit (DXOR). The
reversible function generator and the reversible
controlled unit are cascaded by some n -Toffoli
gates and NOT gates, and arbitrary bit reversible
ALU modules can be realized by this way. In the
procedure of cascading the reversible function
generator and the reversible controlled unit, we
reuse the output signals to reduce the cost of
circuit design as mush as possible

24. Simulation of reversible ALU
• The logic function of the reversible ALU achieved is basically the same with that of 74181ALU
(the traditional 4-bit ALU).

26. CONCLUSION AND FUTURE SCOPE
In this project, emphasis is on efficient approach to design low power digital systems using proposed RPLA. An
improved design of RPLA is proposed and the concept of using MUX gate & Feynman gate for the design of RPLA is
efficient and cost-effective than the existing one. I also proposed a method for using the reversible logic gates as logic devices
to structure the reversible ALU. By using reversible logic gates instead of using traditional logic gates, the function of the
implemented reversible ALU is the same with that of the traditional ALU. It’s proved that functionality of the reversible ALU
is effective by using C ++ programming language. Comparing with the number of input bits and the discarded bits of the
traditional ALU, the reversible ALU does significantly reduce the use and loss of information bits.
Finally, the application of the RPLA is demonstrated by implementing the reversible 1-bit full adder and subtractor.
It is also demonstrated that the proposed design is highly optimized in terms of number of reversible gates. The simulated
results are also shown. So proposed RPLA will provide a new approach to the arena of low power reconfigurable computing
hardware.
It is now evident that reversible logic gates holds a great significance to the realization of the more
complex and systematic reversible circuits with reduced power consumption and loss of information bits.

27. THANK YOU