Reversible circuits are one promising direction withapplications in the field of low-power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge-Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,reversible implementations of ripple-carry, Kogge-Stone carrylook-ahead adders are analyzed and compared in terms ofdelay. The proposed design consists of the reversible Fredkin,Feynman, MG, HNG, PG and RKSC gates. The performancecharacteristics analysis is carried out in Xilinx environment. Swetha Potharla | Rajkumar R"A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5758.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/5758/a-novel-design-of-a-4-bit-reversible-alu-using--kogge-stone-adder/swetha-potharla
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmann’s constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit model
Design of High speed Low Power Reversible Vedic multiplier and Reversible Div...IJERA Editor
This paper bring out a 32X32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper we propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer, reversible n-bit register with parallel load line. The reversible vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i. This reversible vedic multiplier results shows less delay and less power consumption by comparing with array multiplier.
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmann’s constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit model
Design of High speed Low Power Reversible Vedic multiplier and Reversible Div...IJERA Editor
This paper bring out a 32X32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper we propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer, reversible n-bit register with parallel load line. The reversible vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i. This reversible vedic multiplier results shows less delay and less power consumption by comparing with array multiplier.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Reversable Logic Based Design using Submicron TechnologySai Viswanath
Reversible logic has emerged as a computing paradigm having application in low power CMOS, quantum and optical computing. Design of reversible logic gate is reversible operation, when we say reversible it performing computation in such a way that any previous state can be reconstructed at given a description of the current state. The classical set of gates such as AND, OR, and XOR are not reversible.
This presentation is a design of reversible logic gate used for reversible operation. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation results of forward & backward computation of reversible FREDKIN gate and TSG gate.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Optimized Reversible Vedic Multipliers for High Speed Low Power Operationsijsrd.com
Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
Logic gates, Karnaugh Maps, Sum of product, Product of sums, NAND implementation, NOR implementation, OR and INVERT implementation. Don't care condition. Logic minimization, And or invert implementation.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot C...IJERA Editor
Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that attempts to create general computational at the nano-scale by controlling the position of single electrons. Quantum dot cellular automata (QCA) defines a new device architecture that permits the innovative design of digital systems. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with smaller size & low power consumption.QCA help us to overcome the limitations of CMOS technology. In this paper, A design 16-bit arithmetic logic unit (ALU) based on the Quantum dot cellular automata (QCA) is presented. The simulation result of 16 bit ALU is verified using QCA Designer tool.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
High functionality reversible arithmetic logic unitIJECEIAES
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore‟s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17% reduction in garbage lines, 92% reduction in ancillary lines and 53% reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Reversable Logic Based Design using Submicron TechnologySai Viswanath
Reversible logic has emerged as a computing paradigm having application in low power CMOS, quantum and optical computing. Design of reversible logic gate is reversible operation, when we say reversible it performing computation in such a way that any previous state can be reconstructed at given a description of the current state. The classical set of gates such as AND, OR, and XOR are not reversible.
This presentation is a design of reversible logic gate used for reversible operation. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation results of forward & backward computation of reversible FREDKIN gate and TSG gate.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Optimized Reversible Vedic Multipliers for High Speed Low Power Operationsijsrd.com
Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
Logic gates, Karnaugh Maps, Sum of product, Product of sums, NAND implementation, NOR implementation, OR and INVERT implementation. Don't care condition. Logic minimization, And or invert implementation.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot C...IJERA Editor
Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that attempts to create general computational at the nano-scale by controlling the position of single electrons. Quantum dot cellular automata (QCA) defines a new device architecture that permits the innovative design of digital systems. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with smaller size & low power consumption.QCA help us to overcome the limitations of CMOS technology. In this paper, A design 16-bit arithmetic logic unit (ALU) based on the Quantum dot cellular automata (QCA) is presented. The simulation result of 16 bit ALU is verified using QCA Designer tool.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
High functionality reversible arithmetic logic unitIJECEIAES
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore‟s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17% reduction in garbage lines, 92% reduction in ancillary lines and 53% reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VIT-AP University
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder...VIT-AP University
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal
(BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and
13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to
implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic,
which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation
of detecting the missing gate and missing control point of the quantum circuit of overflow detection
is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Design and minimization of reversible programmable logic arrays and its reali...Sajib Mitra
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbage and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbage, quantum costs and delay.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Complex Adders and Parity Generators Using Reversible GatesIJLT EMAS
This paper shows efficient design of an odd and even parity generator, a 4-bit ripple carry adder, and a 2-bit carry look ahead adder using reversible gates. Number of reversible gates used, garbage output, and percentage usage of outputs in implementing each combinational circuit is derived. The CLA used 10 reversible gates with 14 garbage outputs, with 50% percentage performance usage.
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testab...VIT-AP University
The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss.
In this paper, parity preserving reversible binary-to-BCD code converter is
designed, and effect of reversible metrics is analyzed such as gate count, ancilla
input, garbage output, and quantum cost. This design can build blocks of basic
existing parity preserving reversible gates. The building blocks of the code converter
reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of
the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the
optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim
are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Similar to A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder (20)
‘Six Sigma Technique’ A Journey Through its Implementationijtsrd
The manufacturing industries all over the world are facing tough challenges for growth, development and sustainability in today’s competitive environment. They have to achieve apex position by adapting with the global competitive environment by delivering goods and services at low cost, prime quality and better price to increase wealth and consumer satisfaction. Cost Management ensures profit, growth and sustainability of the business with implementation of Continuous Improvement Technique like Six Sigma. This leads to optimize Business performance. The method drives for customer satisfaction, low variation, reduction in waste and cycle time resulting into a competitive advantage over other industries which did not implement it. The main objective of this paper ‘Six Sigma Technique A Journey Through Its Implementation’ is to conceptualize the effectiveness of Six Sigma Technique through the journey of its implementation. Aditi Sunilkumar Ghosalkar "‘Six Sigma Technique’: A Journey Through its Implementation" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64546.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64546/‘six-sigma-technique’-a-journey-through-its-implementation/aditi-sunilkumar-ghosalkar
Edge Computing in Space Enhancing Data Processing and Communication for Space...ijtsrd
Edge computing, a paradigm that involves processing data closer to its source, has gained significant attention for its potential to revolutionize data processing and communication in space missions. With the increasing complexity and data volume generated by modern space missions, traditional centralized computing approaches face challenges related to latency, bandwidth, and security. Edge computing in space, involving on board processing and analysis of data, offers promising solutions to these challenges. This paper explores the concept of edge computing in space, its benefits, applications, and future prospects in enhancing space missions. Manish Verma "Edge Computing in Space: Enhancing Data Processing and Communication for Space Missions" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64541.pdf Paper Url: https://www.ijtsrd.com/computer-science/artificial-intelligence/64541/edge-computing-in-space-enhancing-data-processing-and-communication-for-space-missions/manish-verma
Dynamics of Communal Politics in 21st Century India Challenges and Prospectsijtsrd
Communal politics in India has evolved through centuries, weaving a complex tapestry shaped by historical legacies, colonial influences, and contemporary socio political transformations. This research comprehensively examines the dynamics of communal politics in 21st century India, emphasizing its historical roots, socio political dynamics, economic implications, challenges, and prospects for mitigation. The historical perspective unravels the intricate interplay of religious identities and power dynamics from ancient civilizations to the impact of colonial rule, providing insights into the evolution of communalism. The socio political dynamics section delves into the contemporary manifestations, exploring the roles of identity politics, socio economic disparities, and globalization. The economic implications section highlights how communal politics intersects with economic issues, perpetuating disparities and influencing resource allocation. Challenges posed by communal politics are scrutinized, revealing multifaceted issues ranging from social fragmentation to threats against democratic values. The prospects for mitigation present a multifaceted approach, incorporating policy interventions, community engagement, and educational initiatives. The paper conducts a comparative analysis with international examples, identifying common patterns such as identity politics and economic disparities. It also examines unique challenges, emphasizing Indias diverse religious landscape, historical legacy, and secular framework. Lessons for effective strategies are drawn from international experiences, offering insights into inclusive policies, interfaith dialogue, media regulation, and global cooperation. By scrutinizing historical epochs, contemporary dynamics, economic implications, and international comparisons, this research provides a comprehensive understanding of communal politics in India. The proposed strategies for mitigation underscore the importance of a holistic approach to foster social harmony, inclusivity, and democratic values. Rose Hossain "Dynamics of Communal Politics in 21st Century India: Challenges and Prospects" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64528.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/history/64528/dynamics-of-communal-politics-in-21st-century-india-challenges-and-prospects/rose-hossain
Assess Perspective and Knowledge of Healthcare Providers Towards Elehealth in...ijtsrd
Background and Objective Telehealth has become a well known tool for the delivery of health care in Saudi Arabia, and the perspective and knowledge of healthcare providers are influential in the implementation, adoption and advancement of the method. This systematic review was conducted to examine the current literature base regarding telehealth and the related healthcare professional perspective and knowledge in the Kingdom of Saudi Arabia. Materials and Methods This systematic review was conducted by searching 7 databases including, MEDLINE, CINHAL, Web of Science, Scopus, PubMed, PsycINFO, and ProQuest Central. Studies on healthcare practitioners telehealth knowledge and perspectives published in English in Saudi Arabia from 2000 to 2023 were included. Boland directed this comprehensive review. The researchers examined each connected study using the AXIS tool, which evaluates cross sectional systematic reviews. Narrative synthesis was used to summarise and convey the data. Results Out of 1840 search results, 10 studies were included. Positive outlook and limited knowledge among providers were seen across trials. Healthcare professionals like telehealth for its ability to improve quality, access, and delivery, save time and money, and be successful. Age, gender, occupation, and work experience also affect health workers knowledge. In Saudi Arabia, healthcare professionals face inadequate expert assistance, patient privacy, internet connection concerns, lack of training courses, lack of telehealth understanding, and high costs while performing telemedicine. Conclusions Healthcare practitioners telehealth perceptions and knowledge were examined in this systematic study. Its collection of concerned experts different personal attitudes and expertise would help enhance telehealths implementation in Saudi Arabia, develop its healthcare delivery alternative, and eliminate frequent problems. Badriah Mousa I Mulayhi | Dr. Jomin George | Judy Jenkins "Assess Perspective and Knowledge of Healthcare Providers Towards Elehealth in Saudi Arabia: A Systematic Review" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64535.pdf Paper Url: https://www.ijtsrd.com/medicine/other/64535/assess-perspective-and-knowledge-of-healthcare-providers-towards-elehealth-in-saudi-arabia-a-systematic-review/badriah-mousa-i-mulayhi
The Impact of Digital Media on the Decentralization of Power and the Erosion ...ijtsrd
The impact of digital media on the distribution of power and the weakening of traditional gatekeepers has gained considerable attention in recent years. The adoption of digital technologies and the internet has resulted in declining influence and power for traditional gatekeepers such as publishing houses and news organizations. Simultaneously, digital media has facilitated the emergence of new voices and players in the media industry. Digital medias impact on power decentralization and gatekeeper erosion is visible in several ways. One significant aspect is the democratization of information, which enables anyone with an internet connection to publish and share content globally, leading to citizen journalism and bypassing traditional gatekeepers. Another aspect is the disruption of conventional media industry business models, as traditional organizations struggle to adjust to the decrease in advertising revenue and the rise of digital platforms. Alternative business models, such as subscription models and crowdfunding, have become more prevalent, leading to the emergence of new players. Overall, the impact of digital media on the distribution of power and the weakening of traditional gatekeepers has brought about significant changes in the media landscape and the way information is shared. Further research is required to fully comprehend the implications of these changes and their impact on society. Dr. Kusum Lata "The Impact of Digital Media on the Decentralization of Power and the Erosion of Traditional Gatekeepers" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64544.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/political-science/64544/the-impact-of-digital-media-on-the-decentralization-of-power-and-the-erosion-of-traditional-gatekeepers/dr-kusum-lata
Online Voices, Offline Impact Ambedkars Ideals and Socio Political Inclusion ...ijtsrd
This research investigates the nexus between online discussions on Dr. B.R. Ambedkars ideals and their impact on social inclusion among college students in Gurugram, Haryana. Surveying 240 students from 12 government colleges, findings indicate that 65 actively engage in online discussions, with 80 demonstrating moderate to high awareness of Ambedkars ideals. Statistically significant correlations reveal that higher online engagement correlates with increased awareness p 0.05 and perceived social inclusion. Variations across colleges and a notable effect of college type on perceived social inclusion highlight the influence of contextual factors. Furthermore, the intersectional analysis underscores nuanced differences based on gender, caste, and socio economic status. Dr. Kusum Lata "Online Voices, Offline Impact: Ambedkar's Ideals and Socio-Political Inclusion - A Study of Gurugram District" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64543.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/political-science/64543/online-voices-offline-impact-ambedkars-ideals-and-sociopolitical-inclusion--a-study-of-gurugram-district/dr-kusum-lata
Problems and Challenges of Agro Entreprenurship A Studyijtsrd
Noting calls for contextualizing Agro entrepreneurs problems and challenges of the agro entrepreneurs and for greater attention to the Role of entrepreneurs in agro entrepreneurship research, we conduct a systematic literature review of extent research in agriculture entrepreneurship to overcome the study objectives of complications of agro entrepreneurs through various factors, Development of agriculture products is a key factor for the overall economic growth of agro entrepreneurs Agro Entrepreneurs produces firsthand large scale employment, utilizes the labor and natural resources, This research outlines the problems of Weather and Soil Erosions, Market price fluctuation, stimulates labor cost problems, reduces concentration of Price volatility, Dependency on Intermediaries, induces Limited Bargaining Power, and Storage and Transportation Costs. This paper mainly devoted to highlight Problems and challenges faced for the sustainable of Agro Entrepreneurs in India. Vinay Prasad B "Problems and Challenges of Agro Entreprenurship - A Study" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64540.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64540/problems-and-challenges-of-agro-entreprenurship--a-study/vinay-prasad-b
Comparative Analysis of Total Corporate Disclosure of Selected IT Companies o...ijtsrd
Disclosure is a process through which a business enterprise communicates with external parties. A corporate disclosure is communication of financial and non financial information of the activities of a business enterprise to the interested entities. Corporate disclosure is done through publishing annual reports. So corporate disclosure through annual reports plays a vital role in the life of all the companies and provides valuable information to investors. The basic objectives of corporate disclosure is to give a true and fair view of companies to the parties related either directly or indirectly like owner, government, creditors, shareholders etc. in the companies act, provisions have been made about mandatory and voluntary disclosure. The IT sector in India is rapidly growing, the trend to invest in the IT sector is rising and employment opportunities in IT sectors are also increasing. Therefore the IT sector is expected to have fair, full and adequate disclosure of all information. Unfair and incomplete disclosure may adversely affect the entire economy. A research study on disclosure practices of IT companies could play an important role in this regard. Hence, the present research study has been done to study and review comparative analysis of total corporate disclosure of selected IT companies of India and to put forward overall findings and suggestions with a view to increase disclosure score of these companies. The researcher hopes that the present research study will be helpful to all selected Companies for improving level of corporate disclosure through annual reports as well as the government, creditors, investors, all business organizations and upcoming researcher for comparative analyses of level of corporate disclosure with special reference to selected IT companies. Dr. Vaibhavi D. Thaker "Comparative Analysis of Total Corporate Disclosure of Selected IT Companies of India" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64539.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64539/comparative-analysis-of-total-corporate-disclosure-of-selected-it-companies-of-india/dr-vaibhavi-d-thaker
The Impact of Educational Background and Professional Training on Human Right...ijtsrd
This study investigated the impact of educational background and professional training on human rights awareness among secondary school teachers in the Marathwada region of Maharashtra, India. The key findings reveal that higher levels of education, particularly a master’s degree, and fields of study related to education, humanities, or social sciences are associated with greater human rights awareness among teachers. Additionally, both pre service teacher training and in service professional development programs focused on human rights education significantly enhance teacher’s knowledge, skills, and competencies in promoting human rights principles in their classrooms. Baig Ameer Bee Mirza Abdul Aziz | Dr. Syed Azaz Ali Amjad Ali "The Impact of Educational Background and Professional Training on Human Rights Awareness among Secondary School Teachers" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64529.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/education/64529/the-impact-of-educational-background-and-professional-training-on-human-rights-awareness-among-secondary-school-teachers/baig-ameer-bee-mirza-abdul-aziz
A Study on the Effective Teaching Learning Process in English Curriculum at t...ijtsrd
“One Language sets you in a corridor for life. Two languages open every door along the way” Frank Smith English as a foreign language or as a second language has been ruling in India since the period of Lord Macaulay. But the question is how much we teach or learn English properly in our culture. Is there any scope to use English as a language rather than a subject How much we learn or teach English without any interference of mother language specially in the classroom teaching learning scenario in West Bengal By considering all these issues the researcher has attempted in this article to focus on the effective teaching learning process comparing to other traditional strategies in the field of English curriculum at the secondary level to investigate whether they fulfill the present teaching learning requirements or not by examining the validity of the present curriculum of English. The purpose of this study is to focus on the effectiveness of the systematic, scientific, sequential and logical transaction of the course between the teachers and the learners in the perspective of the 5Es programme that is engage, explore, explain, extend and evaluate. Sanchali Mondal | Santinath Sarkar "A Study on the Effective Teaching Learning Process in English Curriculum at the Secondary Level of West Bengal" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd62412.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/education/62412/a-study-on-the-effective-teaching-learning-process-in-english-curriculum-at-the-secondary-level-of-west-bengal/sanchali-mondal
The Role of Mentoring and Its Influence on the Effectiveness of the Teaching ...ijtsrd
This paper reports on a study which was conducted to investigate the role of mentoring and its influence on the effectiveness of the teaching of Physics in secondary schools in the South West Region of Cameroon. The study adopted the convergent parallel mixed methods design, focusing on respondents in secondary schools in the South West Region of Cameroon. Both quantitative and qualitative data were collected, analysed separately, and the results were compared to see if the findings confirm or disconfirm each other. The quantitative analysis found that majority of the respondents 72 of Physics teachers affirmed that they had more experienced colleagues as mentors to help build their confidence, improve their teaching, and help them improve their effectiveness and efficiency in guiding learners’ achievements. Only 28 of the respondents disagreed with these statements. With majority respondents 72 agreeing with the statements, it implies that in most secondary schools, experienced Physics teachers act as mentors to build teachers’ confidence in teaching and improving students’ learning. The interview qualitative data analysis summarized how secondary school Principals use meetings with mentors and mentees to promote mentorship in the school milieu. This has helped strengthen teachers’ classroom practices in secondary schools in the South West Region of Cameroon. With the results confirming each other, the study recommends that mentoring should focus on helping teachers employ social interactions and instructional practices feedback and clarity in teaching that have direct measurable impact on students’ learning achievements. Andrew Ngeim Sumba | Frederick Ebot Ashu | Peter Agborbechem Tambi "The Role of Mentoring and Its Influence on the Effectiveness of the Teaching of Physics in Secondary Schools in the South West Region of Cameroon" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64524.pdf Paper Url: https://www.ijtsrd.com/management/management-development/64524/the-role-of-mentoring-and-its-influence-on-the-effectiveness-of-the-teaching-of-physics-in-secondary-schools-in-the-south-west-region-of-cameroon/andrew-ngeim-sumba
Design Simulation and Hardware Construction of an Arduino Microcontroller Bas...ijtsrd
This study primarily focuses on the design of a high side buck converter using an Arduino microcontroller. The converter is specifically intended for use in DC DC applications, particularly in standalone solar PV systems where the PV output voltage exceeds the load or battery voltage. To evaluate the performance of the converter, simulation experiments are conducted using Proteus Software. These simulations provide insights into the input and output voltages, currents, powers, and efficiency under different state of charge SoC conditions of a 12V,70Ah rechargeable lead acid battery. Additionally, the hardware design of the converter is implemented, and practical data is collected through operation, monitoring, and recording. By comparing the simulation results with the practical results, the efficiency and performance of the designed converter are assessed. The findings indicate that while the buck converter is suitable for practical use in standalone PV systems, its efficiency is compromised due to a lower output current. Chan Myae Aung | Dr. Ei Mon "Design Simulation and Hardware Construction of an Arduino-Microcontroller Based DC-DC High-Side Buck Converter for Standalone PV System" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64518.pdf Paper Url: https://www.ijtsrd.com/engineering/mechanical-engineering/64518/design-simulation-and-hardware-construction-of-an-arduinomicrocontroller-based-dcdc-highside-buck-converter-for-standalone-pv-system/chan-myae-aung
Sustainable Energy by Paul A. Adekunte | Matthew N. O. Sadiku | Janet O. Sadikuijtsrd
Energy becomes sustainable if it meets the needs of the present without compromising the ability of future generations to meet their own needs. Some of the definitions of sustainable energy include the considerations of environmental aspects such as greenhouse gas emissions, social, and economic aspects such as energy poverty. Generally far more sustainable than fossil fuel are renewable energy sources such as wind, hydroelectric power, solar, and geothermal energy sources. Worthy of note is that some renewable energy projects, like the clearing of forests to produce biofuels, can cause severe environmental damage. The sustainability of nuclear power which is a low carbon source is highly debated because of concerns about radioactive waste, nuclear proliferation, and accidents. The switching from coal to natural gas has environmental benefits, including a lower climate impact, but could lead to delay in switching to more sustainable options. “Carbon capture and storage” can be built into power plants to remove the carbon dioxide CO2 emissions, but this technology is expensive and has rarely been implemented. Leading non renewable energy sources around the world is fossil fuels, coal, petroleum, and natural gas. Nuclear energy is usually considered another non renewable energy source, although nuclear energy itself is a renewable energy source, but the material used in nuclear power plants is not. The paper addresses the issue of sustainable energy, its attendant benefits to the future generation, and humanity in general. Paul A. Adekunte | Matthew N. O. Sadiku | Janet O. Sadiku "Sustainable Energy" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64534.pdf Paper Url: https://www.ijtsrd.com/engineering/electrical-engineering/64534/sustainable-energy/paul-a-adekunte
Concepts for Sudan Survey Act Implementations Executive Regulations and Stand...ijtsrd
This paper aims to outline the executive regulations, survey standards, and specifications required for the implementation of the Sudan Survey Act, and for regulating and organizing all surveying work activities in Sudan. The act has been discussed for more than 5 years. The Land Survey Act was initiated by the Sudan Survey Authority and all official legislations were headed by the Sudan Ministry of Justice till it was issued in 2022. The paper presents conceptual guidelines to be used for the Survey Act implementation and to regulate the survey work practice, standardizing the field surveys, processing, quality control, procedures, and the processes related to survey work carried out by the stakeholders and relevant authorities in Sudan. The conceptual guidelines are meant to improve the quality and harmonization of geospatial data and to aid decision making processes as well as geospatial information systems. The established comprehensive executive regulations will govern and regulate the implementation of the Sudan Survey Geomatics Act in all surveying and mapping practices undertaken by the Sudan Survey Authority SSA and state local survey departments for public or private sector organizations. The targeted standards and specifications include the reference frame, projection, coordinate systems, and the guidelines and specifications that must be followed in the field of survey work, processes, and mapping products. In the last few decades, there has been a growing awareness of the importance of geomatics activities and measurements on the Earths surface in space and time, together with observing and mapping the changes. In such cases, data must be captured promptly, standardized, and obtained with more accuracy and specified in much detail. The paper will also highlight the current situation in Sudan, the degree to which survey standards are used, the problems encountered, and the errors that arise from not using the standards and survey specifications. Kamal A. A. Sami "Concepts for Sudan Survey Act Implementations - Executive Regulations and Standards" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63484.pdf Paper Url: https://www.ijtsrd.com/engineering/civil-engineering/63484/concepts-for-sudan-survey-act-implementations--executive-regulations-and-standards/kamal-a-a-sami
Towards the Implementation of the Sudan Interpolated Geoid Model Khartoum Sta...ijtsrd
The discussions between ellipsoid and geoid have invoked many researchers during the recent decades, especially during the GNSS technology era, which had witnessed a great deal of development but still geoid undulation requires more investigations. To figure out a solution for Sudans local geoid, this research has tried to intake the possibility of determining the geoid model by following two approaches, gravimetric and geometrical geoid model determination, by making use of GNSS leveling benchmarks at Khartoum state. The Benchmarks are well distributed in the study area, in which, the horizontal coordinates and the height above the ellipsoid have been observed by GNSS while orthometric heights were carried out using precise leveling. The Global Geopotential Model GGM represented in EGM2008 has been exploited to figure out the geoid undulation at the benchmarks in the study area. This is followed by a fitting process, that has been done to suit the geoid undulation data which has been computed using GNSS leveling data and geoid undulation inspired by the EGM2008. Two geoid surfaces were created after the fitting process to ensure that they are identical and both of them could be counted for getting the same geoid undulation with an acceptable accuracy. In this respect, statistical operation played an important role in ensuring the consistency and integrity of the model by applying cross validation techniques splitting the data into training and testing datasets for building the geoid model and testing its eligibility. The geometrical solution for geoid undulation computation has been utilized by applying straightforward equations that facilitate the calculation of the geoid undulation directly through applying statistical techniques for the GNSS leveling data of the study area to get the common equation parameters values that could be utilized to calculate geoid undulation of any position in the study area within the claimed accuracy. Both systems were checked and proved eligible to be used within the study area with acceptable accuracy which may contribute to solving the geoid undulation problem in the Khartoum area, and be further generalized to determine the geoid model over the entire country, and this could be considered in the future, for regional and continental geoid model. Ahmed M. A. Mohammed. | Kamal A. A. Sami "Towards the Implementation of the Sudan Interpolated Geoid Model (Khartoum State Case Study)" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63483.pdf Paper Url: https://www.ijtsrd.com/engineering/civil-engineering/63483/towards-the-implementation-of-the-sudan-interpolated-geoid-model-khartoum-state-case-study/ahmed-m-a-mohammed
Activating Geospatial Information for Sudans Sustainable Investment Mapijtsrd
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A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder
1. ISSN No: 2456 -
International
Research
A Novel Design of a four bit Reversible ALU using
an emphasized Carry Look
Swetha Potharla
M.Tech , Dept. of ECE, CITS Warangal.
ABSTRACT
Reversible circuits are one promising direction
with applications in the field of low
design or quantum computation. However, no
real design flow for this new kind of circuits exists
so far. Significant contributions have been made
in the literature towards the design of reversible
logic gate structures and arithmetic units,
however, there are not many efforts directed
towards the design of reversible ALUs. In this
paper, a novel programmable reversible Kogge
Stone adder is presented and verified, and its
implementation in the design of a
Arithmetic Logic Unit is demonstrated. Then,
reversible implementations of ripple
Kogge-Stone carry look-ahead adders are
analyzed and compared in terms of delay. The
proposed design consists of the reversible Fredkin,
Feynman, MG, HNG, PG and RKSC gates. The
performance characteristics analysis is carried out
in Xilinx environment.
Keywords: Arithmetic Logic Unit, Carry Look
Ahead Adder, Emerging Technologies, Low
Power, Nanotechnology, Reversible Logic,
Ripple-Carry Adder
I. INTRODUCTION
In reversible logic there exists a one to on
mapping between the inputs and the outputs
vectors. In an irreversible circuit erasing a bit is
equivalent to dissipation of kTln2 joules of heat
energy where k is the Boltzmann’s constant and T
is the absolute temperature of environment which
is demonstrated by Landauer [1]. This resulting
dissipated heat also causes noise in the remaining
circuitry, which results in computing errors.
Bennett showed that the dissipated energy directly
correlated to the number of lost bits, and that
computers can be logically reversible, maintain
- 6470 | www.ijtsrd.com | Volume -
International Journal of Trend in Scientific
Research and Development (IJTSRD)
International Open Access Journal
A Novel Design of a four bit Reversible ALU using
an emphasized Carry Look-ahead Adder
CITS Warangal.
Subhash. R R. Rajkumar
Asst. Prof., Warangal , Telangana
ing direction
of low-power
design or quantum computation. However, no
real design flow for this new kind of circuits exists
so far. Significant contributions have been made
in the literature towards the design of reversible
logic gate structures and arithmetic units,
er, there are not many efforts directed
towards the design of reversible ALUs. In this
paper, a novel programmable reversible Kogge-
Stone adder is presented and verified, and its
lementation in the design of a reversible
trated. Then,
reversible implementations of ripple-carry,
ahead adders are
analyzed and compared in terms of delay. The
proposed design consists of the reversible Fredkin,
Feynman, MG, HNG, PG and RKSC gates. The
ristics analysis is carried out
Arithmetic Logic Unit, Carry Look-
Ahead Adder, Emerging Technologies, Low
Power, Nanotechnology, Reversible Logic,
one to one
mapping between the inputs and the outputs
vectors. In an irreversible circuit erasing a bit is
equivalent to dissipation of kTln2 joules of heat
energy where k is the Boltzmann’s constant and T
is the absolute temperature of environment which
rated by Landauer [1]. This resulting
dissipated heat also causes noise in the remaining
circuitry, which results in computing errors.
Bennett showed that the dissipated energy directly
correlated to the number of lost bits, and that
be logically reversible, maintain
their simplicity and provide accurate calculations
at practical speeds [2]. Resultantly, a new paradigm
in computer design arose with the goal of reducing
the entropy increase and subsequent energy
dissipation. Such a logical structure must possess the
same number of inputs and outputs and a one
mapping between the input and output states. Any
device designed to these constraints is known as a
reversible logic device.
Section II, we outline the goals of programmable
reversible logic design and some
gates. In Section III, a novel 5*5 programmable MG
gate is proposed that may be utilized in an
arithmetic logic unit requiring the calculation of
AND, NAND, OR, NOR, XOR and XNOR results.
In Section IV, previous work in prog
reversible arithmetic logic units is reviewed, and
the proposed MG gate is implemented in the design
of a novel programmable arithmetic logic unit.
adder designs are presented for ripple kogge
adder.
In Section VI, a reversible implementation of the
carry logic presented in the Kogge
and verified. In section VII, a 4
implemented with ripple carry and kogge
adders and these designs are functionally verified
and compared in terms of delay.
II. REVERSIBLE LOGIC
A. Programmable Reversible Design Goals
The three major design goals of reversible logic are
as follows. First, minimization of the quantum
cost – the number of 1*1 and 2*2 reversible
calculations necessary to generate the logical
output [6] will reduce the device’s computational
complexity. Second, minimization of the delay
the logical depth of the device [7] will improve the
- 1 | Issue – 6
Scientific
(IJTSRD)
International Open Access Journal
A Novel Design of a four bit Reversible ALU using
dder
R. Rajkumar
Warangal , Telangana, India.
simplicity and provide accurate calculations
at practical speeds [2]. Resultantly, a new paradigm
in computer design arose with the goal of reducing
the entropy increase and subsequent energy
dissipation. Such a logical structure must possess the
me number of inputs and outputs and a one-to one
mapping between the input and output states. Any
device designed to these constraints is known as a
Section II, we outline the goals of programmable
reversible logic design and some fundamental logic
gates. In Section III, a novel 5*5 programmable MG
gate is proposed that may be utilized in an
arithmetic logic unit requiring the calculation of
AND, NAND, OR, NOR, XOR and XNOR results.
In Section IV, previous work in programmable
reversible arithmetic logic units is reviewed, and
the proposed MG gate is implemented in the design
of a novel programmable arithmetic logic unit. In
presented for ripple kogge-stone
implementation of the
carry logic presented in the Kogge-Stone is proposed
and verified. In section VII, a 4-bit ALU is
implemented with ripple carry and kogge-stone
adders and these designs are functionally verified
A. Programmable Reversible Design Goals
The three major design goals of reversible logic are
as follows. First, minimization of the quantum
the number of 1*1 and 2*2 reversible
calculations necessary to generate the logical
output [6] will reduce the device’s computational
minimization of the delay -
the logical depth of the device [7] will improve the
2. International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
ancillary inputs and garbage outputs - inputs
and outputs not implemented in the design of the
gate and only serve to maintain reversibility of the
device will improve the design space require to
implement the logic.
A programmable reversible logic gate is defined
in [8] as a logic structure which possesses a
bijection between input and output states and an
equal number of inputs and outputs wherein a
subset of the inputs are fixed select lines, and a
fixed subset of the outputs produce guaranteed
logical calculations. An ideal programmable
reversible logic gate with j inputs and outputs has
a quantity of fixed select inputs m, fixed select
outputs n, data inputs d and propagated outputs p
such that |d-p|=|m-n| [8]. In addition, an ideal
programmable reversible logic gate with m select
inputs may produce at maximum n*2^m logical
calculations on the n logical outputs.
B. Fundamental Logic Gates
There are three types of fundamental 2*2
reversible logic gates. First, the square-root-of-not
gates utilize the unitary operators to produce
reversible logic calculations. The Controlled-V
and the Controlled-V+ gates are the two types of
square-root-of-not gates. In both of these gates,
when the control input is 0, the second input is
propagated to the output. The same holds for two
Controlled-V+ gates in series.
When a Controlled-V and Controlled-V+ gate are
activated in series, they act as an identity.
The second type of fundamental 2*2 reversible-
logic gate is the Feynman gate, or the Controlled-
Not gate. Proposed in [9] by Feynman, it is
configured such that its outputs states correlate to
the input states in the following manner: P=A and
Q=A B. The resulting value of the second output
corresponds to the result of a conventional XOR
gate. Since fanout is expressively forbidden in
reversible logic, since a fanout has one input and
two outputs, the Feynman gate may be used to
duplicate a signal when B is equal to 0. Its
quantum configuration is shown in Fig 2.
Fig 1: Quantum Representation of Feynman
gate
The third type of fundamental 2*2 reversible logic
gate is the integrated qubit gate. This gate is
implemented with a Feynman gate with either a
Controlled-V or Controlled V+ gate. The XOR
output of the Feynman gate is used as the control
signal for the Controlled-V or V+ gate it is coupled
with. The quantum cost of the integrated qubit gate
is 1 and its worst-case delay is 1. The quantum
configurations of these gates are shown below in
Fig. 3.
Fig 2: Quantum Representations of Integrated
Qubit Gates
The 3*3 Peres gate was proposed by Peres in [12].
The Peres gate has a quantum cost of 4 and a worst-
case delay of 3. The quantum representation is
shown in Fig. 6. The output states map to the inputs
in this manner: P=A, Q=A B and R=AB C.
There are three 3*3 fundamental reversible logic
gates. The first was proposed in [10] by Fredkin and
Toffoli. The Fredkin gate’s outputs states map to the
inputs as follows:
P=A, Q=A B AC and R=AB A C.
Therefore, the outputs serve as a multiplexed output
of the two data inputs based on the control input. It is
realized using 2 Feynman gates, a Controlled-V gate
and two integrated qubit gates.
Toffoli proposed the second fundamental 3*3
reversible logic gate in [11]. The output states of the
Toffoli gate map to the inputs in this manner: P=A,
Q=B and R=AB C. The quantum cost is 5 and the
worst-case delay is 5. The quantum representation is
shown below in Fig. 5.
Fig 3: Quantum Representation of Fredkin gate
Fig 4: Quantum Representation of Toffoli gate
3. International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
The 3*3 Peres gate was proposed by Peres in [12].
The Peres gate has a quantum cost of 4 and a
worst-case delay of 3. The quantum representation
is shown in Fig. 6. The output states map to the
inputs in this manner: P=A, Q=A B and R=AB
C.
Fig 5: Quantum Representation of Peres gate
The HNG gate, also designed by Hagparast and
Navi and proposed in [13], is a full adder with
inputs A,B,C,D producing outputs P=A, Q=B,
R=(A B) C and S=(A B)C (AB D) and is
shown in Fig. 6.
Fig. 6: Hagparast-Navi (HNG) Gate
The Peres And-Or (PAOG) gate, proposed in [8],
produces the outputs P = A, Q =A B, R=AB
C and S=(AB C) ((A B) D). Fig. 7
shows the quantum representation of the PAOG
gate. This gate is an extension of the Peres gate
for ALU realization. When the PAOG is utilized
as a programmable reversible logic gate with two
select inputs, it will calculate four logical
calculations on those two logical outputs: AND,
NAND, NOR and OR.
The Morrison-Ranganathan (MRG) gate,
proposed in [8], has a quantum cost of 6, since it
consists of three XOR gates, 2 Controller-V and
one Controller-V+ gate. The worst-case delay of
the MRG gate is 6. The quantum representation of
the MRG gate is shown in Fig. 8 below. When the
MRG is utilized as a programmable reversible
logic gate with two select inputs, it will calculate
four logical calculations on those two logical
Fig. 8: Quantum Representation of the MRG Gate
III. PROPOSED 5*5 PROGRAMMABLE
REVERSIBLE MG GATE
Next, we propose the design of a 5*5 programmable
reversible logic gate structure utilized in the
implementation of an ALU. Fig. 9 shows the block
diagram of the MG, and the logical calculations
based on the programmable inputs are presented in
Table 2. The cost of the MG is 7, and the worst-case
delay is 7. The design for the programmable MG
was verified and simulated using VHDL in Xilinx.
Fig 9: Quantum Representation of Proposed MG.
TABLE II
Mg Programmable Inputs And Logical Outputs
C D E R S T
0 0 0 A B AB A+B
0 0 1 A B AB (A+B)'
0 1 0 A B (AB)' (A+B)'
0 1 1 A B (AB)' A+B
1 0 0 A B AB A+B
1 0 1 A B AB (A+B)'
1 1 0 A B (AB)' (A+B)'
1 1 1 A B (AB)' A+B
IV. MODIFIED ALU DESIGN WITH MG
GATE
Two 1-bit ALUs were proposed in [8]. The first
utilizes the MRG gate and HNG gate to produce six
logical calculations: ADD, SUB, XOR, XNOR, OR
and NOR. The ALU has 8 inputs and 8 outputs. The
inputs consist of three data inputs (A, B and Cin) and
five fixed input select lines. The eight outputs are: A,
S0, S3 and S4 propagated to the output, A B,
SUM, Cout, Overflow and Result. The cost of this 1-
bit ALU is 24, and the worst-case delay is 16. For n
bit ALU devices, an addition cost of 2 is incurred per
bit in order to propagate S1 and S2 to other bits.
4. International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
The MG gate is utilized in the implementation of a
novel arithmetic logic unit based on those
proposed in [8]. The ALU, in addition to
producing the same logical calculations as the
MG, is able to perform addition and subtraction
by utilizing the HNG gate and store less-than
operation. The cost an n-bit ALU is 37n-3 and had
a worst case delay of 4n+13. The proposed ALU
is shown in Fig. 10
V. BASIC ADDER DESIGNS
The adders implemented are the ripple carry adder
and Kogge-Stone adder. The ripple carry adder is
one of the simplest adders. It consists of a
cascaded series of full adders. The 4-bit ALU
implemented by cascading four 1-bit ALUs. The
delay for an N-bit adder is given by
tadder = (N-1)tcarry + tsum
where, tcarry is the carry propagation delay for one
stage and tsum is the time required to compute the
sum bit for one stage.
The Kogge-Stone adder is classified as a parallel
prefix adder since the generate and the propagate
signals are pre computed. In a tree-based adder,
carries are generated in tree and fast computation
is obtained at the expense of increased area and
power. The parallel-prefix adder becomes more
favorable in terms of speed due to the O(log2n)
delay through the carry path compared to O(n) for
the RCA.
Fig.11. 4-bit Kogge-Stone Adder
The 4-bit Kogge-Stone adder is built from
generate and propagate (GP) blocks, black cell
(BC) blocks, and buffer blocks as shown in the
Figure 11. The expressions for the output signals
g,p generated by the black cell are given by g =
gi+pi gj and p = pi pj. The expressions for the
output signals g, p obtained by the buffer block
are given as g=gi and p=pi .
The expressions for the output signals g, p
obtained by the GP block are given as g=a.b and
p=a xor b.
Reversible Kogge-Stone Cumulate Logic
A reversible carry look-ahead adder based on the
Kogge-Stone adder is presented [9]. First, a RKS
Cumulate utilized in the calculation of the carry out
signal is designed and verified. The logical structure
of the RKSC is shown in Fig. 12. The cost of the
RKSC is 14 and it has a worst-case delay of 4.
VI. IMPLEMENTATION OF REVERSIBLE
KOGGE-STONEADDER
A reversible Kogge-Stone adder is implemented by
using Peres gate as GP block, Feynman gate as
Buffer block and RKSC gate as BC block as shown
in Fig.13. The design was verified and simulated
using VHDL in Xilinx 9.2i.
Fig. 12: Reversible Kogge-Stone Cumulate (RKSC)
Logical Layout
VII. IMPLEMENTATION OF REVERSIBLE
KOGGE-STONE ADDER
A reversible Kogge-Stone adder is implemented by
using Peres gate as GP block, Feynman gate as
Buffer block and RKSC gate as BC block as shown
in Fig.13. The design was verified and simulated
using VHDL in Xilinx 9.2i.
Fig 13: 4-bit Reversible Kogge-Stone adder ALU
Design with Reversible Kogge-Stone adder
The 4-bit ALU was implemented using reversible
Kogge-Stone adder as shown in Fig.14. This design
was verified and simulated using VHDL in
Xilinx9.2i.
5. International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
VIII. COMPARISION AND RESULTS
The comparison is carried out in between the
reversible Ripple Carry and Kogge-Stone adders
with respect to 4-bit ALU design and for those the
code was written in VHDL and that was verified
and simulated using Xilinx 9.2i.
TABLE IV
Comparison of ALUs of ripple carry and
kogge-stone adders
Parameter 4-bit ALU
with
4-bit ALU
with
ripple carry
adder
kogge-stone
adder
Delay(ns) 16.856 15.536
LUT’s 37 31
Fig.14. 4-bit reversible ALU with kogge-stone
adder
Fig.15. 1-bit reversible ALU
Fig.16. 4-bit reversible kogge-stone adder
Fig.17. 4-bit reversible ALU with ripple carry
adder
Fig.18. 4-bit reversible ALU with kogge-stone
adder
IX. CONCLUSION
A novel 5*5 programmable MG gate was proposed
and verified that may calculate of AND, NAND,
OR, NOR, XOR and XNOR depending on the inputs
from the programmer. The proposed MG gate was
implemented in the design of a novel programmable
arithmetic logic unit. The novel 1-bit ALU required
only minimal increase in quantum cost and delay due
to the MG design, which also allowed for increased
functionality for the programmer.
Next, we presented reversible implementations of
ripple carry adder (RCA) and kogge-stone adder. A
eversible implementation of the carry logic presented
in the Kogge tone was presented and verified. The
proposed design of 4-bit ALU with RCA and Kogge-
Stone adder were compared in terms of delay.
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