The document describes the implementation of Booth's multiplication algorithm using a reversible circuit. It begins with an overview of Booth's multiplication and how it can speed up multiplication by replacing sequences of additions with subtraction. It then discusses how the multiplier and multiplicand are recoded, followed by a step-by-step explanation of how the algorithm works using an example. It compares the performance of Booth's multiplication to normal addition-based multiplication. The document concludes by providing block diagrams of the conventional logic implementation and the proposed reversible circuit implementation, including details of the internal blocks used such as reversible gates.

1. Booth’s Multiplication implemented in Reversible circuit
Rohith
Rohith
Rahul Krishnamurthy
Roll No. 2011VLSI12
Roll No. 2011VLSI06
Under the Guidance of
Prof. G.K.Sharma
April 20, 2012
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2. What and Why?
Rohith
Whenever there are a large number of consecutive 1’s in multiplier,
multiplication can be speeded up by replacing the corresponding
sequence of addition with subtraction at least significant end and an
addition in the position immediately to the left of its most significant
end.
2J + 2J−1 + 2J−2 + ... + 2K = 2J+1 − 2K
Example: 0111 = 1000 - 0001
Booth exploits this to create a faster multiplier
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3. Recoding
Representation of Signed number (A) is
val (A) = [−an−1 x2n−1 + n−2 (ai x2i )]
0
For example(10)10 = (1010)2
2’s Complement of 10 is 0110.The value of (-10) becomes 10110
VAL(-10) from the formulae is −1x24 + 1x22 + 1x21 = (−10)10
Bxval (A) =
Yi
Yi−1
Xi
0
0
Explanation
0
1
0
1
1
0
−1
End of string of 1s in x
Beginning of string of 1s in x
1
1
0
Continuation of string of 1s in X
No string 1s in sight
(a−1 − a0 )xBx20 + (a0 − a1 )xBx21 + (a2 − a1 )xBx22 + (a3 − a2 )xBx23 +
...(an−2 − an−1 )xBx2n−1
Bx[−an−1 x2n−1 +
Rohith
n−2
i
0 (ai x2 )]
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4. WORKING
STEP 1
Multiplier is recoded into Booth’s recoded form using the conversion
truth table.We will take X−1 = 0. For example
A is 11000
B is 10101
recoded Y becomes -11-11-1
STEP 2
Rohith
Use the recoded version of multiplier and perform the right shift
multiplication algorithm to get the product
Multiplicand(A) 11000
Multiplier(Y) -11-11-1
Partial product is intialized to 0
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5. WORKING contd..
Rohith
Y is scanned from right to left
a) If Y=-1 then
Calculate 2’s complement of the multiplicand and add with the
existing partial product.
Perform the right shift of the obtained partial product.
We have to preserve the sign of the partial product so the bit
enetring the MSB is same as the previous MSB
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6. WORKING contd..
Rohith
b) If Y=1 then
Add the multiplicand with the existing partial product.
Perform the right shift of the obtained partial product.
We have to preserve the sign of the partial product so the bit
enetring the MSB is same as the previous MSB
c) If Y=0 then
Perform the right shift of the obtained partial product.
We have to preserve the sign of the partial product so the bit
enetring the MSB is same as the previous MSB
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7. Example
Below example we have taken Multiplicand as -8 And Multilplier as
-11 and recoded form of Multilplier is -1 1 -1 1 -1
A
1
Y
−1 1
1
0
−1 1
0
−1
0
P
0
0
0
0
0
AY
0
1
0
0
0
2P 0
0
1
0
0
0
P
0
0
1
0
0
AY
1
1
0
0
0
0
2P 1
1
1
1
0
0
0
P
1
1
1
1
0
0
AY
0
1
0
0
0
2P 0
0
0
1
1
0
0
0
P
0
0
0
1
1
0
0
AY
1
1
0
0
0
0
0
2P 1
1
1
0
1
1
0
0
0
P
1
1
1
0
1
1
0
0
0
AY
0
0
0
2P 0
0
0
1
1
0
0
0
1
0
0
1
Result of the multiplication is 88 represented by 0001011000
Rohith
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8. Comparision
Rohith
In normal add and shift algorithms number of additions and shifting
depends on multiplier bits.For example
If the Multiplier is 1111 then
we require 4 addition and shifting operation
In Booth’s multiplication for the same multiplier we require
1 addition and 4 Shifting operations
Shifting alone takes less time than both shifting and addition.
This makes multiplication faster than normal add and shift algorithms.
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9. BLOCK DIAGRAM CONVENTIONAL LOGIC
Rohith
PARTIAL PRODUCT(P)
5−BIT
full
adder
UPDATE
PARTIAL
PRODUCT
SHIFT REGISTER
(8 DOWNTO 0)<=(9 DOWN TO 1)
0000
MULIPLICAND
MUX FOR SELECTING MULTIPLICAND
2’S COMP
0000
X(I)
X(I−1)
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10. VHDL SIMULATION
Rohith
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11. BASIC REVERSIBLE GATES
Rohith
FEYNMAN GATE
TOFFOLI GATE
PERES GATE
FREDKIN GATE
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12. Feynman GATE
Feynman GATE
Rohith
It is a 2x2 reversible gate.
Quantum cost is 1
It has a unit delay
A
B
P=A
FG
Q=A
A
B
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B
P=A
Q=A
B
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13. TOFFOLI GATE
TOFFOLI GATE
Rohith
It is a 3x3 reversible gate
Quantum cost is 5
Delay is 5△
A
P=A
Q=B
TG
B
Q=A.B C
C
1
2
3
4
5
A
P=A
B
Q=B
C
V
V
V+
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R=A.B C
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14. FREDKIN GATE
FREDKIN GATE
Rohith
It is a 3x3 reversible gate
Quantum cost is 5
Delay is 5△
A
P=A
B
Q=AB+AC
F
R=A.B+AC
C
Fredkin Gate
1
2
3
4
5
A
B
P=A
V+
V
C
V
Q=AB+AC
R=A.B+AC
Delay of Fredkin Gate
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15. PERES GATE
PERES GATE
Rohith
It is a 3x3 reversible gate
Quantum cost is 4
Delay is 4△
A
P=A
Q=A B
PG
B
Q=A.B C
C
1
2
3
4
A
P=A
B
Q=A B
C
V+
V
+
V
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R=A.B C
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16. BLOCK DIAGRAM OF REVERSIBLE BOOTH
MULTIPLIER
Rohith
X is a 4 bit Multiplicand
Y is a 4 bit Multiplier
Z is a 8 bit product of X and Y.
X(3:0)
BOOTH’S
Z(7:0)
MULTIPLIER
Y(3:0)
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17. Internal Block diagram
STAGE 2
X0
X3
STAGE 4
STAGE 3
2’S
COMPLIMENT
X0
2’S
COMPLIMENT
STAGE 1
Y
Y i−1
i
P4
HA
STAGE 5
S0
P7
FG
FG
P7
0
0
C0
X i or 2’S OF Xi
or 0
P
5
FA
X3
S1
C1
FG
Yi
0
0
0
Y i−1
P
6
FA
P7
P6
REVERSIBLE SHIFTER
0
4:1
MUX
S2
P
5
P4
P3
P2
P1
P
FG
1
C2
4:1
MUX
FA
P0
S3
P
7
P
1
P3
INTERNAL BLOCK REPRESENTATION
FG stands for Feynman Gate.
Rohith
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18. Working of Internal Block diagram
Stage 1
This stage comprises of 4 Feynman gates in order to get
a copy of each bit of Multiplicand.
The first output of each feynman gate goes to
2’s Complement block and then the output
of 2’s complement block goes to each multiplexer block.
The second output of feynman gate goes directly
to Multiplexer block.
stage 1 quantum cost :4 and Garbage output :0
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19. Working of Internal Block diagram Contd..
Stage 2
Computing 2’s Complement of the multiplicand.
Rohith
First compute 1’s Complement of each bit of Multiplicand
4 Not gates are used to perform this operation
Then add 1 to the LSB bit of 1’s Complement using half adder and
propagate carry to subsequent half adders.
1 Peres gate is used to perform the half adder operation.
4 Peres gates are used to get the 2’s complement.
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20. 2’s Complement
1
A0
PG
OUTPUT BIT 0
0
C0
A1
0
PG
OUTPUT BIT 1
C1
A2
PG
OUTPUT BIT 2
0
C2
A3
FG
OUTPUT BIT 3
2’S COMPLEMENT OF A
stage 2 quantum cost :17 and Garbage output :4
Rohith
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21. Working of Internal Block diagram Contd..
Stage 3
Multiplexer
Rohith
Yi
Yi−1
Xi
0
0
0
1
0
1
1
0
−1
End of string of 1s in x
Beginning of string of 1s in x
1
1
0
Continuation of string of 1s in X
Explanation
No string 1s in sight
In the truth table depending on the Yi Yi-1 we are sending modified
form of multiplicand to the adder block
If Yi=0 and Yi-1=0
If Yi=0 and Yi-1=1
If Yi=1 and Yi-1=0
adder block.
If Yi=1 and Yi-1=1
then send 0000 to the adder block.
then send muliplican as it is to the adder block.
then send 2’s complement of mulitiplicand to the
then send 0000 to the adder block.
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22. Working of Internal Block diagram Contd..
Stage 3
Multiplexer contd..
To select one of the above as an input to the adder block we are
using 4:1 multiplexer.
This 4:1 multiplexer is performed using three 2:1 multiplexer.
each 2:1 multiplexer is implemented using Fredkin gate.
Yi
Xi
0
2:1 mux
using
fredkin
gate
Yi−1
Yi
0
2’s comp of X
i
2:1 mux
using
fredkin
gate
2:1 mux
using
fredkin
gate
4:1 mux using fredkin gate
stage 3 quantum cost :60 and and Garbage output :20
Rohith
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23. Working of Internal Block diagram Contd..
Stage 4
Full Adder and Half Adder
To add the output of multiplexer block and 4 MSB bit’s of partial
product we need one half adder and 3 full adders.
for half adder we used PERES GATE and for full adder we used HNG
GATE.
A
A
B
C
PERES
GATE
A
A
A B
B
B
C
C
AB
HNG
GATE
A
D
HALF ADDER
B
(A B)
C
C
AB D
FULL ADDER
stage 4 quantum cost :22 and and Garbage output :7
Rohith
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24. Parallel Input Parallel Output shifter
Stage 5
PIPO Shifter
Shifter performs the arithmetic right shift operation on the
partial product generated after the addition operation.
1
X2
1
FREDKIN
GATE
1
X3
FREDKIN
GATE
1
X4
FREDKIN
GATE
1
X5
FREDKIN
GATE
1
X6
FREDKIN
GATE
X7
FREDKIN
GATE
1
X6
FREDKIN
GATE
X7
0
FEYNMAN GATE
Shifter is implemented using 7 Fredkin gate and
1 Feynman gate.
X1
1
0
X5
0
X4
X3
X2
X1
X7
X7
7TH BIT
6TH BIT
X6
5TH BIT
X5
4TH BIT
X4
3RD BIT
X2
X3
2ND BIT
X1
1ST BIT
0TH BIT
stage 5 quantum cost :36 and and Garbage output :2
Rohith
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25. Comparision
Reversible Multiplier
Our Design
(Haghparast et al., 2009)(Design 1)
(Haghparast et al., 2009)(Design 2)
(Haghparast et al., 2008)
(Shams et al., 2008)
(Thaplyal and Srinivas, 2006)
(Thaplyal et al., 2005)
Rohith
Total Quantum Cost
146
137
Garbage outputs
33
28
153
28
152
244
286
236
52
56
58
56
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26. CONCLUSION
Rohith
′
Good for sequences of 3 or more 1 s
Replaces 3 adds with 1 add and 1 subtract.For Example
Multilplier is 1 0 1 1 1
In Booth algorithm the multiplier reduces to the form
-1 1 0 0 -1
This requires 3 additions as oppose 4 addition in normal
multiplier
Quantum Cost of Reversible design is 146
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27. References
1.Computer Arithmetic - Algorithms and Hardware designs by
Behrooz Parhami
2. Design of a Nanometric Fault Tolerant Reversible Multiplier
Circuit J. Basic. Appl. Sci. Res., 2(2)1355-1361, 2012 by Somayeh
Babazadeh and Majid Haghparast,
Rohith
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28. Thank you
Rohith
Thank You
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