This document describes the design of high-performance 8-bit, 16-bit, and 32-bit Vedic multipliers using SCL PDK 180nm technology. It discusses the need for fast low-power multipliers in applications like DSP. Vedic multiplication algorithms and architectures for proposed multipliers are presented. Performance analysis shows post-layout propagation delays of 1.4ns, 3.6ns, and not reported for 8-bit, 16-bit, and 32-bit multipliers respectively. Power dissipation is also reported. Hardware implementation including padring is discussed and layout shown occupying 1.89mm2.

1. DESIGN OF HIGH PERFORMANCE
8,16,32-BIT VEDIC MULTIPLIERS
USING SCL PDK 180NM
TECHNOLOGY
Supervised By:
Dr. Anil K. Gupta
Co-ordinator of School
of VLSI Design and
Embedded Systems
Submitted By:
Yogendri
Roll No - 3142506

2. CONTENTS
1. INTRODUCTION
2. NEED OF MULTIPLIERS
3. VEDIC ALGORITHM
4. FULL ADDER
5. PROPOSED 8,16,32-BIT VEDIC MULTIPLIERS
6. PERFORMANCE ANALYSIS
7. HARDWARE IMPLEMENTATION
8. CONCLUSION
9. REFERENCES

3. INTRODUCTION
 Multiplier is an essential functional block of a microprocessor because
multiplication is needed to be performed repeatedly in almost all scientific
calculations.
 The fast and low power multipliers are required in small size wireless sensor
networks and many other DSP (Digital Signal Processing) applications. They
are also used in many algorithms such as FFT(Fast Fourier transform),
DFT(Discrete Fourier Transform)
 There are two basic multiplication methods namely Booth multiplication
algorithm and Array multiplication algorithm used for the design of multipliers.
 The schemes for efficient addition of partial products are Wallace tree [1];
Dadda tree [2]. The speed of multiplication (as well as power dissipation) is
dominantly controlled by the propagation delay of the full / half adders used for
the addition of partial products

4. TOOLS USED
 Cadence EDA
 Technology – SCL PDK 180nm
 Simulator – Hspice
 For DRC, LVS and PEX - Calibre

5. VEDIC ALGORITHM
Vedic multiplication method is described by Urdhva-tiryakbyham sutra of
Vedic arithmetic.
Fig. 1. 16X16 multiplication using UT sutra [3]
• Partial product generation
consists of vertically and
crosswise operations.
• Partial product
generations and additions
are carried out in parallel

6. BLOCK DIAGRAM OF (m)X(m) BINARY MULTIPLIER
(m/2)x(m/2) (m/2)x(m/2)
(m/2)x(m/2)(m/2)x(m/2)
k-bit Adder Block
Fig. 2. m x m multiplication using UT sutra [3]
2m
• For (m x m) multiplier, 4 numbers of
(m/2) x (m/2) multipliers are required.
• The first reduction layer requires ‘m’
full adders and second reduction stage
requires a k-bit binary adder (k is
equal to [(3/2) m-1] where m is the
number of bits in the operands)

7. FULLADDER
FEATURES OF FULL ADDER
1. It uses minimum area transistors (360n/180n for pMOS and 240n/180n
for nMOS is used in this work)
2. It should have equal delay from i/p to both the outputs i.e. Carry and
Sum due to which glitches are minimum
3. It has very compact layout.
These features of FA provides for carry skip operation.
A
C
B
Sum
Carry

8. SCHEMATIC OF FULLADDER

9. LAYOUT OF FULLADDER

10. TABLE 1
PROPAGATION DELAY OF FULL ADDER FOR THE PRE
LAYOUT AND POST LAYOUT SIMULATION
The power dissipation of FA was evaluated at the switching frequency of 500MHz. The
average power consumption was determined to be 55µW for pre layout simulation and 72
µW for post layout simulation i.e. with parasitics.
Full Adder Pre layout (ps) Post Layout (ps)
Min. Max. Min. Max.
A to Sum 177.1 268 237.5 401
A to Cout 171 294 222.5 450
Cin to Cout (when Cout
change)
171 202.5 222.5 267.5
Cin to Cout (when Cout
does not change)
1 1.5 11 14

11. PROPOSED 8-BIT MULTIPLIER
Fig. 5. Schematic of 8-bit multiplier
• Proposed 8-bit multiplier has
been designed using Cadence
Virtuoso in SCL PDK 180nm
technology and performance
was evaluated with power
supply of 1.8 volt using
Hspice
• It is designed with the help of
four 4 x 4 Vedic multiplier units
and 11-bit carry skip adder. For
the addition of intermediate
results generated from 4-bit
Vedic multiplier blocks 15 FA’s,
3 HA’s and 1 XOR gate is used

12. LAYOUT OF PROPOSED 8-BIT MULTIPLIER
82.965um
80.155um

13. Pre-layout simulation Post-layout simulation
WAVEFORMS OF 8-BIT VEDIC MULTIPLIER

14. PROPOSED 16-BIT MULTIPLIER
Fig. 4. Schematic of 16-bit multiplier
• Proposed 16-bit multiplier has
been designed using Cadence
Virtuoso in SCL PDK 180nm
technology and performance
was evaluated with power
supply of 1.8 volt using
Hspice
• It is designed with the help of
four 8 x 8 Vedic multiplier units
and 23-bit carry skip adder. For
the addition of intermediate
results generated from 8-bit
Vedic multiplier blocks 31 FA’s,
7 HA’s and 1 XOR gate is used

15. LAYOUT OF PROPOSED 16-BIT MULTIPLIER
167.56
um
188.715 um

16. Pre-layout simulation Post-layout simulation
WAVEFORMS OF 16-BIT VEDIC MULTIPLIER

17. PROPOSED 32-BIT VEDIC MULTIPLIER
Fig. 3. Schematic of 32-bit multiplier
• Proposed 16-bit multiplier
has been designed using
Cadence Virtuoso in SCL
PDK 180nm technology
and performance was
evaluated with power
supply of 1.8 volt using
Hspice
• It is designed with the help of
four 8 x 8 Vedic multiplier
units and 47-bit carry skip
adder. For the addition of
intermediate results generated
from 16-bit Vedic multiplier
blocks 63 FA’s,15 HA’s and 1
XOR gate is used

18. LAYOUT OF PROPOSED 32-BIT MULTIPLIER
334.8
um
414.065 um

19. WAVEFORMS OF 32-BIT VEDIC MULTIPLIER
Fig. 4 Output waveform of M45-M63 for pre-layout Simulation

20. PERFORMANCE ANALYSIS
4-bit multiplier
A0 to M5 A0 to M7
Pre
layout
(ns)
Post
layout
(ns)
Pre
layout
(ns)
Post
layout
(ns)
0.835 1.4 0.282 0.42
8-bit multiplier
A0 to M9 A0 to M15
Pre
layout
(ns)
Post
layout
(ns)
Pre
layout
(ns)
Post
layout
(ns)
1.4 2.5 0.364 0.686
The performance analysis is carried out using Cadence EDA tool in SCL PDK180nm tech
at 1.8 power supply and parasitic extraction is done using Calibre
Table 2 Propagation Delay of multipliers
16-bit multiplier
A0 to M17 A0 to M31
Pre
layout
(ns)
Post
layout
(ns)
Pre
layout
(ns)
Post
layout
(ns)
1.532 3.5 0.435 1.28
32-bit multiplier
A0 to M33 A0 to M63
Pre
layout
(ns)
Post
layout
(ns)
Pre
layout
(ns)
Post
layout
(ns)
3.912 -- 0.524 --

21. Table 3 Transistor Count and The Layout Area
Name of multiplier
Tranistor Count Layout Area(in um2)
45nm [33]
180nm
(This
work)
180nm
[35]
45nm
[33]
180nm
(This work)
4bit Vedic multiplier 320* 417 514 549.31 1364.454
8bit Vedic multiplier 1648* 2151 2634 5080.38 7454.564
16bitVedic multiplier -- 9603 11674 -- 31563
32bitVedic multiplier -- 40443 -- -- 138578.742

22. 0
1
2
3
4
5
6
7
2-bit Vedic
multiplier
4bit Vedic
multiplier
8bit Vedic
multiplier
16bitVedic
multiplier
PropagationDelay(ns)
Name of Multipliers
Contribution of Interconnections to
the Propagation Delay
for post-layout
for pre-layout
Fig.5. Graph of Contribution of
interconnections to the Propagation
Delay
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
2bit Vedic
multiplier
4bit Vedic
multiplier
8bit Vedic
multiplier
16bitVedic
multiplier
32bitVedic
multiplier
TransistorCount
Name of multipliers
Transistor Count of different
multipliers
Fig.6. Graph of Transistor Count of
different multipliers

23. LINE DIAGRAM OF 8-BIT VEDIC
MULTIPLIER
× × × × × × × ×
× × × × × × × ×
14 3
2

24. TABLE 4
PERFORMANCE COMPARISON WITH OTHER MUTIPLIERS
Name of Multiplier
Technology
Propagation delay
Pre-layout (ns) Post-layout (ns)
4-bit Vedic
Multiplier
180nm
(This work)
A0 to
M5
A0 to
M7
A0 to
M5
A0 to
M7
0.835 0.243 1.42 0.399
45nm [33] 0.268* 0.754*
90nm [34] 1.11* --
180nm [35] 4.86* --
8-bit Vedic
Multiplier
180nm
(This work)
A0 to M9 A0 to M15 A0 to M9 A0 to M15
1.5 0.416 2.5 0.754
45nm [33] 0.635* 3.479*
90nm [34] 2.02* --
180nm [35] 13.36* --

25. 16-bit Vedic
Multiplier
180nm
(This work)
A0 to M17 A0 to M31 A0 to M17 A0 to M31
2.291 0.435 3.6 1.28
90nm [34] 4* --
180nm [35] 18.53* --
* Not specified whether it is from A0 to M5 or A0 to M7 for 4-bit or A0 to M9 or A0
to M15 for 8-bit or A0 to M17 or A0 to M31 for 16-bit multiplier

26. Name of multipliers Technology Power Dissipation (mW)
Pre Layout Post Layout
`
4-bit Vedic
Multiplier
180nm
(This work)
0.115(100MHz) 0.185(100MHz)
45nm [33] 0.842** 2.95**
90nm [34] 1.74** --
180nm [35] 0.2** --
8-bit Vedic
Multiplier
180nm
(This work)
0.630(100MHz) 1.04(100MHz)
45nm [33] 7.4** 26.76**
90nm [34] 3.29** --
180nm [35] 0.97** --
16-bit Vedic
Multiplier
180nm
(This work)
3.060(100MHz) 5.299(100MHz)
90nm [34] 6.5** --
180nm [35] 0.412** --
The power dissipation for multipliers is calculated at 100 MHz.
** Not specified at which frequency the power is calculated

27. CORNER ANALYSIS
For pre-Layout simulation
Topology Parameter ff fs sf ss tt
8-bit Vedic
multiplier
Propagation delay (ns) 1.07 1.46 1.34 1.92 1.4
Power dissipation (in
mW)
0.671 0.619 0.698 0.582 0.630
16-bit
Vedic
multiplier
Propagation
delay (ns)
1.75 2.38 2.152 3.376 2.291
Power dissipation (in
mW)
3.28 2.99 3.393 2.854 3.06
32-bit
Vedic
multiplier
Propagation
delay (ns)
3.014 4.07 3.65 5.206 3.912
Power dissipation (in
mW)
14.96 13.5 15.52 12.80
8
13.98

28. For Post-layout Simulation
Name of
Multiplier
Parameter ff fs sf ss tt
4-bit Vedic
multiplier
Propagation delay
(ns)
0.923 1.484 1.347 2 1.42
Power dissipation
(in mW)
0.203 0.184 194.4 0.173 0.185
8-bit Vedic
multiplier
Propagation delay
(ns)
2.06 2.9 2.57 3.8 2.5
Power dissipation
(in mW)
1.120 1.030 1.120 0.984 1.040
16-bit
Vedic
multiplier
Propagation delay
(ns)
3 5 4.56 4.9 3.6
Power dissipation
(in mW)
5.58 5.19 6.64 4.88 5.3

29. 0
1
2
3
4
5
6
ff fs sf ss tt
PropagationDelay(ns)
Process Corners
2bit Vedic multiplier
4bit Vedic multiplier
8bit Vedic multiplier
16bit Vedic multiplier
32bit Vedic multiplier
Fig.7. Graph of Propagation
Delay at different corners for
pre-layout simulation
0
2
4
6
8
10
12
14
16
18
ff fs sf ss tt
PowerDissipation(mW)
Process Corners
2-bit Vedic multiplier
4-bit Vedic multiplier
8-bit Vedic multiplier
16-bit Vedic multiplier
32-bit Vedic multiplier
Fig.8. Graph of Power dissipation
at different corners for pre-layout
simulation

30. 0
1
2
3
4
5
6
ff fs sf ss tt
PropagationDelay(ns)
Process Corners
2bit Vedic multiplier
4bit Vedic multiplier
8bit Vedic multiplier
16bit Vedic multiplier
Fig.9. Graph of Propagation
Delay at different corners for
post-layout simulation
0
1
2
3
4
5
6
7
ff fs sf ss tt
PowerDissipation(mW)
Process corners
2bit Vedic multiplier
4bit Vedic multiplier
8bit Vedic multiplier
16bit Vedic multiplier
Fig.10. Graph of Power Dissipation
at different corners for post-layout
simulation

31. HARDWARE IMPLEMENTATION
Fig .11. Pin diagram of 8-bit Vedic multiplier

32. PIN DESCRIPTION OF 8-BIT VEDIC MULTIPLIER
Pins Purpose
A0-A7 and B0 –B7 Input pins - operand bits to be multiplied
mul_en
It is an enable input pin to enable the inputs of input side
which are to be multiplied. When it is 1, all the inputs will be
available at the input side.
out_en
It is also an enable input pin to enable the outputs of output
side. When it is1, all the outputs will be available at the output
side.
VDD,VDDO,GND,VSSO
VDD_core for vdd and VSS_core for gnd to supply power to
the core. VDDO and VSSO are also power pins for vdd and
gnd respectively to provide supply to the ring.
M0-M7 Output pins i.e. output of the multiplier

33. 8-BIT VEDIC MULTIPLIER WITH ADDITIONAL
CIRCUITRY AT I/PAND O/P SIDE

34. 8-BIT VEDIC MULTIPLIER INCLUDING PADS
PC3D21 - I/P PAD
PT3O01 - O/P PAD
POWER PADS :
PVDI – To provide
supply voltage to core
PV0I – As a ground to
core
PVDA – To provide
supply voltage to padring
PV0A - As a ground to
padring

35. LAYOUT OF 8-BIT VEDIC MULTIPLIER WITH PADS
Area of Core =
0.008 mm2
Area of total
Chip =
1.890625mm2
(1.375 X 1.375)

36. PROPAGATION DELAY AND POWER DISSIPATION OF 8-
BIT VEDIC MULTIPLIER (INCLUDING PADS)
Specifications Pre-Layout Post-Layout
Power Consumption (core circuit
including driving circuit)
0.096mW(at10MHz) 0.159mW (at10MHz)
Power Consumption (including pads) 0.26mW(at10MHz) 0.215 (at 10MHz)
Delay (Core circuit including driving
circuit)
A0 to M9 – 1.765n
A0 to M15(MSB) –
0.76n
A0 to M9 – 3.47n
A0 to M15(MSB) – 1.5n
Delay (including pads)
A0 to M9 – 4.57n
A0 to M15 – 3.6n
A0 to M9 – 6.28n
A0 to M15 – 4.36n

37. CONCLUSION
The proposed 16-bit multiplier is implemented in SCL PDK 180nm tech
using cadence EDA tool and simulation is done using Hspice simulator. It has
been shown that
 Highly compact layout leading to small contribution of interconnections
to the overall propagation delay. This is clearly indicated by relatively
small difference between pre layout and post layout propagation delay as
obtained by simulation.
 High speed. The speed of the proposed multiplier design has been
shown to be significantly better than those reported earlier.
 Vedic multiplication method offers the advantage of design reuse in the
sense that (n/2) x (n/2) multipliers and k- bit binary adders can be reused
for design of (n x n) multiplier.
The use of Full adders having equal input to output delay results in glitch
free output.

38. It has been shown that as the operand size increases the contribution of
interconnects to the propagation delay increases. It also has been shown that
implementation of Vedic multiplication method results in highly compact
layout leading to small contribution of interconnections to the overall
propagation delay. This is clearly indicated by relatively small difference
between pre-layout propagation delay and post-layout propagation delay as
obtained by simulation. This shows that optimized layout is of critical
importance for the designing of fast multipliers.
The layout of 8-bit Vedic multiplier has been given for fabrication but the
chip has not been fabricated yet by the Semiconductor lab. So, the
validation of the design could not be completed.

39. REFERENCES
1. C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Computers, vol. 13, no.
2, pp. 14-17, Feb. 1964.
2. L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-
356, Mar. 1965.
3. Amit Gupta, “Design of Fast, Low power 16 bit Multiplier using Vedic Mathematics,”
M.Tech. Thesis, SVNIT Surat, India, 2011.
4. Amit Gupta, R. K. Sharma, and Rasika Dhavse, “Low-Power High-Speed Small Area
Hybrid CMOS Full Adder,” Journal of Engineering and Technology, vol2,no.1,pp 41-44,
2012.
5. Suryasnata Tripathy, L B Omprakash, Sushanta K. Mandal & B S Patro, “Low Power
Multiplier Architectures using Vedic Mathematics in 45nm Technology for High Speed
Computing,” 2015 International Conference on Communication, Information &
Computing Technology (ICCICT), Mumbai ,Jan. 16-17,2015.
6. Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, “High Speed
ASIC Design of Complex Multiplier Using Vedic Mathematics,” Proceeding of the 2011
IEEE Students Technology Symposium, IIT Kharagpur, pp. 38, January 14-16, 2011.

40. 7. Arushi Somani, Dheeraj Jain, Sanjay Jaiswal, Kumkum Verma and Swati Kasht,
“Compare Vedic Multipliers with Conventional Heirarchical array of array
multiplier,” International Journal of Computer Technology and Electronics
Engineering (IJCTEE) vol. 2,no.6,2012.

41. PUBLICATION OUT OF THIS WORK
[1] Yogendri and Dr. A. K Gupta, “Design of High performance 8-bit Vedic
multiplier,” presented in IEEE International Conference in Advances in Computing,
Communication and Automation (ICACCA) 2016, at Tulas Institute, 8-9th April 2016.
[2] Yogendri and Dr. A. K Gupta, “Design of High performance 16-bit Vedic
multiplier,” published in National conference on Advances in Electrical, Engineering
and Energy Sciences (AEES - 2016), NIT Hamirpur, 24-25th May 2016.