Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VIT-AP University
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
Network Coding for Distributed Storage Systems(Group Meeting Talk)Jayant Apte, PhD
Reviews work of Koetter et al. and Dimakis et al.
The former provides an algebraic framework for linear network coding. The latter reduces the so called repair problem to single-source multicast network-coding problem and shows that there is a tradeoff between amount of data stored in a distributed sturage system and amount of data transfer required to repair the system if a node(hard-drive) fails.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VIT-AP University
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
Network Coding for Distributed Storage Systems(Group Meeting Talk)Jayant Apte, PhD
Reviews work of Koetter et al. and Dimakis et al.
The former provides an algebraic framework for linear network coding. The latter reduces the so called repair problem to single-source multicast network-coding problem and shows that there is a tradeoff between amount of data stored in a distributed sturage system and amount of data transfer required to repair the system if a node(hard-drive) fails.
In this paper, low linear architectures for analyzing the first two maximum or minimum values are of paramount importance in several uses, including iterative decoders. The min-sum giving out step is to that it produces only two diverse output magnitude values irrespective of the number of incoming bit-to check communication. These new micro-architecture structures would utilize the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use. Multipliers are complex units and play an important role in finding the overall area, speed and power consumption of digital designs. By using the multiplier we can minimize the parameters like latency, complexity and power consumption. The decoding algorithms we propose generalize and unify the decoding schemes originally presented the product codes and those of low-density parity-check codes.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Reduced Energy Min-Max Decoding Algorithm for Ldpc Code with Adder Correction...ijceronline
In this paper, high linear architectures for analysing the first two maximum or minimum values are of paramount importance in several uses, including iterative decoders. We proposed the adder and LDPC. The min-sum processing step that it gives only two different output magnitude values irrespective of the number of incoming bit-to check messages. These new micro-architecture layouts would employ the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use. Multipliers are complex units and play an important role in finding the overall area, speed and power consumption of digital designs. By using the multiplier we can minimize the parameters like latency, complexity and power consumption.
DETECTION AND ELIMINATION OF NON-TRIVIAL REVERSIBLE IDENTITIESIJCSEA Journal
Non-Trivial Reversible Identities (NTRIs) are reversible circuits that have equal inputs and outputs. NTRIs of arbitrary size cannot be detected, in general, using ptimization algorithms in the literature. Existence of NTRIs in a circuit will cause a slow down by increasing the number of gates and the quantum cost. NTRIs might arise because of an integration of two or more optimal reversible circuits. In this paper, an algorithm that detects and removes NTRIs in polynomial time will be proposed. Experiments that show the bad effect of NTRIs and the enhancement using the proposed algorithm will be presented.
Low complexity design of non binary ldpc decoder using extended min-sum algor...eSAT Journals
Abstract
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon’s limit. Nonbinary
LDPC is the class of binary LDPC, which works on the higher order Galois field. The decoding performance of non-binary
(NB) LDPC is better than binary LDPC for moderate code lengths. The increased computation with the increased order of field is
the major challenge in hardware realization of NB-LDPC. The extension of conventional sum-product algorithm, known as
extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper. However, a tradeoff exists
between computational complexity and decoding performance.
This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The
bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm
can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Keywords—Non-binary; LDPC; EMS algorithm; PCM
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
Performance Analysis of Steepest Descent Decoding Algorithm for LDPC Codesidescitation
Among various hard decision based Bit Flipping (BF)
algorithms for decoding Low-Density Parity-Check (LDPC)
codes such as Weighted Bit Flipping (WBF), Improved
Reliability Ratio Weighted Bit Flipping (IRRWBF) etc., the
Steepest Descent Bit Flipping Algorithm (SDBF) achieves
better error performance. In this paper, the performance of
the Steepest Descent Algorithm for both single steepest
descent and Multi steepest descent modes is analysed. Also
the performance of IEEE 802.16e standard is analysed using
Steepest Descent Bit Flipping (SDBF) decoding algorithm.
SDBF requires fewer check node and variable node operations
compared to Sum Product Algorithm (SPA) and Min Sum
Algorithm (MSA). The SDBF achieves a coding gain of 0.1 ~
0.2 dB compared to Single-SDBF without requiring complex
log and exponential operations.
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
In this paper, low linear architectures for analyzing the first two maximum or minimum values are of paramount importance in several uses, including iterative decoders. The min-sum giving out step is to that it produces only two diverse output magnitude values irrespective of the number of incoming bit-to check communication. These new micro-architecture structures would utilize the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use. Multipliers are complex units and play an important role in finding the overall area, speed and power consumption of digital designs. By using the multiplier we can minimize the parameters like latency, complexity and power consumption. The decoding algorithms we propose generalize and unify the decoding schemes originally presented the product codes and those of low-density parity-check codes.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Reduced Energy Min-Max Decoding Algorithm for Ldpc Code with Adder Correction...ijceronline
In this paper, high linear architectures for analysing the first two maximum or minimum values are of paramount importance in several uses, including iterative decoders. We proposed the adder and LDPC. The min-sum processing step that it gives only two different output magnitude values irrespective of the number of incoming bit-to check messages. These new micro-architecture layouts would employ the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use. Multipliers are complex units and play an important role in finding the overall area, speed and power consumption of digital designs. By using the multiplier we can minimize the parameters like latency, complexity and power consumption.
DETECTION AND ELIMINATION OF NON-TRIVIAL REVERSIBLE IDENTITIESIJCSEA Journal
Non-Trivial Reversible Identities (NTRIs) are reversible circuits that have equal inputs and outputs. NTRIs of arbitrary size cannot be detected, in general, using ptimization algorithms in the literature. Existence of NTRIs in a circuit will cause a slow down by increasing the number of gates and the quantum cost. NTRIs might arise because of an integration of two or more optimal reversible circuits. In this paper, an algorithm that detects and removes NTRIs in polynomial time will be proposed. Experiments that show the bad effect of NTRIs and the enhancement using the proposed algorithm will be presented.
Low complexity design of non binary ldpc decoder using extended min-sum algor...eSAT Journals
Abstract
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon’s limit. Nonbinary
LDPC is the class of binary LDPC, which works on the higher order Galois field. The decoding performance of non-binary
(NB) LDPC is better than binary LDPC for moderate code lengths. The increased computation with the increased order of field is
the major challenge in hardware realization of NB-LDPC. The extension of conventional sum-product algorithm, known as
extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper. However, a tradeoff exists
between computational complexity and decoding performance.
This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The
bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm
can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Keywords—Non-binary; LDPC; EMS algorithm; PCM
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
Performance Analysis of Steepest Descent Decoding Algorithm for LDPC Codesidescitation
Among various hard decision based Bit Flipping (BF)
algorithms for decoding Low-Density Parity-Check (LDPC)
codes such as Weighted Bit Flipping (WBF), Improved
Reliability Ratio Weighted Bit Flipping (IRRWBF) etc., the
Steepest Descent Bit Flipping Algorithm (SDBF) achieves
better error performance. In this paper, the performance of
the Steepest Descent Algorithm for both single steepest
descent and Multi steepest descent modes is analysed. Also
the performance of IEEE 802.16e standard is analysed using
Steepest Descent Bit Flipping (SDBF) decoding algorithm.
SDBF requires fewer check node and variable node operations
compared to Sum Product Algorithm (SPA) and Min Sum
Algorithm (MSA). The SDBF achieves a coding gain of 0.1 ~
0.2 dB compared to Single-SDBF without requiring complex
log and exponential operations.
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywords— advanced computing, Reversible logic circuits, reversible logic gates and comparator
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A low power adder using reversible logic gateseSAT Journals
Abstract
Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power
VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in
the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has
the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic
gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and
their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition,
subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates.
Index Terms: Reversible logic, Quantum computing, Garbage outputs, Constant inputs
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
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Design of Reversible Sequential Circuit Using Reversible Logic Synthesis
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
DOI : 10.5121/vlsic.2011.2404 37
Design of Reversible Sequential Circuit Using
Reversible Logic Synthesis
Md. Belayet Ali 1
, Md. Mosharof Hossin1
and Md. Eneyat Ullah1
1
Department of Computer Science and Engineering
Mawlana Bhashani Science and Technology University, Santosh, Tangail-1902,
Bangladesh
belayet.mbstu@gmail.com, mosharof_cse@yahoo.com, eneyat_mbstu@yahoo.com
Abstract
Reversible logic is one of the most vital issue at present time and it has different areas for its application,
those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA
computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer
graphics. It is not possible to realize quantum computing without implementation of reversible logic. The
main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the
number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed
RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better
than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this
realization is more efficient and less costly than other realizations.
Keywords
Reversible logic, Reversible gate, Power dissipation, Flip-Flop, Garbage, BME gate.
1. Introduction
Energy dissipation is an important consideration in VLSI design. Reversible logic was first
related to energy when Landauer states that information loss due to function irreversibility leads
to energy dissipation[1].This principle is further supported by Bennett that zero energy
dissipation can be achieved only when the circuit contains reversible gates [2].Information is lost
when the input vector cannot be uniquely recovered from its output vectors. Reversible logic
circuits naturally take care of heating since in a reversible logic every input vector can be
uniquely recovered from its output vectors and therefore no information is lost. According to [2]
zero energy dissipation would be possible only if the network consists of reversible gates. Thus
reversibility will become an essential property in future circuit design. Reversible circuits are also
interesting because the loss of bits of information implies energy loss [2]. Younis and Knight [3]
showed that some reversible circuits can be made asymptotically energy-lossless if their delay is
allowed to be arbitrarily large. However, reversible logic is suffering from two problems. Firstly,
there is a lack of technologies with which to build reversible gates. Work is certainly continuing
in this area. Secondly, while there is much research into how to design combinational circuits
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
38
using reversible logic, there is little in the area of sequential reversible logic implementations.
There is no limitation inherent to reversible logic preventing the design of sequential circuits; in
fact when Tommaso Toffoli first characterized reversible logic in his 1980 work Reversible
Computing [4] he stated that “Using invertible logic gates, it is ideally possible to build a
sequential computer with zero internal power dissipation. ''To establish the relevance of reversible
and quantum computing it seems appropriate to note that the VLSI industry is moving at high
speed towards miniaturization. With miniaturization it faces two issues: i) A considerable amount
of energy gets dissipated in VLSI circuits and ii) the size of the transistors are approaching the
quantum limits where tunneling and other quantum phenomena are likely to appear. Thus, we
need a superior technology that can circumvent these problems.
This paper presents a new 4*4 reversible logic gate that is BME gate. BME gate is a universal in
the sense that it can be used to synthesize any arbitrary Boolean function. It is shown that a RS
and D Flip-Flop can be realized using proposed reversible logic gate and Peres gate. The
presented design reduces the number of gates and the number of garbage outputs.
2. Reversible Logic Synthesis and Others
Definition 2.1
A circuit is reversible if it maps each input vector into a unique output vector and vice versa.
Definition 2.2
Reversible Gates are circuits in which number of outputs is equal to the number of inputs and
there is a one to one correspondence between the vector of inputs and outputs [5], [10] and [12].
Example 2.1. Let the input vector be Iv, output vector Ov and they are defined as follows,
Iv = (Ii, Ii+1, Ii+2 …Ik-1, Ik) and Ov = (Oi, Oi+1, Oi+2 … Ok-1, Ok). For each particular i, there exits the
relationship Iv ↔ Ov [10].
A reversible circuit should be designed using minimum number of reversible logic gates. From
the point of view of reversible circuit design, there are many parameters for determining the
complexity and performance of circuits [6], [7], [8] and [11].
Definition 2.3
Garbage output refers to the number of inputs that are to be maintained constant at either 0 or 1 in
order to synthesize the given logical function [12].
Definition 2.4
Quantum cost refers to the cost of the circuit in terms of the cost of a primitive gate. It is
calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize
the circuit. The quantum cost of a circuit is the minimum number of 2*2 unitary gates to represent
the circuit keeping the output unchanged. The quantum cost of a 1*1 gate is 0 and that of any 2*2
gate is the same, which is 1 [19]. So, the quantum cost of a 2*2 Feynman gate is 1. Again, the
quantum cost of a 3*3 Toffoli, Fredkin, Peres and New gate is 5, 5, 4 and 11 respectively
[20][21][22].
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
39
Definition 2.5
Flexibility refers to the universality of a reversible logic gate in realizing more functions [12].
Definition 2.6
Gate Level refers to the number of levels in the circuit which are required to realize the given
logic functions [12].
Definition 2.7
Hardware Complexity refers to the total number of logic operation in a circuit. Means the total
number of AND, OR and EXOR operation in a circuit [9] and [12].
3. Major Several Reversible Logic
3.1 Feynman Gate
It is a 2*2 Feynman gate [13]. The input vector is I (A, B) and the output vector is O(P, Q). The
outputs are defined by P=A, Q=A⊕B. Quantum cost of a Feynman gate is 1. Figure 1 shows a
2*2 Feynman gate.
Figure 1: Feynman gate
3.2 Double Feynman Gate (F2G)
It is a 3*3 Double Feynman gate [14].The input vector is I (A, B, C) and the output vector is O
(P, Q, R). The outputs are defined by P = A, Q=A⊕B, R=A⊕C. Quantum cost of double
Feynman gate is 2.
Figure 2 shows a 3*3 Double Feynman gate.
Figure 2: Double Feynman gate
3.3 Toffoli Gate
It is a 3*3 Toffoli gate [6] The input vector is I(A, B, C) and the output vector is O(P,Q,R). The
outputs are defined by P=A, Q=B, R=AB⊕C. Quantum cost of a Toffoli gate is 5. Figure 3 shows
a 3*3 Toffoli gate.
P=A
Q=A⊕B
R=A⊕C
A
B
C
Double
Feynman
Gate
A
C
B
P=A
Q=A⊕B
R=A⊕C
● ●
P=A
Q=A⊕B
A
B
Feynman
Gate
Q=A⊕B
P=AA
B
●
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
40
Figure 3: Toffoli gate
3.4 Fredkin Gate
It is a 3*3 Fredkin gate [7]. The input vector is I (A, B, C) and the output vector is O(P, Q, R).
The output is defined by P=A, Q= AഥB⊕AC and R= AഥC⊕AB. Quantum cost of a Fredkin gate is
5. Figure 4 shows a 3*3 Fredkin gate.
Figure 4: Fredkin gate
3.5 Peres Gate
It is a 3*3 Peres gate [15]. The input vector is I (A, B, C) and the output vector is O (P, Q, R).
The output is defined by P = A, Q = A⊕B and R=AB⊕C. Quantum cost of a Peres gate is 4.
Figure 5 shows a 3*3 Peres gate.
Figure 5: Peres gates
3.6 Double Peres gate
It is a 4*4 Double Peres Gate [16]. The input vector is I(A,B,C,D) and the output vector is
O(P,Q,R,S).The output is defined by P=A,Q=A⊕B,R=A⊕B⊕D and S=(A⊕B)D⊕AB⊕C.
Figure 6 shows a 4*4 Double Peres gate.
Figure 6: DPG gate
S= (A⊕B) D⊕AB⊕C
P=A
Q=A⊕B
R=A⊕B⊕D
A
B
C
D
DPG
Gate
A
B
C
Q=B
R=AB⊕C
P=A●
●
P=A
Q=B
R=AB⊕C
A
B
C
Toffoli
Gate
P=A
Q=AഥB ⊕AC
R=AഥC⊕AB
A
B
C
Fredkin
Gate
A
B
C
Q=AഥB⊕AC
R=AഥC⊕AB
P=A●
P=A
Q=A⊕B
R=AB⊕C
A
B
C
Peres
Gate
R=AB⊕C
Q=A⊕B
P=AA
B
C
●
● ●
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
41
4. Related Work
4.1 RS Flip-Flop Designs
Thapliyal [18] proposed reversible clocked RS Flip-Flop which is a direct realization of
conventional irreversible circuit realized. His design is costly because it incorporated two New
gates whose quantum cost is higher than other reversible gates which is mentioned at Section 2 in
Definition 2.4. Moreover, the design contained a single fan-out which is forbidden in strict
reversible sense [23].Ashis [17] proposed design perform NAND operations using a single 3*3
Peres gate instead of using Fredkin gate, his design less costly reversible SR Flip-Flop using the
Peres gate.Since the design of Thapliyal [18] consists of two New gates and the quantum cost of
each New gate is 11, so the overall design cost increased. Moreover Ashis [17] realization
contained two redundant Feynman gates. But Ashis [17] design is less costly in terms of number
of gates, garbage bits and quantum costs than Thapliyal [18] design.
4.2 D Flip-Flop Designs
Thapliyal [18] proposed a reversible clocked D Flip-Flop that is also costly because it contained
four New gates. Moreover a fanout can be seen in the design. Ashis [17] proposed design of
reversible clocked D Flip-Flop employs the proposed SR latch. The clocked D Flip-Flop is
efficient to use in designing reversible memory circuits because of its superiority over the existing
one [18] in terms of number of gates, garbage bits and quantum cost.
5. Proposed Reversible Logic Gate
We have proposed a new 4*4 reversible logic gate named BME gate. The input vector is
I(A,B,C,D) and the output vector is O(P,Q,R,S).The output is defined by P=A, Q=AB⊕C,
R=AD⊕C and S= AഥB⊕C⊕D. The block diagram of BME gate is shown in Figure 7.
Figure 7: Block diagram of a new reversible BME gate
Table 1: Truth Table of New Reversible BME Gate
A B C D A AB⊕C AD⊕C AഥB⊕C⊕D
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 1 1 1
0 0 1 1 0 1 1 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 0 0
0 1 1 0 0 1 1 0
0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 0
1 0 0 1 1 0 1 1
1 0 1 0 1 1 1 1
S= AഥB⊕C⊕D
P=A
Q=AB⊕C
R=AD⊕C
A
B
C
D
BME
Gate
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
42
We can verify our BME gate by the truth table that the output and input vectors have one to one
mapping between them which satisfies the condition of reversibility of a gate. We can see that
from Table 1 that the 16 different input and output vectors are unique means they have one to one
mapping between them. So, BME gate satisfies the condition of reversibility.
6. Proposed Design of Reversible RS Flip-Flop
The RS Flip-Flop can be mapped with one BME and two Peres gate. The BME gate needs E, S, 1
and R inputs respectively in 1st
, 2nd
, 3rd
and 4th
input. The output .ܧ ܵ and .ܧ ܴ are realized by
one BME in the 2nd
and 3rd
outputs. Now, the 2nd
output of E. S that is ܵ̅ can be used as 2nd
input
of one Peres gate. The 3rd
output of E. R that is Rഥ can be used as 2nd
input of another Peres gate.
Thus, our design needs only 3 reversible logic gates with 4 garbage outputs to design of RS Flip-
Flip. The proposed design of RS Flip-Flip is shown in Figure 8.
Figure 8: Proposed RS Flip-Flop
6.1. Evaluation of Proposed RS Flip-Flop
Table 2: Comparison of Different RS Flip-Flop
No of gates No of garbage outputs
Proposed design 3 4
Existing design [17] 5 6
Existing design [18] 6 8
From Table 2 we can see that the design is better than the design [17] and [18].Here, we need
only 3 gates and 4 garbage outputs. So, the design is optimized than the design of [17] and [18] in
terms of no of gates and garbage outputs.
1 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
1 1 0 1 1 1 1 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 0 0
Q
Qഥ
1
Rഥ
Sത
Sത
1
Peres
Gate
Peres
Gate
1
R
E
S BME
Gate
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
43
7. Proposed Design of Reversible D Flip-Flop Using Proposed RS Flip-
Flop
The D Flip-Flop can be mapped with one BME and two Peres gate. The BME gate needs D,
CLK, 1 and 0 inputs respectively in 1st
, 2nd
, 3rd
and 4th
input. The output D. CLK and Dഥ. CLKതതതതതതതതത are
realized by one BME in the 2nd
and 4th
outputs. Now, the 2nd
output D. CLK that is ܵ̅ can be used
as 2nd
input of one Peres gate. The 4th
output Dഥ. CLKതതതതതതതതതthat is Rഥ can be used as 2nd
input of another
Peres gate. Thus, our design needs only 3 reversible logic gates with 4 garbage outputs to design
of RS Flip-Flip. The proposed design of D Flip-Flip is shown in Figure 9.
Figure 9: Proposed reversible clocked D Flip-Flop using Proposed RS Flip-Flop
7.1. Evaluation of Proposed design of D Flip-Flop using Proposed RS Flip-Flop
Table 3: Comparison of Different D Flip-Flop
No of gates No of garbage outputs
Proposed design 3 4
Existing design [17] 5 5
Existing design [18] 7 8
From Table 3 we can see that the design is better than the design [17] and [18].Here, we need
only 3 gates and 4 garbage output. So, the design is optimized than the design of [17] and [18] in
terms of no of gates and garbage outputs.
8. Conclusions
The proposed reversible design is utilized for efficiently designing RS and D Flip-Flop. As, Flip-
Flips are most important memory elements and used in several circuits like RAM, Logic Blocks
of FPGA. We have seen by comparing the existing design with our proposed design that the
proposed design is less costly in terms of number of gates and number of garbage outputs. The
proposed design is highly optimized. So, this proposed gate can contribute significantly in the
reversible logic community. Thus, the resulting reversible sequential circuits are more cost
competent.
Q
Qഥ
1
Peres
Gate
Rഥ
Sത
Sത
1
1
0
D
E BME
Gate
Peres
Gate
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
45
[19] J.Smoline and David P.DiVincenzo, “Five two-qubit gates are sufficient to implement the quantum
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Authors
Md. Belayet Ali, received his B.Sc (Engg.) degree in Computer Science and Engineering from Mawlana
Bhashani Science and Technology University, Santosh, Tangail-1902, Bangladesh, in 2008. He is working
as Lecturer in Department of Computer Science and Engieering at (MBSTU), Santosh, Tangail-1902,
Bangladesh. He has 2(two) years experience of working in MBSTU. He has published 04(four) papers in
national, international journals. His area of interest includes reversible logic synthesis, multi-valued
reversible logic synthesis, network business security, cloud computing.