This document discusses pass transistor logic, which uses MOS transistors to transfer charge between circuit nodes under gate control. It describes how nMOS and pMOS transistors can pass strong or weak signals depending on their configuration. Threshold voltage drops, charge sharing problems, and sneak paths that can occur in pass transistor logic circuits are also covered. The document provides examples of analyzing charge distribution before and after transistors turn on, and presents a general design for pass transistor logic gates that ensures both charging and discharging paths exist. Exercises are included on analyzing charge sharing and designing pass transistor logic circuits like majority gates and decoders.

1. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Pass Transistor Logic
Pass Transistor Logic involves nMOS or pMOS transistors to transfer the charge from one
node of a circuit to another node under the control of MOS gate voltage.
Pass transistor chain can be used in design of regular array based structures such as ROMS,
PLAs, Multiplexers etc
Strength of output signal
The strength of a signal is measured by how closely it approximates an ideal voltage source. In
general, the stronger a signal, the more current it can source or sink. The power supplies, or rails,
(VDD and GND) are the source of the strongest 1s and 0s.
An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a
strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is less
than VDD. We say it passes a degraded or weak 1.
A pMOS transistor is an almost perfect switch when passing a 1 and thus we say it passes a
strong 1. However, the nMOS transistor is imperfect at passing a 0. The high voltage level is less
than VDD. We say it passes a degraded or weak 0.

2. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Threshold Drops
Rule 1. If the Gate and Drain are both at VDD, the source can rise only upto one threshold
below the gate. If the Source tries to rise higher, the device goes to Cut-off region.

3. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Rule 2. If the Gate is at-least one threshold voltage higher than the drain, the source will
rise within few millivolts to Drain potential.
Rule 3. If the Gate and Drain of a pass-transistor are both High, the source will rise to the
lower of the two potentials VDD and VG-VT.
Thus, following generalization can be made.

4. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Exercises:

5. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Exercises:
Advantages of Pass-transistor Logic
1. They are not ratio-ed devices and hence, minimum geometry transistor can be used
2. They do not dissipate stand-by power.
3. They utilize the minimum number of transistors to implement a logic function.

6. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Limitations of Pass-transistor Logic
1. Consider a three-input AND gate, as shown
Initially, if inputs are A = B = C = 1, then the output node is charged to VDD. Later, control B
goes low and the corresponding pass transistor is turned off. Ideally, the output node must be at
0V. But, there is no path for the output node to discharge and therefore output is not pulled-
down instantly.
Limitation: In designing pass-transistor logic, care must be taken to ensure the existence of
both charging and discharging paths to the inputs of all inverters.
2. Consider a situation shown in figure.
Even when the applied input voltage is 5V, the voltage at the input of the inverter is 2V. This is
well below the inverter switching threshold voltage and will most likely be treated by the
inverter as a logic ‘0’ when it should have been a logic ‘1’.
The issue can be resolved by adjusting the W/L ratios of pull-up and pull-down devices so that
signals are appropriately restored.
Limitation: In designing pass-transistor logic, one must avoid to drive a pass transistor with
the output of another pass transistor.

7. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
3. Charge sharing
Charge sharing problems occur when two capacitive nodes charged to different voltages are
connected through a pass-transistor. When the pass transistor is turned on, it connects the two
nodes, resulting in redistribution of the charge on both nodes.
Charge sharing is a serious problem in pre-charge circuits and must be carefully guarded
against.
4. Sneak paths
A sneak path is created when two pass transistors are both ON at the same time and one is
connected to VDD while the other os connected to GND.
Charge Sharing
Capacitors C1 and C2 are in parallel when pass transistor P is conducting. This forces the
voltages across C1 and C2 to be equal. If the two capacitors are charged to different initial
voltages, charge sharing will occur when P turns on.
Let the initial voltage and charge on C1 be V1 and Q1, and the initial voltage and charge on C2 be
V2 and Q2. After the pass transistor turns on, the final charges on C1 and C2 are Q1f and Q2f,
respectively, and both capacitors are charged to voltage Vf.

8. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
The initial charge balance equation is
Q1 + Q2 = C1V1 +C2V2
The final charge balance equation is
Q1f + Q2f = (C1 +C2)Vf
To find the final charge distribution, equate the charges before and after P turns on
C1V1 + C2V2 = (C1 +C2) Vf
Solve for Vf, then Q1f
Vf =
C1V1+C2V2
C1+C2
Q1f = C1Vf = (C1V1 +C2 V2) (
C1
C1+C2
)
Exercise:
Determine the charge on each capacitor of figure above, before and after P turns on, if C1=20fF,
C2=20fF, V1= 1V and V2 =5V.
Solution:
Initially, Q1 =C1V1 =20fC, and Q2 = C2V2 = 100fC.
After P turns on,
Vf =
20 1 + 20(5)
20+20
= 30V
Q1f = Q2f =C1Vf = 20(3) = 60fC.

9. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Try it yourself
1. Determine the charge on each capactor before and after P turns on, if C1 =10fF, C2 =50fF,
V1 =0V, V2 = 5V and VG = 6V.
2. Repeat 1 if, C1 is 2.6fF and C2 is 4fF.
Designing Pass Transistor Logic Circuits
The following circuit shows a General function block to realize Boolean Gates using pass
transistor logic, such that both charging and discharging paths exist.
I0 and I1 are the control inputs to be applied at Drain Terminal and C0 and C1 are the gate control
inputs.
Output Inputs Controls
Y I0 I1 C0 C1
AB 0 B A’ A
(AB)’ 1 B’ A’ A
A +B B 1 A’ A
(A + B)’ B’ 0 A’ A
A ^ B B B’ A’ A
(A ^ B)’ B’ B A’ A
Multiplexer A B S’ S

10. Compiled by : Sudhanshu Janwadkar, 6th
November 2017
Try it yourself:
1. The output of a majority gate is true if at least two inputs are true. The controls are A and
B. Show the Karnaugh map. Design a pass-transistor circuit for a three-input majority gate.
2. Design a pass-transistor circuit for a 2:4 decoder.
3. Realize the following gates using Pass transistor logic:
a. 3-input NAND gate
b. 3-input NOR gate
c. 3-input XOR gate
d. 3-input XNOR gate