This document summarizes a research paper on designing a high-speed, time-efficient reversible arithmetic logic unit (ALU) using novel reversible logic gates. The paper proposes two new 4x4 reversible logic gates, the MRG and PAOG gates, that can be configured to perform various logical calculations with minimal delay. An 16-bit reversible ALU design is presented that can perform eight operations simultaneously using these gates. The ALU design is verified through simulation in ModelSim 6.5 and synthesis using Xilinx ISE 14.1 software. Analysis shows the proposed ALU design has advantages over existing designs in terms of speed, efficiency and logical functionality.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Reversable Logic Based Design using Submicron TechnologySai Viswanath
Reversible logic has emerged as a computing paradigm having application in low power CMOS, quantum and optical computing. Design of reversible logic gate is reversible operation, when we say reversible it performing computation in such a way that any previous state can be reconstructed at given a description of the current state. The classical set of gates such as AND, OR, and XOR are not reversible.
This presentation is a design of reversible logic gate used for reversible operation. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation results of forward & backward computation of reversible FREDKIN gate and TSG gate.
Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmann’s constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit model
Design and minimization of reversible programmable logic arrays and its reali...Sajib Mitra
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbage and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbage, quantum costs and delay.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Reversable Logic Based Design using Submicron TechnologySai Viswanath
Reversible logic has emerged as a computing paradigm having application in low power CMOS, quantum and optical computing. Design of reversible logic gate is reversible operation, when we say reversible it performing computation in such a way that any previous state can be reconstructed at given a description of the current state. The classical set of gates such as AND, OR, and XOR are not reversible.
This presentation is a design of reversible logic gate used for reversible operation. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation results of forward & backward computation of reversible FREDKIN gate and TSG gate.
Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmann’s constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit model
Design and minimization of reversible programmable logic arrays and its reali...Sajib Mitra
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbage and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbage, quantum costs and delay.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Design of High speed Low Power Reversible Vedic multiplier and Reversible Div...IJERA Editor
This paper bring out a 32X32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper we propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer, reversible n-bit register with parallel load line. The reversible vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i. This reversible vedic multiplier results shows less delay and less power consumption by comparing with array multiplier.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adderijtsrd
Reversible circuits are one promising direction withapplications in the field of low-power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge-Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,reversible implementations of ripple-carry, Kogge-Stone carrylook-ahead adders are analyzed and compared in terms ofdelay. The proposed design consists of the reversible Fredkin,Feynman, MG, HNG, PG and RKSC gates. The performancecharacteristics analysis is carried out in Xilinx environment. Swetha Potharla | Rajkumar R"A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5758.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/5758/a-novel-design-of-a-4-bit-reversible-alu-using--kogge-stone-adder/swetha-potharla
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSPVLSICS Design
Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.
Low Power VLSI Design of Modified Booth Multiplieridescitation
Low power VLSI circuits became very vital criteria
for designing the energy efficient electronic designs for prime
performance and compact devices. Multipliers play a very
important role for planning energy economical processors that
decides the potency of the processor. To scale back the facility
consumption of multiplier factor booth coding methodology
is being employed to rearrange the input bits. The operation
of the booth decoder is to rearrange the given booth equivalent.
Booth decoder can increase the range of zeros in variety. Hence
the switching activity are going to be reduced that further
reduces the power consumption of the design. The input bit
constant determines the switching activity part that’s once
the input constant is zero corresponding rows or column of
the adder ought to be deactivated. When multiplicand contains
a lot of number of zeros the higher power reduction will takes
place. therefore in booth multiplier factor high power
reductions are going to be achieved.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Design of High speed Low Power Reversible Vedic multiplier and Reversible Div...IJERA Editor
This paper bring out a 32X32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper we propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer, reversible n-bit register with parallel load line. The reversible vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i. This reversible vedic multiplier results shows less delay and less power consumption by comparing with array multiplier.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adderijtsrd
Reversible circuits are one promising direction withapplications in the field of low-power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge-Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,reversible implementations of ripple-carry, Kogge-Stone carrylook-ahead adders are analyzed and compared in terms ofdelay. The proposed design consists of the reversible Fredkin,Feynman, MG, HNG, PG and RKSC gates. The performancecharacteristics analysis is carried out in Xilinx environment. Swetha Potharla | Rajkumar R"A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5758.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/5758/a-novel-design-of-a-4-bit-reversible-alu-using--kogge-stone-adder/swetha-potharla
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSPVLSICS Design
Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.
Low Power VLSI Design of Modified Booth Multiplieridescitation
Low power VLSI circuits became very vital criteria
for designing the energy efficient electronic designs for prime
performance and compact devices. Multipliers play a very
important role for planning energy economical processors that
decides the potency of the processor. To scale back the facility
consumption of multiplier factor booth coding methodology
is being employed to rearrange the input bits. The operation
of the booth decoder is to rearrange the given booth equivalent.
Booth decoder can increase the range of zeros in variety. Hence
the switching activity are going to be reduced that further
reduces the power consumption of the design. The input bit
constant determines the switching activity part that’s once
the input constant is zero corresponding rows or column of
the adder ought to be deactivated. When multiplicand contains
a lot of number of zeros the higher power reduction will takes
place. therefore in booth multiplier factor high power
reductions are going to be achieved.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VIT-AP University
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Design of 4:16 decoder using reversible logic gatesIJERA Editor
Reversible logic has received great importance in the recent years because of its feature of reduction in power
dissipation. It finds application in low power digital designs, quantum computing, nanotechnology, DNA
computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using
reversible logic. Decoders are one of the most important circuits used in combinational logic. Different
approaches have been proposed for their design. In this article, we have proposed a novel design of 4:16.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)VLSICS Design
Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuit’s primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Method for Prevention of Bandwidth Distributed Denial of Service AttacksIJERD Editor
Distributed Denial of Service (DDoS) Attacks became a massive threat to the Internet. Traditional
Architecture of internet is vulnerable to the attacks like DDoS. Attacker primarily acquire his army of Zombies,
then that army will be instructed by the Attacker that when to start an attack and on whom the attack should be
done. In this paper, different techniques which are used to perform DDoS Attacks, Tools that were used to
perform Attacks and Countermeasures in order to detect the attackers and eliminate the Bandwidth Distributed
Denial of Service attacks (B-DDoS) are reviewed. DDoS Attacks were done by using various Flooding
techniques which are used in DDoS attack.
The main purpose of this paper is to design an architecture which can reduce the Bandwidth
Distributed Denial of service Attack and make the victim site or server available for the normal users by
eliminating the zombie machines. Our Primary focus of this paper is to dispute how normal machines are
turning into zombies (Bots), how attack is been initiated, DDoS attack procedure and how an organization can
save their server from being a DDoS victim. In order to present this we implemented a simulated environment
with Cisco switches, Routers, Firewall, some virtual machines and some Attack tools to display a real DDoS
attack. By using Time scheduling, Resource Limiting, System log, Access Control List and some Modular
policy Framework we stopped the attack and identified the Attacker (Bot) machines
Hearing loss is one of the most common human impairments. It is estimated that by year 2015 more
than 700 million people will suffer mild deafness. Most can be helped by hearing aid devices depending on the
severity of their hearing loss. This paper describes the implementation and characterization details of a dual
channel transmitter front end (TFE) for digital hearing aid (DHA) applications that use novel micro
electromechanical- systems (MEMS) audio transducers and ultra-low power-scalable analog-to-digital
converters (ADCs), which enable a very-low form factor, energy-efficient implementation for next-generation
DHA. The contribution of the design is the implementation of the dual channel MEMS microphones and powerscalable
ADC system.
Influence of tensile behaviour of slab on the structural Behaviour of shear c...IJERD Editor
-A composite beam is composed of a steel beam and a slab connected by means of shear connectors
like studs installed on the top flange of the steel beam to form a structure behaving monolithically. This study
analyzes the effects of the tensile behavior of the slab on the structural behavior of the shear connection like slip
stiffness and maximum shear force in composite beams subjected to hogging moment. The results show that the
shear studs located in the crack-concentration zones due to large hogging moments sustain significantly smaller
shear force and slip stiffness than the other zones. Moreover, the reduction of the slip stiffness in the shear
connection appears also to be closely related to the change in the tensile strain of rebar according to the increase
of the load. Further experimental and analytical studies shall be conducted considering variables such as the
reinforcement ratio and the arrangement of shear connectors to achieve efficient design of the shear connection
in composite beams subjected to hogging moment.
Gold prospecting using Remote Sensing ‘A case study of Sudan’IJERD Editor
Gold has been extracted from northeast Africa for more than 5000 years, and this may be the first
place where the metal was extracted. The Arabian-Nubian Shield (ANS) is an exposure of Precambrian
crystalline rocks on the flanks of the Red Sea. The crystalline rocks are mostly Neoproterozoic in age. ANS
includes the nations of Israel, Jordan. Egypt, Saudi Arabia, Sudan, Eritrea, Ethiopia, Yemen, and Somalia.
Arabian Nubian Shield Consists of juvenile continental crest that formed between 900 550 Ma, when intra
oceanic arc welded together along ophiolite decorated arc. Primary Au mineralization probably developed in
association with the growth of intra oceanic arc and evolution of back arc. Multiple episodes of deformation
have obscured the primary metallogenic setting, but at least some of the deposits preserve evidence that they
originate as sea floor massive sulphide deposits.
The Red Sea Hills Region is a vast span of rugged, harsh and inhospitable sector of the Earth with
inimical moon-like terrain, nevertheless since ancient times it is famed to be an abode of gold and was a major
source of wealth for the Pharaohs of ancient Egypt. The Pharaohs old workings have been periodically
rediscovered through time. Recent endeavours by the Geological Research Authority of Sudan led to the
discovery of a score of occurrences with gold and massive sulphide mineralizations. In the nineties of the
previous century the Geological Research Authority of Sudan (GRAS) in cooperation with BRGM utilized
satellite data of Landsat TM using spectral ratio technique to map possible mineralized zones in the Red Sea
Hills of Sudan. The outcome of the study mapped a gossan type gold mineralization. Band ratio technique was
applied to Arbaat area and a signature of alteration zone was detected. The alteration zones are commonly
associated with mineralization. The alteration zones are commonly associated with mineralization. A filed check
confirmed the existence of stock work of gold bearing quartz in the alteration zone. Another type of gold
mineralization that was discovered using remote sensing is the gold associated with metachert in the Atmur
Desert.
Reducing Corrosion Rate by Welding DesignIJERD Editor
The paper addresses the importance of welding design to prevent corrosion at steel. Welding is
used to join pipe, profiles at bridges, spindle, and a lot more part of engineering construction. The
problems happened associated with welding are common issues in these fields, especially corrosion.
Corrosion can be reduced with many methods, they are painting, controlling humidity, and also good
welding design. In the research, it can be found that reducing residual stress on the welding can be
solved in corrosion rate reduction problem.
Preheating on 500oC and 600oC give better condition to reduce corosion rate than condition after
preheating 400oC. For all welding groove type, material with 500oC and 600oC preheating after 14 days
corrosion test is 0,5%-0,69% lost. Material with 400oC preheating after 14 days corrosion test is 0,57%-0,76%
lost.
Welding groove also influence corrosion rate. X and V type welding groove give better condition to reduce
corrosion rate than use 1/2V and 1/2 X welding groove. After 14 days corrosion test, the samples with
X welding groove type is 0,5%-0,57% lost. The samples with V welding groove after 14 days corrosion test is
0,51%-0,59% lost. The samples with 1/2V and 1/2X welding groove after 14 days corrosion test is 0,58%-
0,71% lost.
Router 1X3 – RTL Design and VerificationIJERD Editor
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks (as opposed to a network switch, which connects data lines from one single network). This paper,
mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of
router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top
module.
Active Power Exchange in Distributed Power-Flow Controller (DPFC) At Third Ha...IJERD Editor
This paper presents a component within the flexible ac-transmission system (FACTS) family, called
distributed power-flow controller (DPFC). The DPFC is derived from the unified power-flow controller (UPFC)
with an eliminated common dc link. The DPFC has the same control capabilities as the UPFC, which comprise
the adjustment of the line impedance, the transmission angle, and the bus voltage. The active power exchange
between the shunt and series converters, which is through the common dc link in the UPFC, is now through the
transmission lines at the third-harmonic frequency. DPFC multiple small-size single-phase converters which
reduces the cost of equipment, no voltage isolation between phases, increases redundancy and there by
reliability increases. The principle and analysis of the DPFC are presented in this paper and the corresponding
simulation results that are carried out on a scaled prototype are also shown.
Mitigation of Voltage Sag/Swell with Fuzzy Control Reduced Rating DVRIJERD Editor
Power quality has been an issue that is becoming increasingly pivotal in industrial electricity
consumers point of view in recent times. Modern industries employ Sensitive power electronic equipments,
control devices and non-linear loads as part of automated processes to increase energy efficiency and
productivity. Voltage disturbances are the most common power quality problem due to this the use of a large
numbers of sophisticated and sensitive electronic equipment in industrial systems is increased. This paper
discusses the design and simulation of dynamic voltage restorer for improvement of power quality and
reduce the harmonics distortion of sensitive loads. Power quality problem is occurring at non-standard
voltage, current and frequency. Electronic devices are very sensitive loads. In power system voltage sag,
swell, flicker and harmonics are some of the problem to the sensitive load. The compensation capability
of a DVR depends primarily on the maximum voltage injection ability and the amount of stored
energy available within the restorer. This device is connected in series with the distribution feeder at
medium voltage. A fuzzy logic control is used to produce the gate pulses for control circuit of DVR and the
circuit is simulated by using MATLAB/SIMULINK software.
Study on the Fused Deposition Modelling In Additive ManufacturingIJERD Editor
Additive manufacturing process, also popularly known as 3-D printing, is a process where a product
is created in a succession of layers. It is based on a novel materials incremental manufacturing philosophy.
Unlike conventional manufacturing processes where material is removed from a given work price to derive the
final shape of a product, 3-D printing develops the product from scratch thus obviating the necessity to cut away
materials. This prevents wastage of raw materials. Commonly used raw materials for the process are ABS
plastic, PLA and nylon. Recently the use of gold, bronze and wood has also been implemented. The complexity
factor of this process is 0% as in any object of any shape and size can be manufactured.
Spyware triggering system by particular string valueIJERD Editor
This computer programme can be used for good and bad purpose in hacking or in any general
purpose. We can say it is next step for hacking techniques such as keylogger and spyware. Once in this system if
user or hacker store particular string as a input after that software continually compare typing activity of user
with that stored string and if it is match then launch spyware programme.
A Blind Steganalysis on JPEG Gray Level Image Based on Statistical Features a...IJERD Editor
This paper presents a blind steganalysis technique to effectively attack the JPEG steganographic
schemes i.e. Jsteg, F5, Outguess and DWT Based. The proposed method exploits the correlations between
block-DCTcoefficients from intra-block and inter-block relation and the statistical moments of characteristic
functions of the test image is selected as features. The features are extracted from the BDCT JPEG 2-array.
Support Vector Machine with cross-validation is implemented for the classification.The proposed scheme gives
improved outcome in attacking.
Secure Image Transmission for Cloud Storage System Using Hybrid SchemeIJERD Editor
- Data over the cloud is transferred or transmitted between servers and users. Privacy of that
data is very important as it belongs to personal information. If data get hacked by the hacker, can be
used to defame a person’s social data. Sometimes delay are held during data transmission. i.e. Mobile
communication, bandwidth is low. Hence compression algorithms are proposed for fast and efficient
transmission, encryption is used for security purposes and blurring is used by providing additional
layers of security. These algorithms are hybridized for having a robust and efficient security and
transmission over cloud storage system.
Application of Buckley-Leverett Equation in Modeling the Radius of Invasion i...IJERD Editor
A thorough review of existing literature indicates that the Buckley-Leverett equation only analyzes
waterflood practices directly without any adjustments on real reservoir scenarios. By doing so, quite a number
of errors are introduced into these analyses. Also, for most waterflood scenarios, a radial investigation is more
appropriate than a simplified linear system. This study investigates the adoption of the Buckley-Leverett
equation to estimate the radius invasion of the displacing fluid during waterflooding. The model is also adopted
for a Microbial flood and a comparative analysis is conducted for both waterflooding and microbial flooding.
Results shown from the analysis doesn’t only records a success in determining the radial distance of the leading
edge of water during the flooding process, but also gives a clearer understanding of the applicability of
microbes to enhance oil production through in-situ production of bio-products like bio surfactans, biogenic
gases, bio acids etc.
Gesture Gaming on the World Wide Web Using an Ordinary Web CameraIJERD Editor
- Gesture gaming is a method by which users having a laptop/pc/x-box play games using natural or
bodily gestures. This paper presents a way of playing free flash games on the internet using an ordinary webcam
with the help of open source technologies. Emphasis in human activity recognition is given on the pose
estimation and the consistency in the pose of the player. These are estimated with the help of an ordinary web
camera having different resolutions from VGA to 20mps. Our work involved giving a 10 second documentary to
the user on how to play a particular game using gestures and what are the various kinds of gestures that can be
performed in front of the system. The initial inputs of the RGB values for the gesture component is obtained by
instructing the user to place his component in a red box in about 10 seconds after the short documentary before
the game is finished. Later the system opens the concerned game on the internet on popular flash game sites like
miniclip, games arcade, GameStop etc and loads the game clicking at various places and brings the state to a
place where the user is to perform only gestures to start playing the game. At any point of time the user can call
off the game by hitting the esc key and the program will release all of the controls and return to the desktop. It
was noted that the results obtained using an ordinary webcam matched that of the Kinect and the users could
relive the gaming experience of the free flash games on the net. Therefore effective in game advertising could
also be achieved thus resulting in a disruptive growth to the advertising firms.
Hardware Analysis of Resonant Frequency Converter Using Isolated Circuits And...IJERD Editor
-LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region[5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Amateurs Radio operator, also known as HAM communicates with other HAMs through Radio
waves. Wireless communication in which Moon is used as natural satellite is called Moon-bounce or EME
(Earth -Moon-Earth) technique. Long distance communication (DXing) using Very High Frequency (VHF)
operated amateur HAM radio was difficult. Even with the modest setup having good transceiver, power
amplifier and high gain antenna with high directivity, VHF DXing is possible. Generally 2X11 YAGI antenna
along with rotor to set horizontal and vertical angle is used. Moon tracking software gives exact location,
visibility of Moon at both the stations and other vital data to acquire real time position of moon.
“MS-Extractor: An Innovative Approach to Extract Microsatellites on „Y‟ Chrom...IJERD Editor
Simple Sequence Repeats (SSR), also known as Microsatellites, have been extensively used as
molecular markers due to their abundance and high degree of polymorphism. The nucleotide sequences of
polymorphic forms of the same gene should be 99.9% identical. So, Microsatellites extraction from the Gene is
crucial. However, Microsatellites repeat count is compared, if they differ largely, he has some disorder. The Y
chromosome likely contains 50 to 60 genes that provide instructions for making proteins. Because only males
have the Y chromosome, the genes on this chromosome tend to be involved in male sex determination and
development. Several Microsatellite Extractors exist and they fail to extract microsatellites on large data sets of
giga bytes and tera bytes in size. The proposed tool “MS-Extractor: An Innovative Approach to extract
Microsatellites on „Y‟ Chromosome” can extract both Perfect as well as Imperfect Microsatellites from large
data sets of human genome „Y‟. The proposed system uses string matching with sliding window approach to
locate Microsatellites and extracts them.
Importance of Measurements in Smart GridIJERD Editor
- The need to get reliable supply, independence from fossil fuels, and capability to provide clean
energy at a fixed and lower cost, the existing power grid structure is transforming into Smart Grid. The
development of a smart energy distribution grid is a current goal of many nations. A Smart Grid should have
new capabilities such as self-healing, high reliability, energy management, and real-time pricing. This new era
of smart future grid will lead to major changes in existing technologies at generation, transmission and
distribution levels. The incorporation of renewable energy resources and distribution generators in the existing
grid will increase the complexity, optimization problems and instability of the system. This will lead to a
paradigm shift in the instrumentation and control requirements for Smart Grids for high quality, stable and
reliable electricity supply of power. The monitoring of the grid system state and stability relies on the
availability of reliable measurement of data. In this paper the measurement areas that highlight new
measurement challenges, development of the Smart Meters and the critical parameters of electric energy to be
monitored for improving the reliability of power systems has been discussed.
Study of Macro level Properties of SCC using GGBS and Lime stone powderIJERD Editor
One of the major environmental concerns is the disposal of the waste materials and utilization of
industrial by products. Lime stone quarries will produce millions of tons waste dust powder every year. Having
considerable high degree of fineness in comparision to cement this material may be utilized as a partial
replacement to cement. For this purpose an experiment is conducted to investigate the possibility of using lime
stone powder in the production of SCC with combined use GGBS and how it affects the fresh and mechanical
properties of SCC. First SCC is made by replacing cement with GGBS in percentages like 10, 20, 30, 40, 50 and
by taking the optimum mix with GGBS lime stone powder is blended to mix in percentages like 5, 10, 15, 20 as
a partial replacement to cement. Test results shows that the SCC mix with combination of 30% GGBS and 15%
limestone powder gives maximum compressive strength and fresh properties are also in the limits prescribed by
the EFNARC.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Designing Great Products: The Power of Design and Leadership by Chief Designe...
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
1. International Journal of Engineering Research and Development
e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.com
Volume 11, Issue 04 (April 2015), PP.72-77
72
High Speed Time Efficient Reversible ALU Based Logic Gate
Structure on Vertex Family
Suman Yadav, Manish Saxena
Bansal Institude of Science and Technology
Abstract:- Programmable reversible logic is emerging as a prospective logic design style for implementation in
modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent
advances in reversible logic using and quantum computer algorithms allow for improved computer architecture
and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are
used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output
lines based on programmable select input lines. The proposed ALU design is verified and its advantages over
the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE
software and simulated using MODEL SIM 6.5b.
Keywords:- Reversible Gates, Arithmetic Unit (ALU), Garbage Output, Quantum Cost
I. INTRODUCTION
In modern VLSI system power dissipation is very high due to rapid switching of internal signals. The
complexity of VLSI circuits increases with each year due to packing more and more logic elements into smaller
volumes. Hence power dissipation has become the main area of concern in VLSI design. Reversible logic has its
basics from thermodynamics of information processing. According to this, traditional irreversible circuits
generate heat due to the loss of information during computation. In order to avoid this information loss the
conventional circuits are modeled using reversible logic. Landauer [1961] showed that the circuits designed
using irreversible elements dissipate heat due to the loss of information bits [1]. It is proved that the loss of one
bit of information results in dissipation of KT*log2 joules of heat energy where K is the Boltzmann constant and
T is the temperature at which the operation is performed. Benett [1973] showed that this heat dissipation due to
information loss can be avoided if the circuit is designed using reversible logic gates [2]. A gate is considered to
be reversible only if for each and every input there is a unique output assignment. Hence there is a one to one
mapping between the input and output vectors. A reversible logic gate is an n –input, n- output device indicating
that it has same number of inputs and outputs. A circuit that is built from reversible gates is known as reversible
logic circuit. In this paper, we design a 16 bit reversible ALU that can perform eight operations simultaneously.
The eight operations include addition, subtraction, AND, NAND, OR, NOR and XOR. All the modules are
simulated in modalism SE 6.5 and synthesized using Xilinx ISE 14.1.
II. LITRATURE SURVEY
The research on reversible logic is being pursued towards both design and synthesis. In the synthesis of
reversible logic circuits there have been several interesting attempts in the literature such as the work in [2-3]. A
reversible arithmetic logic unit was designed by Thomsen, Gluck, and Axelsen [4] that was based on the V-
shaped design of the Van Rentergem adder [5]. The ALU had five fixed select lines, and produced the following
logical outputs: ADD, SUB, NSUB, XOR and NOP. The least significant bit comprised of two Feynman gates
and two Toffoli gates. Each additional bit also had two Fredkin gates.
Asher Peres:- This article is concerned with the construction of a quantum-mechanical Hamiltonian
describing a computer. This Hamiltonian generates a dynamical evolution which mimics a sequence of
elementary logical steps. This can be achieved if each logical step is locally reversible (global reversibility is
insufficient). Computational errors due to noise can be corrected by means of redundancy. In particular,
reversible error-correcting codes can be embedded in the Hamiltonian itself. An estimate is given for the
minimum amount of entropy which must be dissipated at a given noise level and tolerated error rate.
Raghava Garipelly et al. “A Review on Reversible Logic
Gates and their Implementation”, International Journal of Emerging Technology and Advanced
Engineering in this paper the Reversible logic is one of the most vital issue at present time and it has different
areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography,
optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata,
communication, computer graphics. It is not possible to realize quantum computing without implementation of
2. High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
73
reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the
circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in
designing of more complex system having reversible circuits as a primitive component and which can execute
more complicated operations using quantum computers. The reversible circuits form the basic building block of
quantum computers as all quantum operations are reversible. This paper presents the data relating to the
primitive reversible gates which are available in literature and helps researches in designing higher complex
computing circuits using reversible gates.
Himanshu Thapliyal et al. “Design of Efficient Reversible Binary Subtractors Based on A New
Reversible Gate”, 2009 IEEE Computer Society Annual Symposium on VLSI, this paper tells about the
extensive applications of Reversible logic in quantum computing, low power VLSI design, quantum dot cellular
automata and optical computing. While several researchers have investigated the design of reversible logic
elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design
of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based
on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to
such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.
Morrison, M. et al. “Design of a novel reversible ALU using an enhanced carry look- ahead adder”
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference Reversible logic is gaining significant
consideration as the potential logic design style for implementation in modern nanotechnology and quantum
computing with minimal impact on physical entropy. Recent advances in reversible logic allow schemes for
computer architectures using improved quantum computer algorithms. Significant contributions have been made
in the literature towards the design of reversible logic gate structures and arithmetic units, however, there are not
many efforts directed towards the design of reversible ALUs. In this work, a novel programmable reversible
logic gate is presented and verified, and its implementation in the design of a reversible Arithmetic Logic Unit is
demonstrated. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead
adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16
were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders
was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is
demonstrated.
III. REVERSIBLE GATES
Reversible logic is gaining importance in areas of CMOS design because of its low power dissipation.
The traditional gates like AND, OR, XOR are all irreversible gates. Consider the case of traditional AND gate.
It consists of two inputs and one output. As a result, one bit is lost each time a computation is carried out.
According to the truth table shown in Fig.1, there are three inputs (1, 0), (0, 1) and (0, 0) that corresponds to an
output zero. Hence it is not possible to determine a unique input that resulted in the output zero. In order to
make a gate reversible additional input and output lines are added so that a one to one mapping exists between
the input and output. This prevents the loss of information that is main cause of power dissipation in irreversible
circuits. The input that is added to an m x n function to make it reversible is known as constant input (CI). All
the outputs of a reversible circuit need not be used in the circuit. Those outputs that are not used in the circuit is
called as garbage output (GO). The number of garbage output for a particular reversible gate is not fixed. The
two main constraints of reversible logic circuit is
Fan out not allowed
Feedbacks or loops not allowed.
BASIC REVERSIBLE GATES
Several reversible gates have come out in the recent years. The most basic reversible gate is the
Feynman gate and is shown in Fig.1. It is the only 2x2 reversible gate available and is commonly used for fan
out purposes. Consider the input B as constant. When B is zero, the gate acts as a copying gate or a buffer where
both the output lines contain the input A. When B is one, the complement of A is obtained at the output Q. The
3x3 reversible gates include Toffoli gate, Fredkin gate, New gate and Peres gate, all of which can be used to
realize various Boolean functions. Fredkin gate is shown in Fig.2.The 4x4 reversible gates include TSG gate,
MKG gate, HNG gate, PFAG gate etc.
3. High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
74
Figure 2: Fredkin gate
Fig.3 shows the TSG gate. Some of the 4x4 gates are designed for implementing some important
combinational functions in addition to the basic functions. Most of the above mentioned gates can be used in the
design of reversible adders.
Figure 3: Peres gate
Several 4x4 and 5x5 gates have been described in the literature targeting low cost and delay which may
be implemented in a programmable manner to produce a high number of logical calculations. The HNG gate,
presented in [10], produces the following logical output calculations:
P A (1) and the logical results based on the input opcodes are presented in Table 1.
(4)
The quantum cost and delay of the HNG is 6. When D = 0,the logical calculations produced on the R and S
outputs are the required sum and carry-out operations for a full adder. The quantum representation of the
HNG is presented in Fig. 4.
4. High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
75
A new programmable 4x4 reversible logic structure – Peres And-Or(PAOG) gate – is presented
which produces outputs
Fig. 5 shows the block diagram of the PAOG gate. This gate is an extension of the Peres gate for ALU
realization.
Figure 5: Block Diagram of the PAOG
The ALU utilizes the PAOG gate and HNG gate to produce six logical calculations: ADD, SUB, AND,
NAND, OR and NOR. The cost and delay calculations are identical to the ALU in Fig. 6.2. The proposed ALU
is shown in Fig. 16,
5. High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
76
V. SIMULATION RESULTS
Fig.6 shows the output of 4 bit reversible ALU for different operations. The inputs to this module are
the 4 bit data A and B and a control signal S0, S1, S 2, S3, S 4, S5 . The control signals select the type of
operation to be performed on the data bits shown in Table 1.
The project was simulated with the help of the Xilinx ISE 9.2 tool. Remember that the real inputs for
this project were the 4 bits A and B and the 1 bit Cin (Carry In) and 4 control signals S) S0, S1, S 2, S3, S 4 .
The rest (g1 to g21) are only the ancilla bits and they need to remain always in zero. Figure 7 shows the RTL
schematic of ALU as well as Figure 8 shows the simulation waveform for the ALU.
Table 2: Syntheses Result for Reversible ALU with different Device Family
Device Number of Number Maximum
Family Slices Used as Combinatio
LUTs Logic n Path delay
Spartan 3 3 5 10.840ns
Virtex-6 4 4 1.123ns
Virtex-7 4 4 1.051ns
Figure 7: RTL schematic for reversible ALU
Figure 8: Simulation Wave for Reversible Arithmetic Logic Operations
6. High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
77
VI. CONCLUSION
The 4bit reversible ALU is designed by integrating various sub modules that includes adder/subtract or,
and logical unit. The logical unit performs AND, OR, NOR, XOR, NAND. The performance evaluation of the
various sub modules are carried out using Modalism 6.5 tools and it was found that the circuits designed using
reversible logic showed a reduced delay and power. As a future work more arithmetic and logical function can
be used.
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