This document proposes designing a 4x4 Vedic multiplier using reversible logic gates. It discusses how traditional multipliers have high area, latency and power consumption. The Vedic multiplication algorithm called Urdhva Tiryagbhyam can increase speed compared to other techniques. Implementing this algorithm with reversible logic gates can further reduce area and power dissipation. A 4x4 Vedic multiplier is designed using reversible Peres and HNG gates to realize the multiplication, with benefits of constant inputs, low garbage outputs, quantum cost, area and speed compared to other reversible logic multipliers.

2. Design of High Speed, Area Efficient, Low Power Vedic
Multiplier using Reversible Logic Gate

3. ABSTRACT
 Multipliers have large area, long latency and consume
considerable power.
 Hence good multiplier architecture increases the efficiency
and performance of a system. Vedic multiplier is one such
high speed, low area multiplier architecture.
 Further implementing this in reversible logic reduces
power.
 a 4 X 4 Vedic multiplier is designed using reversible logic
gates which is efficient in terms of constant inputs, garbage
outputs, quantum cost, area, speed and power.

4. INTRODUCTION
 Existing Method.
 Poposed Method.
 Reversible Logic.
 Urdhva Tiryagbhyam Multiplication.
 Conclusion.
.

5. Existing Method
 The multipliers are the most important part of all digital
signal processors; they are very important in realizing
many important functions such as fast Fourier
transforms and convolutions.
 Since a processor spends considerable amount of time in
performing multiplication, an improvement in
multiplication speed can greatly improve system
performance.
 Multiplication can be implemented using many
algorithms such as array, booth, carry save, and Wallace
tree algorithms.

6. Proposed Method
 Reversible logic is a promising area of study with regard
to the future low power technology.
 the implementation of reversible logic Urdhava
Triyagbhyam multiplier which has two main features.
 One is implementing the multiplier using vedic sutra
increases the speed of the multiplication.
 Second is the use of reversible logic reduces the area
and the hence the power dissipation.

7. Reversible Logic
 Reversible logic is a promising computing design
paradigm which presents a method for constructing
computers that produce no heat dissipation.
 Reversible computing emerged as a result of the
application of quantum mechanics principles towards the
development of a universal computing machine.
 A reversible logic gate is an N-input N-output logic
device that provides one to one mapping between the
input and the output.

8. The following are the important design constraints for
reversible logic circuits.
 I. Reversible logic gates do not allow fan-outs.
 2.Reversible logic circuits should have minimum quantum
cost.
 3.The design can be optimized so as to produce minimum
number of garbage outputs.
 4.The reversible logic circuits must use minimum number
of constant inputs.
 5.The reversible logic circuits must use a minimum logic
depth or gate levels.

9. Peres gate and HNG gate
 It is a 3x3 gate and its logic circuit is as shown in the
figure. It is used to realize various Boolean functions
such as AND, XOR.
HNG gate
 It is a 4x4 gate and its logic circuit is as shown in the
figure.
 It is used for designing ripple carry adders. It can
produce both sum and carry in a single gate thus
minimizing the garbage and gate counts.

10. Structure of peres gate and Hng gate

11. Urdhva Tiryagbhyam multiplication
 The “Urdhva Tiryagbhyam” Sutra is a general
multiplication formula applicable to all cases of
multiplication such as binary, hex, decimal and octal.
 The Sanskrit word “Urdhva” means “Vertically” and
“Tiryagbhyam‟ means “crosswise”.
 The speed of the multiplier is increased considerably
when compared to other techniques.

14. Example of Urdhva Tiryagbhyam algorithm

15. 2 X 2 Urdhva Tiryagbhyam algorithm

16.  The 2 X 2 Urdhva Tiryagbhyam multiplier using
conventional logic will have 4 outputs. The logical
expressions are given below.
 q0= a0.b0
 ql= (a1.b0) xor (a0.bl)
 q2= (a0.al.b0.bl) xor (al.bl)
 q3= a0.al.b0.bl
 The reversible logic implementation of the above
expressions requires four peres gate and one Feynmen
(CNOT) gate.

17. 4Bit ripple carry using Hng gate

18. 4Bit Vedic multiplier

19. Conclusion
 First 2X2 UT multiplier is designed using Peres gate and
Feynmen gate.
 The ripple carry adders which were required for adding
the partial products were constructed using HNG gates.
 This design has high speed, smaller area and less power
consumption when compared with other reversible logic
multipliers.