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Broadcom Accelerates PCIe/CXL
Roadmap to Enable the Open
AI Ecosystem
Broadcom Accelerates PCIe/CXL Roadmap
to Enable the Open AI Ecosystem
Rick Kutcipal, Product Planner, Broadcom
Sreeni Bagalkote, Product Planner, Broadcom
AI
Broadcom PCIe & CXL Switches
Predictable high-quality execution for 10+ Years
Increasing lane counts for AI systems
Simple fanout  Internal fabric
86x bandwidth increase
Low power / lane
Atlas 3: PCIe Gen 6 & CXL 3.1 Switch
144 lane switch in 5nm
technology
Peer-to-Peer across virtual
hierarchies
CXL.mem, CXL.cache, & CXL
fabric support
Best in class SerDes (> 36db
margin)
Embedded PCIe analyzer
Dec 2024 Samples
PCIe Gen 5  Gen 6 Complexity
Features Gen 1 Gen 2 Gen 3 Gen 4 Gen 5 Gen 6 Complexity
Physical
Bus Freq. (GHz) 2.5 5 8 16 32 32
High Complexity
Throughput (MB/s) 4 8 16 32 64 128
Physical Encoding NRZ NRZ + PAM4
Link
Link Data Integrity ECRC ECRC + FEC
High Complexity
Wire Protocol Variable length packets Variable + Fixed length (Flit)
Replay Protocol Packet ACK/NAK Packet ACK/NAK + Flit-based ACK
Transaction
Packet Formats 4 Header Types, 22 Packet types 7 Header Types, 61 Packet types
High Complexity
Credit Protocol 3 credit types
3 credit + Flit credits, 2 shared
credits
Encryption Support - Link and Stream(end-to-end)
PCIe Gen 5  Gen 6 transition is highly complex
• PCI Gen 6 / CXL 3.1
• Opening to all ecosystem
partners for interop
• Available Now
• Contact for details
rick.kutcipal@broadcom.com
sreenivas.bagalkote@broadcom.c
om
Atlas 3 FPGA Platform Available for Interop
1
2
3 4
5
6
7
8
9
1 Atlas 3 FPGA platform
2 PCIe subsystem
3 CXL subsystem
4 ARM 15
5 Sprite daughter card
6 Debug daughter card
7 Drive connection daughter card
8 Host connection daughter card
9 Atlas 3 FPGA setup
Atlas 3 Rapid Development Kit (RDK)
• Multi-host PCIe & CXL topologies
• Create fabric using multiple RDKs
• CXL memory modules via riser card
• Allows out-of-band BMC connection
• Validated with Broadcom Gen 6 retimer
Available Dec 2024
Atlas Enables Open AI Architectures
CPU
CPU CPU
CPU
GPU
GPU GPU
GPU GPU
GPU GPU
GPU
CXL Memory
Ethernet NIC
Storage
CXL Memory
Ethernet NIC
Storage
Open internal AI fabric
Open scale-up fabric
Announcing Atlas 4 – PCIe Gen 7 & CXL
Switch
128 Gb/s
Broadcom PAM4 SerDes
3nm Process Technology
Sample Availability Dec 2025
Atlas4
AI
Thank you!

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Broadcom PCIe & CXL Switches OCP Final.pptx

  • 1. Broadcom Accelerates PCIe/CXL Roadmap to Enable the Open AI Ecosystem
  • 2. Broadcom Accelerates PCIe/CXL Roadmap to Enable the Open AI Ecosystem Rick Kutcipal, Product Planner, Broadcom Sreeni Bagalkote, Product Planner, Broadcom AI
  • 3. Broadcom PCIe & CXL Switches Predictable high-quality execution for 10+ Years Increasing lane counts for AI systems Simple fanout  Internal fabric 86x bandwidth increase Low power / lane
  • 4. Atlas 3: PCIe Gen 6 & CXL 3.1 Switch 144 lane switch in 5nm technology Peer-to-Peer across virtual hierarchies CXL.mem, CXL.cache, & CXL fabric support Best in class SerDes (> 36db margin) Embedded PCIe analyzer Dec 2024 Samples
  • 5. PCIe Gen 5  Gen 6 Complexity Features Gen 1 Gen 2 Gen 3 Gen 4 Gen 5 Gen 6 Complexity Physical Bus Freq. (GHz) 2.5 5 8 16 32 32 High Complexity Throughput (MB/s) 4 8 16 32 64 128 Physical Encoding NRZ NRZ + PAM4 Link Link Data Integrity ECRC ECRC + FEC High Complexity Wire Protocol Variable length packets Variable + Fixed length (Flit) Replay Protocol Packet ACK/NAK Packet ACK/NAK + Flit-based ACK Transaction Packet Formats 4 Header Types, 22 Packet types 7 Header Types, 61 Packet types High Complexity Credit Protocol 3 credit types 3 credit + Flit credits, 2 shared credits Encryption Support - Link and Stream(end-to-end) PCIe Gen 5  Gen 6 transition is highly complex
  • 6. • PCI Gen 6 / CXL 3.1 • Opening to all ecosystem partners for interop • Available Now • Contact for details rick.kutcipal@broadcom.com sreenivas.bagalkote@broadcom.c om Atlas 3 FPGA Platform Available for Interop 1 2 3 4 5 6 7 8 9 1 Atlas 3 FPGA platform 2 PCIe subsystem 3 CXL subsystem 4 ARM 15 5 Sprite daughter card 6 Debug daughter card 7 Drive connection daughter card 8 Host connection daughter card 9 Atlas 3 FPGA setup
  • 7. Atlas 3 Rapid Development Kit (RDK) • Multi-host PCIe & CXL topologies • Create fabric using multiple RDKs • CXL memory modules via riser card • Allows out-of-band BMC connection • Validated with Broadcom Gen 6 retimer Available Dec 2024
  • 8. Atlas Enables Open AI Architectures CPU CPU CPU CPU GPU GPU GPU GPU GPU GPU GPU GPU CXL Memory Ethernet NIC Storage CXL Memory Ethernet NIC Storage Open internal AI fabric Open scale-up fabric
  • 9. Announcing Atlas 4 – PCIe Gen 7 & CXL Switch 128 Gb/s Broadcom PAM4 SerDes 3nm Process Technology Sample Availability Dec 2025 Atlas4 AI