Mirabilis Design provides the VisualSim Versal Library that enable System Architect and Algorithm Designers to quickly map the signal processing algorithms onto the Versal FPGA and define the Fabric based on the performance. The Versal IP support all the heterogeneous resource.
The increasing demand for computing power in fields such as biology, finance, machine learning is pushing the adoption of reconfigurable hardware in order to keep up with the required performance level at a sustainable power consumption. Within this context, FPGA devices represent an interesting solution as they combine the benefits of power efficiency, performance and flexibility. Nevertheless, the steep learning curve and experience needed to develop efficient FPGA-based systems represents one of the main limiting factor for a broad utilization of such devices.
In this talk, we present CAOS, a framework which helps the application designer in identifying acceleration opportunities and guides through the implementation of the final FPGA-based system. The CAOS platform targets the full stack of the application optimization process, starting from the identification of the kernel functions to accelerate, to the optimization of such kernels and to the generation of the runtime management and the configuration files needed to program the FPGA.
How to create innovative architecture using VisualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
How to create innovative architecture using ViualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
Please find our webinar video - How to create innovative architecture using ViualSim? at the last slide.
How to create innovative architecture using VisualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
The increasing demand for computing power in fields such as biology, finance, machine learning is pushing the adoption of reconfigurable hardware in order to keep up with the required performance level at a sustainable power consumption. Within this context, FPGA devices represent an interesting solution as they combine the benefits of power efficiency, performance and flexibility. Nevertheless, the steep learning curve and experience needed to develop efficient FPGA-based systems represents one of the main limiting factor for a broad utilization of such devices.
In this talk, we present CAOS, a framework which helps the application designer in identifying acceleration opportunities and guides through the implementation of the final FPGA-based system. The CAOS platform targets the full stack of the application optimization process, starting from the identification of the kernel functions to accelerate, to the optimization of such kernels and to the generation of the runtime management and the configuration files needed to program the FPGA.
How to create innovative architecture using VisualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
How to create innovative architecture using ViualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
Please find our webinar video - How to create innovative architecture using ViualSim? at the last slide.
How to create innovative architecture using VisualSim?Deepak Shankar
In this presentation, we will get you started on using VisualSim Architect to conduct performance analysis, power measurement and functional validation. You will learn advanced concepts of system modeling and how to apply VisualSim Architect for a variety of applications.
Highlights include the application for both System-on-Chip and Large Systems including Designing memory interfaces using DDR3 and LPDDR3.
VisualSim Architect is used by systems and semiconductor companies to validate and analyze the specification of the product. The environment offers an easy-to-use methodology, huge library of technology components, extremely fast simulator and a huge reports list.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
Task allocation on many core-multi processor distributed systemDeepak Shankar
Migration of software from a single to multi-core, single to multi-thread, and integrated into a distributed system requires a knowledge of the system and scheduling algorithms. The system consists of a combination of hardware, RTOS, network, and traffic profiles. Of the 100+ popular scheduling algorithms, the majority use First Come-First Server with priority and preemption, Weight Round Robin, and Slot-based. The task allocation must take into consideration a number of factors including the hardware configuration, the RTOS scheduling, task dependency, parallel partitioning, shared resources, and memory access. Additionally, embedded system architectures always have the possibility of using custom hardware to implement tasks that may be associated with Artificial Intelligence, diagnostic or image processing.
In this Webinar, we will show you how to conduct trade-offs using a system model of the tasks and the target resources. You will learn to make decisions based on the hardware and network statistics. The statistics will assist in identifying deadlocks, bottlenecks, possible failures and hardware requirements. To estimate the best task allocation and partitioning, a discrete-event simulation with both time- and quantity-shared resource modeling is essential. The software must be defined as a UML or a task graph.
Web: www.mirabilisdesign.com
Webinar Youtube Link: https://youtu.be/ZrV39SYTWSc
Accelerated development in Automotive E/E Systems using VisualSim ArchitectDeepak Shankar
The recent trends and developments in the automotive sector towards fully autonomous diving system and vehicle to vehicle (V2V) communication would mean a drastic increase in the number of sensors, increased number of ECUs, increased concern for safety and security. This calls for the need to perform thorough evaluations on the target system architecture, at all levels - Hardware, Software and Network. During this webinar, we show how we evaluate each of these aspects of the Automotive E/E system and take a closer look at the performance, power and functional correctness of each of the auto subsystems. We will also inject faults into the demo model, which will tell us how the automotive system would perform under failure.
The webinar also showcases various Use case examples, which includes - comparison of TSN Standards, modelling of various topology, task graph modelling, glimpses into TC10 sleep-wakeup standard and integrated software.
This slides show how to utilize real-world applications to teach early architecture exploration of electronics, embedded systems, software/firmware and semiconductor using visualsim.
Using a Field Programmable Gate Array to Accelerate Application PerformanceOdinot Stanislas
Intel s'intéresse tout particulièrement aux FPGA et notamment au potentiel qu'ils apportent lorsque les ISV et développeurs ont des besoins très spécifiques en Génomique, traitement d'images, traitement de bases de données, et même dans le Cloud. Dans ce document vous aurez l'occasion d'en savoir plus sur notre stratégie, et sur un programme de recherche lancé par Intel et Altera impliquant des Xeon E5 équipés... de FPGA
Intel is looking at FPGA and what they bring to ISVs and developers and their very specific needs in genomics, image processing, databases, and even in the cloud. In this document you will have the opportunity to learn more about our strategy, and a research program initiated by Intel and Altera involving Xeon E5 with... FPGA inside.
Auteur(s)/Author(s):
P. K. Gupta, Director of Cloud Platform Technology, Intel Corporation
Using VisualSim Architect for Semiconductor System AnalysisDeepak Shankar
Mirabilis Design provides architecture exploration software for semiconductor, electronics and embedded software. Using this modeling and simulation solution, designers could trade-off power vs performance, partition into hardware-software, optimize for timing, minimize power consumption, functional analysis and evaluate the quality of the system in the event of a failure. The outcome of this early exploration is a highly validated specification, a reference design for prospective customers to evaluate and data for certification purposes.
VisualSim has a large library of components (stochastic, hardware, software, network and RTOS) that is used to assemble models of the entire system, extremely fast and handle level of abstraction from stochastic to timing-accurate. These models are simulated against workloads and use-cases and the generated reports are used to make architecture decisions.
In Electronic System design, modeling abstraction is a powerful technique that involves creating simplified representations of complex electronic systems.
VisualSim Architect allows designers to create more manageable, modular, scalable, and robust electronic systems that meet the requirements of real-world applications. By leveraging abstraction, designers can focus on the critical aspects of a system's functionality, behavior, and interface, and effectively communicate design concepts and make informed decisions.
Develop High-bandwidth/low latency electronic systems for AI/ML applicationDeepak Shankar
the architecture exploration required to accurately size and implement AI/ML platforms for a wide-range of applications in automotive, radar and high-performance computing.
Looking for Full-time opportunities after graduation in December'19. Interested in Hardware Engineer roles and Embedded Systems roles. Experienced in Computer Architecture, Embedded Systems, Digital Design, Digital Testing and Design Verification.
Dataplane networking acceleration with OpenDataplane / Максим Уваров (Linaro)Ontico
HighLoad++ 2017
Зал «Москва», 7 ноября, 13:00
Тезисы:
http://www.highload.ru/2017/abstracts/2909.html
OpenDataPlane (ODP, https://www.opendataplane.org) является open-source-разработкой API для сетевых data plane-приложений, представляющий абстракцию между сетевым чипом и приложением. Сейчас вендоры, такие как TI, Freescale, Cavium, выпускают SDK с поддержкой ODP на своих микросхемах SoC. Если проводить аналогию с графическим стеком, то ODP можно сравнить с OpenGL API, но только в области сетевого программирования.
...
The increasing demand for computing power in fields such as biology, finance, machine learning is pushing the adoption of reconfigurable hardware in order to keep up with the required performance level at a sustainable power consumption. Within this context, FPGA devices represent an interesting solution as they combine the benefits of power efficiency, performance and flexibility. Nevertheless, the steep learning curve and experience needed to develop efficient FPGA-based systems represents one of the main limiting factor for a broad utilization of such devices.
In this talk, we present CAOS, a framework which helps the application designer in identifying acceleration opportunities and guides through the implementation of the final FPGA-based system. The CAOS platform targets the full stack of the application optimization process, starting from the identification of the kernel functions to accelerate, to the optimization of such kernels and to the generation of the runtime management and the configuration files needed to program the FPGA.
How to achieve 95%+ Accurate power measurement during architecture exploration? Deepak Shankar
During the conceptualization and architectural exploration phases, it is crucial to assess the power budget.
Would you like to accurately measure the:
1. Power consumed for a proposed embedded software or firmware?
2. Savings of a Power Management Algorithm prior to development?
3. Power impact of hardware configuration change?
4. Trade-off between Power and Performance?
5. Temperature, heat, peak power and cumulative power?
Get ready to dive into the exciting world of IoT data processing! 🌐📊
Join us for a thought-provoking webinar on "Processing: Turning IoT Data into Intelligence" hosted by industry visionary Deepak Shankar, founder of Mirabilis Design. Discover how to harness the potential of IoT devices by strategically choosing processors that optimize power, performance, and space.
In this engaging session, you'll explore key insights:
✅ Impact of processor architecture on Power-Performance-Area optimization
✅ Enabling AI and ML algorithms through precise compute and storage requirements
✅ Future trends in IoT hardware innovation
✅ Strategies for extending battery life and cost prediction through system design
Don't miss the chance to learn how to leverage a single IoT Edge processor for multiple applications and much more. This is your opportunity to gain a competitive edge in the evolving IoT landscape.
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Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
Task allocation on many core-multi processor distributed systemDeepak Shankar
Migration of software from a single to multi-core, single to multi-thread, and integrated into a distributed system requires a knowledge of the system and scheduling algorithms. The system consists of a combination of hardware, RTOS, network, and traffic profiles. Of the 100+ popular scheduling algorithms, the majority use First Come-First Server with priority and preemption, Weight Round Robin, and Slot-based. The task allocation must take into consideration a number of factors including the hardware configuration, the RTOS scheduling, task dependency, parallel partitioning, shared resources, and memory access. Additionally, embedded system architectures always have the possibility of using custom hardware to implement tasks that may be associated with Artificial Intelligence, diagnostic or image processing.
In this Webinar, we will show you how to conduct trade-offs using a system model of the tasks and the target resources. You will learn to make decisions based on the hardware and network statistics. The statistics will assist in identifying deadlocks, bottlenecks, possible failures and hardware requirements. To estimate the best task allocation and partitioning, a discrete-event simulation with both time- and quantity-shared resource modeling is essential. The software must be defined as a UML or a task graph.
Web: www.mirabilisdesign.com
Webinar Youtube Link: https://youtu.be/ZrV39SYTWSc
Accelerated development in Automotive E/E Systems using VisualSim ArchitectDeepak Shankar
The recent trends and developments in the automotive sector towards fully autonomous diving system and vehicle to vehicle (V2V) communication would mean a drastic increase in the number of sensors, increased number of ECUs, increased concern for safety and security. This calls for the need to perform thorough evaluations on the target system architecture, at all levels - Hardware, Software and Network. During this webinar, we show how we evaluate each of these aspects of the Automotive E/E system and take a closer look at the performance, power and functional correctness of each of the auto subsystems. We will also inject faults into the demo model, which will tell us how the automotive system would perform under failure.
The webinar also showcases various Use case examples, which includes - comparison of TSN Standards, modelling of various topology, task graph modelling, glimpses into TC10 sleep-wakeup standard and integrated software.
This slides show how to utilize real-world applications to teach early architecture exploration of electronics, embedded systems, software/firmware and semiconductor using visualsim.
Using a Field Programmable Gate Array to Accelerate Application PerformanceOdinot Stanislas
Intel s'intéresse tout particulièrement aux FPGA et notamment au potentiel qu'ils apportent lorsque les ISV et développeurs ont des besoins très spécifiques en Génomique, traitement d'images, traitement de bases de données, et même dans le Cloud. Dans ce document vous aurez l'occasion d'en savoir plus sur notre stratégie, et sur un programme de recherche lancé par Intel et Altera impliquant des Xeon E5 équipés... de FPGA
Intel is looking at FPGA and what they bring to ISVs and developers and their very specific needs in genomics, image processing, databases, and even in the cloud. In this document you will have the opportunity to learn more about our strategy, and a research program initiated by Intel and Altera involving Xeon E5 with... FPGA inside.
Auteur(s)/Author(s):
P. K. Gupta, Director of Cloud Platform Technology, Intel Corporation
Using VisualSim Architect for Semiconductor System AnalysisDeepak Shankar
Mirabilis Design provides architecture exploration software for semiconductor, electronics and embedded software. Using this modeling and simulation solution, designers could trade-off power vs performance, partition into hardware-software, optimize for timing, minimize power consumption, functional analysis and evaluate the quality of the system in the event of a failure. The outcome of this early exploration is a highly validated specification, a reference design for prospective customers to evaluate and data for certification purposes.
VisualSim has a large library of components (stochastic, hardware, software, network and RTOS) that is used to assemble models of the entire system, extremely fast and handle level of abstraction from stochastic to timing-accurate. These models are simulated against workloads and use-cases and the generated reports are used to make architecture decisions.
In Electronic System design, modeling abstraction is a powerful technique that involves creating simplified representations of complex electronic systems.
VisualSim Architect allows designers to create more manageable, modular, scalable, and robust electronic systems that meet the requirements of real-world applications. By leveraging abstraction, designers can focus on the critical aspects of a system's functionality, behavior, and interface, and effectively communicate design concepts and make informed decisions.
Develop High-bandwidth/low latency electronic systems for AI/ML applicationDeepak Shankar
the architecture exploration required to accurately size and implement AI/ML platforms for a wide-range of applications in automotive, radar and high-performance computing.
Looking for Full-time opportunities after graduation in December'19. Interested in Hardware Engineer roles and Embedded Systems roles. Experienced in Computer Architecture, Embedded Systems, Digital Design, Digital Testing and Design Verification.
Dataplane networking acceleration with OpenDataplane / Максим Уваров (Linaro)Ontico
HighLoad++ 2017
Зал «Москва», 7 ноября, 13:00
Тезисы:
http://www.highload.ru/2017/abstracts/2909.html
OpenDataPlane (ODP, https://www.opendataplane.org) является open-source-разработкой API для сетевых data plane-приложений, представляющий абстракцию между сетевым чипом и приложением. Сейчас вендоры, такие как TI, Freescale, Cavium, выпускают SDK с поддержкой ODP на своих микросхемах SoC. Если проводить аналогию с графическим стеком, то ODP можно сравнить с OpenGL API, но только в области сетевого программирования.
...
The increasing demand for computing power in fields such as biology, finance, machine learning is pushing the adoption of reconfigurable hardware in order to keep up with the required performance level at a sustainable power consumption. Within this context, FPGA devices represent an interesting solution as they combine the benefits of power efficiency, performance and flexibility. Nevertheless, the steep learning curve and experience needed to develop efficient FPGA-based systems represents one of the main limiting factor for a broad utilization of such devices.
In this talk, we present CAOS, a framework which helps the application designer in identifying acceleration opportunities and guides through the implementation of the final FPGA-based system. The CAOS platform targets the full stack of the application optimization process, starting from the identification of the kernel functions to accelerate, to the optimization of such kernels and to the generation of the runtime management and the configuration files needed to program the FPGA.
Similar to Mirabilis_Design AMD Versal System-Level IP Library (20)
How to achieve 95%+ Accurate power measurement during architecture exploration? Deepak Shankar
During the conceptualization and architectural exploration phases, it is crucial to assess the power budget.
Would you like to accurately measure the:
1. Power consumed for a proposed embedded software or firmware?
2. Savings of a Power Management Algorithm prior to development?
3. Power impact of hardware configuration change?
4. Trade-off between Power and Performance?
5. Temperature, heat, peak power and cumulative power?
Get ready to dive into the exciting world of IoT data processing! 🌐📊
Join us for a thought-provoking webinar on "Processing: Turning IoT Data into Intelligence" hosted by industry visionary Deepak Shankar, founder of Mirabilis Design. Discover how to harness the potential of IoT devices by strategically choosing processors that optimize power, performance, and space.
In this engaging session, you'll explore key insights:
✅ Impact of processor architecture on Power-Performance-Area optimization
✅ Enabling AI and ML algorithms through precise compute and storage requirements
✅ Future trends in IoT hardware innovation
✅ Strategies for extending battery life and cost prediction through system design
Don't miss the chance to learn how to leverage a single IoT Edge processor for multiple applications and much more. This is your opportunity to gain a competitive edge in the evolving IoT landscape.
Evaluating UCIe based multi-die SoC to meet timing and power Deepak Shankar
Multi-die designs allow systems engineering to pack more functionality with different timing and power constraints into a single package. Older generation multi-die split the dies into high-speed and low speed. Newer, high-performance multi-die System-on-Chip (SoC) requires interaction between memories across the die-to-die interfaces. Connections between dies must be power efficient, have low latency, provide high bandwidth to transfer massive amounts of data, and deliver error-free operation. The distribution of cores, deep neural networks and AI engines across these dies makes it extremely hard to predict the expected end-to-end latency, power spikes and effective bandwidth. Moreover, Multi-die architectures have evolved from proprietary to industry standard UCIe.
This Webinar looks at the system-wide view of performance and power in a multi-die SOC. We will be showcasing a few use cases that combines various types of processing engines across PCIe and interconnected UCIe. This modeling effort will present the user with different system performance and system architecture models and a guide on how to best bring different aspects of their design together in a holistic way that is optimized for power, timing and functionality.
During the Webinar, users can follow along using VisualSim Cloud. To get started with VisualSim Cloud, users can register and receive a login at https://www.mirabilisdesign.com/visualsim-cloud-login/. Once you receive the login, follow the instructions, and open the models provided in the Template pull-down. More instructions will be provided at the start of the Webinar.
ROLE OF DIGITAL SIMULATION IN CONFIGURING NETWORK PARAMETERSDeepak Shankar
Selecting the right Ethernet standard and configuring all the network devices in the embedded systems accurately is an extremely hard and rigorous job. The configuration depends on the topology, workloads of the connected devices, processing overhead at the switches, and the external interfaces. Network calculus, mathematical models and analytical techniques provide worst case execution time (WCET), but their probability of activity is extremely wide. This leads to overdesign which leads to higher costs, power consumption, weight, and size. Simulating the network is the best way to measure the throughput of the entire system. Digital system simulation provides better latency and throughput accuracy, but the accuracy is still limited because it does not consider the latency associated with the network OS, cybersecurity processing and scheduling. In many cases, these factors can reduce the throughput by 20-40%.
In this paper, we will present our research on modeling the entire Ethernet network, including the workloads, network flow control, scheduling, switch hardware, and software. To substantially increase the coverage and compare topologies, we have developed a set of benchmarks that provides coverage for different combination of deterministic, rate-constrained, and best effort traffic. During the presentation, we will cover the benchmarks, the list of attributes required to accurately model the traffic, nodes, switches, and the scheduler settings. We will also look at the statistics and reports required to make the configuration decision. In addition, we will discuss how the model must be constructed to study the impact of future requirements, failures, network intrusions, and security detection schemes.
Key Takeaways:
1. Learn how to efficiently use network simulation to design Ethernet systems
2. Develop a reusable benchmark and associated statistics to test different configurations
3. The role and impact of the CDT slots, guard band, send slope, idle slope, shuffle scheduling, flow control and virtual channels
Compare Performance-power of Arm Cortex vs RISC-V for AI applications_oct_2021Deepak Shankar
Abstract: In the Webinar, we will show you how to construct, simulate, analyze, validate, optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53, SiFive u74, ARM Cortex A77, and other vendor cores. The system will be built around custom switches, Ingress/Egress buffers, credit flow control, AI accelerators, NoC and AMBA AXI buses with multi-level caches, DDR4 DRAM and DMA. The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth. The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.
Selection of cores is a combination of financial and technical bias. Technical comparison of processor cores requires the understanding of the workload, task partitioning and cache-memory structure. A core must be evaluated in the context of the target application. To evaluate these selections, architecture simulation software must be fortified with a library of Intellectual property for power and timing accurate processor cores, simulator at 100 million events per second, peripherals, and all possible traffic distributions
Key Takeaways:
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model
Speaker Bio:
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. He has been an FPGA Solution Architect and Xilinx FPGA Trainer for a number of years, supporting companies, research centers and universities in China and Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP. Alex has also been engaged with a variety of FPGA-based Hardware Emulation System and over ten years in ASIC/SoC design and verification engineer.
Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
Energy efficient AI workload partitioning on multi-core systemsDeepak Shankar
o create an AI system, the semiconductor, software, and systems team need to work together. Multi-core systems can provide extremely low latency and higher throughput at lower power consumption. But concurrent access to shared resources by multiple of AI workloads running on different cores can create higher worst-case execution time (WCET) and causes multiple system failures. Architecture exploration can be used to efficiently balance the compute, communication, synchronization, and storage. In this Webinar, we will be using Workloads from automotive, and data centers to demonstrate the methodology.
VisualSim Architect enables designers to assemble architecture models that extend from the smallest IoT to full automotive, and Radar systems to Data Centers. These models will include any combination of software, processors, ECU, RTOS and networks. Using this platform, software designer can explore the partitioning of the AI tasks (software or model) on to cores based on the latency, bandwidth, and power constraints. Within the IoT, the processor, A/D, Bluetooth and software can be modeled while an automotive design will require the network, ECU and firmware. Both have a unique mechanism to define the traffic, test scenarios and AI workloads. Hardware engineers can select cores, cores per cluster, cache hierarchy, memory controller, accelerators, and the interface topology. Software engineers can tune the partitioning, synchronization overhead, memory access schedules and scheduling.
Capacity Planning and Power Management of Data Centers. Deepak Shankar
Key Points discussed in this webinar are:
1.How dynamic simulation can replace traditional network simulations that are slow and lack configuration and visibility to analyze performance.
2.How to avoid over or under design, cost increases, and delays.
3.How an architectural model can be used to test the capacity and power requirements of your data center or your server.
Contact us at info@mirabilisdesign.com for any queries.
Analytical, prototyping, model-based systems engineering and custom discrete-event model development of automotive networks are inaccurate, expensive, and takes too long to do detailed routing analysis, Quality-of-Service (QoS) trade-off, and bandwidth exploration. To capture the nuances of QoS, scheduling, buffer management, and network topologies, these solutions require a considerable amount of time, costs, and customization. To achieve the reliability of wiring harness, the latency and bandwidth measurements of automotive networks must be accurate, tested for failure conditions, and simulated for security breaches, traffic spikes, and translations.
In the design of electronics and semiconductors, challenges are compounded by the integration of AI, multi-core, real-time software, network, connectivity, diagnostics, and security. Performance limits, battery life, and cost are adoption barriers. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle.
Continuous verification from planning to development addresses the multi-discipline needs of hardware, software, and networks. This unique approach accelerates the design phase, defines the test efforts, and finds defects during specification. Architecture modeling is required to meet timing deadlines, generate the lowest power consumption, and attain the highest Quality-of-Service. optimize the electronic design system and designing of custom components.
Using ai for optimal time sensitive networking in avionicsDeepak Shankar
The IEEE 802.1 Time-Sensitive Networking is a standard technology to provide deterministic
routing or transmission of packets on standard Ethernet. By reserving resources for critical traffic,
and applying various queuing and shaping techniques, TSN achieves zero congestion loss for
critical data traffic. This, in turn, allows TSN to guarantee a worst-case end-to-end latency for
critical data. TSN also provides ultra-reliability for data traffic via a data packet level reliability
mechanism as well as protection against bandwidth violation, malfunctioning, malicious attacks,
etc. TSN includes reliable time synchronization, a profile of IEEE 1588, which provides the basis
for many other TSN functions.
Introduction to Architecture Exploration of Semiconductor, Embedded Systems, ...Deepak Shankar
- Identify design challenges, trade-offs, and exploration.
- Construct an architecture model using data available in documents, spreadsheets, existing code, datasheets, and future concepts.
- Analyze the model to determine the cause of a bottleneck or performance degradation
Webinar on Latency and throughput computation of automotive EE networkDeepak Shankar
This solution enables Architects to conduct trade-off on early planning, system sizing and network topology planning. This is part one in a three series that covers systems engineering exploration of Automotive EE Systems. technologies studied in this session include FlexRay, CAN, CAn_FD, TSN. Ethernet, ECU, Brake System, power Supply electronics, Li-Ion Batteries, ADAS and AUTOSAR.
Webinar: Detecting Deadlocks in Electronic Systems using Time-based SimulationDeepak Shankar
Webinar: Detecting Deadlocks in Electronic Systems
Date: Nov 13th, 2019
Europe/ India Time: 11 AM CEST / 2:30 PM IST
US Time: 10 AM PT/ 1 PM ET
Register For the Webinar
Join Deepak Shankar, Founder of Mirabilis Design,
on Deadlock Detection of task graphs, using Discrete-Event Simulation.
on Thursday Nov 13th 2019
Europe/ India Time: 11 AM CEST / 2:30 PM IST
US Time: 10 AM PT/ 1 PM ET
Register For the Webinar
In Part One on Functional Analysis and Safety, we covered architecture modeling, fault injection, identification and resolution. View this Webinar, at the Mirabilis Design Video Channel. In Part Two, we focus on detecting deadlocks in systems that are time-variant. Traditional methods such as Ho-Ramamoorthy check for deadlocks in static directed graphs. In real systems, deadlocks occur from dependents missing deadlines, non-availability of resources from dependency and processing needs, multiple concurrent resource requests, criss-cross requests, stringent flow control, limited credit policies and buffer overflow. These require a dynamic, time-based simulation model to evaluate and detect deadlocks. In this Webinar, we use VisualSim Architect to assemble the task graph of the electronic; run use-cases and traffic through a time-based simulation; and evaluate the generated report to detect the source of the deadlocks.
During the webinar, you will learn to
1. Construct the system behavior using a system modeling environment
2. Run traffic and use-cases to create real-world operation
3. Evaluate the timing and resource consumption data to detect deadlocks
4. Determine the cause of the deadlocks using process and resource information
We will evaluate the simulated outcomes of an application to observe the functional coverage and design bottlenecks. Data Sampling with different test case are used to validate the correctness of the design. Example of deadlock scenarios are Multi-Core Cache Coherence, protocol and baseband Task Graphs, preemptive shared Bus and external resources such as printer, cameras and electrical drives.
Webinar on Functional Safety Analysis using Model-based System AnalysisDeepak Shankar
To learn more, visit https://www.mirabilisdesign.com or email: info (at) mirabilisdesign.com.
To meet the ISO-26262 Parts 4,5,6 Requirements.
Failure Analysis, Identification and Resolution of Electronics and Software
Join Mirabilis Design for a Webinar to evaluate performance and power consumption, measure the quality of your architecture in the event of failures and, the recovery time from the failures. During this Webinar, we will demonstrate a step-by-step approach to dynamic system modeling, fault generation, and evaluation of diagnostics to cover both ISO26262-Part 4,5,6.
Using the VisualSim modeling and simulation software, we will validate and optimize the system architecture, apply failures, add diagnostics to identify the failures, and create logic to resolve the error condition. This model will be used to measure the compliance of the functional safety setup to meet the requirements of ISO26262-Part 4,5,6.
At the Webinar, we will
1. Cover hardware, software, network, RTOS and power systems.
2. Construct an architecture model of a braking system.
3. Apply failures, add methods to detect errors and algorithms to return the system to normal operation.
3. Analyze the models to meet the timing, power and functional requirements during an event of a failure.
System failure analysis plays a vital role in avoiding any real-time injuries/dangers, especially in aerospace, automotive and medical appliances. While designing the system, a proactive and systematic method to evaluate where and how the system might fail, the outcome of the failure, and how the failures can be prevented helps to consider required safety measures. This minimizes the cost, resources, and time-consumed after the occurrence of an unexpected incident.
Is accurate system-level power measurement challenging? Check this out!Deepak Shankar
The most common method of computing power of a system or semiconductor is with spreadsheets. Spreadsheets generates worst case power consumption and, in most cases, is insufficient to make architecture decisions. Accurate power measurement requires knowledge of use-cases, processing time, resource consumption and any transitions. Doing this at the RTL-level or using software tools is both too late and requires huge model construction effort. Based on our experience, a systems-level model with timing, power and functionality is the only real solution to measure accurate power consumption. Unfortunately, system-level models are hard to construct because of the complex expressions, right-level of abstraction and defining the right workload. Fortunately, there is a solution that enables to you to build functional models that can generate accurate power measures. These measurements can be used to make architecture decisions, conduct performance-power trade-off, determining power management quality, and compliance with requirements.
During this Presentation, we will demonstrate how system-level power modeling and measurement works. We shall go over the requirements to create the model, what outputs to capture and how to ensure accuracy. During the presentation, the speaker will demonstrate real-life examples, share best practices, and compare with real hardware. This presentation will cover power from the perspective of semiconductor, systems and embedded software.
Architectural tricks to maximize memory bandwidthDeepak Shankar
Deepak Shankar, CEO and Founder of Mirabilis Deign Inc. hosted a webinar(Feb 17,2016) on the architectural possibilities to improve memory bandwidth. This webinar highlighted that memory plays a role in impacting the performance & power consumption of a system.
Mirabilis Design Inc. provides the cutting-edge system-level modeling software for designers and architects. Mirabilis Design established in 2005, a Silicon Valley company based in California, USA provides electronic system-level design software and services. Our company empowers architects/designers to create right products that meet the market requirements.
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Mirabilis_Design AMD Versal System-Level IP Library
1.
2. Introduction to AMD Versal SOC-FPGA
Versal adaptive SoCs deliver unparalleled application- and
system-level value for cloud, network, and edge
applications.
The disruptive 7 nm architecture combines heterogeneous
compute engines with a breadth of hardened memory and
interfacing technologies for superior performance/watt
System-on-chip (SoC) combines CPUs, DSPs, I/O and RAM
control along with programmable hardware logic
Built around an integrated shell composed of a
programmable network on chip (NoC), which enables
seamless memory-mapped access to the full height and
width of the device.
3. Current Approach to Architecting FPGA
Math algorithm modeling
◦ Conducts Functional or math simulation to study precision and fidelity of new algorithms
Requirements database
◦ Requirements modeling list and static test changes
List the delays in spreadsheet and add them up
◦ Average or worst case without concurrent activity
Emulation/Boards
◦ Run benchmarks and capture the latency and memory throughput
4. FPGA Designer Requirements
1. High-level system architecture mapping. System architects (MATLAB) to evaluate the advantage
provided by Xilinx Versal heterogeneous architecture
• Persona: System architect
• High-level application capture w/ models of key application building blocks
• Fast application exploration to heterogeneous HW targets (PS, PL, AIE, PL+AIE)
2. Algorithm Trade-Offs: Initial architecture application mapping decisions to choose the right fabric for
optimal performance for each algorithm
• Persona: PL/RTL, AIE, & PS designers
• Make trade studies of how different implementations and mappings change system performance
• Identify potential bottlenecks
5. Introduction to VisualSim System-Level- IP
Architecture Platform for AMD Versal FPGA
VisualSim is system-level modeling and simulation SW
Platform for rapid Trade-off
◦ Performance/Power/Area during planning
◦ Study speed, power, failure and bottlenecks
Optimize implementation, resource and timing constraints of
algorithm tasks
New Versal FPGA IP is a Stochastic model containing
◦ Heterogeneous compute resources
◦ DDR and HBM memory interfaces
◦ Statistics for latency, throughput, utilization and power
◦ User expandable resource usage table
◦ External Interfaces
◦ Task block with mapping function
◦ Traffic generator for workloads
6. System-Level Application Exploration Tool
App
Model
Resource
Model
App resource
target
Simulate/test
Identify
congestion
?
What is it?
• Stochastic models focused on early application mapping
exploration to heterogeneous SoC compute resources.
• Users are system architect responsible for high-level
complex system mapping, not design entry
• Rapid trade-off and design iteration prior to algorithm
and design entry
Existing AMD-Xilinx tools
Where does it fit?
• Extends AMD-Xilinx general toolset with pre-design-
entry focused application analysis
• Lower fidelity stochastic based model vs. full design
entry simulation tools
• Provides guidance to down-stream sub-system (AIE, PL,
PS) design entry development teams
Persona
Generates
System
Architect
Subsystem
requirements
Developer
PL: RTL/HLS
AIE: C/C++
PS: C/C++/Python
System Eng
BootFW
Gen configs
SW Eng
Runtime SW
OTA life-cycle
App Exploration
Analysis Tool
Design Entry
RTL, C/C++
Design Generation
*.bit, *.pdi, *.elf
On-Target Runtime
Deployment
(Linux, libs, ??
VisualSim
App Exploration
Analysis Tool
Design Entry
(Vivado & Vitis)
RTL, C/C++
Design Generation
(Vivado & Vitis)
*.bit, *.pdi, *.elf
On-Target Runtime
Deployment
(Linux, libs, ??
7. App Exploration Tool – Elements
Resource models
• AIE tile & subsystem
• NOC backbone, AXI interconnects and Direct Path
• PL function “task” models
• DDR memory controller & devices
• Arm CPU models
User app functions & stimulus
• Target persona: System architect
• Traffic pattern generators
• Task/compute behavior models
• Task & data description via XML semantic language including SysML
• C-code for CPU & GPU like targets including Tarmac, Gem5 trace
• Stochastic and cycle-accurate function models for FPGA
App Exploration
Analysis Tool
Design Entry
(Vivado & Vitis)
RTL, C/C++
Design Generation
(Vivado & Vitis)
*.bit, *.pdi, *.elf
On-Target Runtime
Deployment
(Linux, libs,
AIE AIE AIE
AIE AIE AIE
Interconnect
Model
Interconnect
Model
Interconnect
Model
Interconnect
Model
Interconnect
Model
Interconnect
Model
NOC Backbone
PL Custom
Models
PL Custom
Models
PL Custom
Models
DDR Memory
PS Subsystem
Interfaces
9. Mapping Algorithm to Versal SoC-FPGA
Implementing an Image Processing
algorithm on AMD-Xilinx Versal FPGA.
Each task is mapped to a resources
Standard
Library
Component
Basic/Starting Configuration
Grayscale_Conversion - PS [A72 Core 1]
IIR – Logic (PL)
FFT – AI Engine Tile
Edge_Image - Logic (PL)
iFFT – AI Engine Tile
Edge_Image_Enhancement – Logic (PL)
Segmentation – PS [A72 Core 2]
Image
Processing
Algorithm
10. Algorithm Task Table
This table is used to define the number of resources consumed by each tasks across various resources (PS, PL,
AI Tiles) if they were to be mapped to any of them. Each of these tasks are mapped to the resource of choice
from the behavioural flow.
11. Requirements and AI-based Tracking
All the requirements (Latency, throughput, power, utilization etc.) can be listed in this csv file.
At the end of simulation, a report which says whether the requirements were met is generated.
12. Run 1 – Base Configuration
Application latency increasing over time.
Increase in latency is due to Segmentation.
Remap segmentation task AI Engine Tiles
13. Run 2 – Segmentation Mapped to AI Engine
Application latency is in a bounded range.
NoC Utilization is high.
To reduce utilization, changed interconnect for Segmentation from NoC to Direct
14. Run 3 – Using Direct Path between PS and AI
Latency if deterministic
Latency requirement (App latency < 80 msec) is met.
Utilization across NoC is acceptable
19. Behavior Graph and Mapping File
VisualSim Architect
Dispatcher sends it to the target hardware module for processing and Handle Transitions
Map individual functions to
resources in Mapping Table
20. Simulate Base Model (Clk = 600 MHz)
The Requirements – latency for both ST
(Static Target) and MT (Moving Target)
estimation is not met
21. Parameter Regression on Multi-Core
Different parameter combinations based on the
configured ranges are generated and simulated
22. AI-Based Study using Requirements
• Run number 19 – clock
frequency at 1000 MHz satisfied
the performance requirements
we had set.
• Since the frequency was
increased from 600 MHz, the
total power consumption went
up while running the system at
1000 MHz
• Architect can evaluate
different processing
resources – DSP vs Xeon
cores vs Power cores if
they have stringent power
thresholds
Requirements being evaluated for each simulation
run in the parameter sweep
Overall Results – We can identify the simulation runs which
meet the requirements and select the right configuration
after considering cost vs performance trade-offs
24. Failure Analysis
Hardware Failure
Loss of processing cores, limited storage, reduced or loss
memory device or bus overload/incorrect signals
Software failure
Resource starvation, deadlocks, data overwrite
Network failure
Network Congestion, misconfiguration, link loss and network
errors
RTOS failure
Unable to achieve real-time deadlines, malicious change in
schedule table, and executes beyond time slots
Power Failure
Both reduced and full power failure. Slower processing speed,
limited number of resources can be executing concurrently
MIRABILIS DESIGN INC. 24
26. Software Design and Optimization
GCC Compiler –
Target arch.
Compile and
disassembly
Source code
Objdump –
Disassembly
Trace in VisualSim
usable format
Select
Processor
core
Obtain Pipeline
structure from
official
documentation
Create the list
of parameters
and their
possible values
Map parameters
Stats
Reconfigure parameter map to
improve performance
Update Source code to improve
performance
28. Interconnect Architecture Exploration
Analyze SoC NOC and Memory sub-System
architectures
Coherent .vs. Non-Coherent sub-systems connectivity
IO Coherency BW allocation
QoS – control, configuration and data intensive
Analyze SoC end to end flow control, credits,
queueing and arbitration mechanisms
Analyze scheduling and distribution of tasks throughout the
compute pipeline
Analyze the importance of different flow control
mechanisms
e.g., credit allocation schemes, token bucket mechanisms
and rate limit configurations
Analyze SW-HW interfaces and communication
End-to-End Latency - Time taken for the return trip
1. Cross point delay
2. Buffering at cross point and slave
3. Transfer and control delay at cross point, slave and
cache coherent domains
4. Memory read or write delay
5. Wire delay
Network Latency – Latency across cross point
Throughput– Memory and PL-AIE bandwidth
30. Analysis Scenarios
Scenarios 1 2
Optimal network configuration
Packets only have to take one or two
hops to reach destination
Yes Non-Optimal network
configuration – Non-
optimal placement of
nodes
Router Frequency MHZ
Frequency at which the XP operates
2500 2500
Flit_Size (Bytes)
Max packet size allowed on the network
If the incoming packet is more than the
Flit_Size, the packet is fragmented
256 1024
X-dimension
Y-dimension
8
8
8
8
Packet Size 256 1024
Analysis shows the HBM Throughput is 40GBps because of Optimal network configuration and high frequency
40. Architecting Hardware-Software for
Infotainment System
DRAM
Display
IO
A
M
B
A
A
X
I
B
u
s
CPU
GPU
Display
Ctrl
P
C
I
e
Video Camera
SRAM
Packet
System Overview
◦ Camera : 30fps, VGA corresponds
◦ CPU : Multi-core ARM Cortex-A53 1.2GHz
◦ GPU : 64Cores(8Warps×8PEs), 32Threads, 1GHz
◦ DisplayCtrl : DisplayBuffer 293,888Byte
◦ SRAM: SDR, 64MB, 1.0GHz
◦ DRAM : DDR3, 64MB, 2.4GHz
Explore at the board- and semiconductor-level to size uP/GPU, memory bandwidth and bus/switch configuration
Develop an integrated Infotainment Processor
• Size GPU, AXI bus and memory controller
• Target is a high-end Automotive
infotainment
• Ensure sequence of flows from Video
Camera to Display Controller is correct
• Determine the maximum throughput that
can be processor with no overflows
41. VisualSim Model of Infotainment System
NXP i.MX6 /
nVIDIA Drive PX
Xilinx FPGA
Kintex 8
Discrete
DMA
ARM A53
GPU
Display Ctrl
SRAM3
DRAM3
Video IN
Parameters
Video OUT
42. Conducting Architecture Trade-off
• By changing the amount of video input data (packet number), observe the SRAM -> DRAM transfer
performance and examine the upper limit performance of the video input that the system can tolerate.
210Packet/Sec
12ms
21Packet/Sec
41.4us
300Packet/Sec
• 250 Packet/Sec is the system limit
• With 300 Packet/Sec, simulation cannot be
executed due to FIFO buffer overflow.
48. About Mirabilis Design
Software Company based in Silicon Valley
Integrates Model-based Systems Engineering with the electronics development flow
Development and Support Centers
USA, India, China, South Korea, Japan and Europe
VisualSim Architect - Modeling and Simulation Software
Graphical modeling, multi-domain simulator, system-level IP, analysis tools and open API
Digital Enablement of the Electronics Product Development Front-End
Market Segments
Semiconductors, Automotive and, Aerospace and Defense
Design Enablement
Architecture trade-offs, system validation, early functional testing and communication
Networking
49. System Design Solution and Platform
VisualSim
Architect
• Graphical and
Hierarchical
Modeling
System-Level IP
• Parameterized
components that
cover hardware,
software and
networking
Multi-domain
Simulator
Digital, FSM
Untimed &
Continuous
MBSE
Linking
Requirements with
multi-core
Regression with AI
Cloud and Desktop Version available
Key Innovations
• Parameterized library components for hardware to
create any vendor variation
• Real-time plotting
• Single-event calendar that can communicate with
both VisualSim and external simulators
• Behavior to architecture mapping
• Support for all design and analysis from Concept to
implementation flow for electronics
50. VisualSim System Level IP
Custom Creator
Algorithm
Power
Control, analog, DSP,
communication,audio
imaging Table, Energy harvesters,
Battery
Distribution, Sequence,
Trace file, Instruction
profile
Traffic
Reports
Latency, Throughput,
Utilization, Ave/peak
power, Statistics
RTL-Like
RTOS
Clock, Wire-Delay,
Registers, Latches and
Flip-flop, ALU and FSM,
Mux, DeMux, Lookup
table
Generic RTOS, ARINC
653, AUTOSAR
AMBA (AHB/ APB/ AXI), Corelink,
CoreConnect, Network-on-Chip,
Virtual Channel, DMA, Crossbar,
Serial Switch, Bridge
SOC
Board-
Level
VME, PCI/PCI-X/PCIe, SPI 3.0,
Rapid IO, 1553B, FlexRay, CAN-
FD, AFDX, TTEthernet, OpenVPX
Processors ARM (M-Series), ARM (A8, A72, A53,
A76), RISC-V, Nvidia- Drive-PX,
Configurable GPU, DSP, mP and mC,
PowerPC, X86- Intel and AMD, DSP- TI
and ADI, Others: MIPS, Tensilica,
Renesas SH, Marvel
Stochastic
Queue ,Time
Queue, Quantity
Queue, System
Resources,
Scheduling
algorithms
Script language,
600 RegEx, Task
graph, Use cases,
Programming
languages
Storage Flash, NVMe, Disk
Memory Controller, MPMC,
Fibre Channel, Fire Wire
Switched Ethernet, Resilient Packet Ring,
RP3, Wireless LAN 802.11, Bluetooth and
PAN, Spacewire, Audio-Video Bridging,
IEEE802.1Q
Networking
Memory
• Memory Controller, SDR, DDR
DRAM 2,3,4, LPDDR 2, 3, 4,
HBM, HMC, QDR, RDRAM
FPGA Xilinx- Zynq, Virtex, Kintex,
Intel-Stratix, Arria,
Microsemi- Smartfusion,
Programmable logic
generator, External links to
I/O, Network and Memory
Largest Library of System Modeling IP Components
51. VisualSim Integrated System Design Flow
MBSE Concept
Failure &
Security
Functional
Unit Testing
Embedded
Systems
FPGA/
ASIC
Misison and
Vehicles
RF/Analog/
Antenna
Hardware/
Software Flow
To Implementation
(Schematics, HDL, Embedded C/C++/Java
Emulators, test equipment, FPGA Boards)
Document
Generation
External Users
Government
Systems
Integrator
Protocols &
DSP/Imaging
3rd Party
Provided
4.
Communication
& Sharing
5.
Functional
Testing
1. Algorithmic
Optimization
(Fidelity & Precision)
Systems
engineering
Marketing
VisualSim
Architect
VisualSim
Architect
Integrating What-if’s to Functional Testing
2. Architecture
Exploration (Speed,
Power & Area)
3. Specialized
Testing and Demo
52. VisualSim drives Efficiency & Productivity
Model Creation (6)
Implementation (18)
Using Current Design Methodology
Project Schedule
)
Implementation (12)
Using VisualSim Design Methodology
Time savings
based on 24
month project
is 20-40%
Note: All times in months
TM
Communication and Refinement (4)
Analysis (2.5)
Model Creation (0.5)
Analysis (1.5)
Communication and Refinement (6)
Advantageous over generic modeling environment due to less time & greater applicability across the organization
Editor's Notes
Instant Power represents the instantaneous power consumption of the devices (mentioned in power table) at every instance of clock cycle
Average Power represents the average of power for each devices at different states-> (Standby, Active, Wait, Idle and Retention)
Here the Maximum Network Latency is 3.5x10-9 (Which is in Nano seconds) and Maximum End to End Latency is 1.6x10-7. From the analysis we can see that an optimal network configuration and high frequency results in better latency.