This document provides information about a virtual RISC-V summit event taking place from December 8-10. It then summarizes a presentation given by Leonidas Kosmidis on educating computer architects with RISC-V. The presentation discusses safety critical systems and why companies are interested in RISC-V for these applications. It also describes the computer architecture curriculum and RISC-V projects at the Polytechnic University of Catalonia and Barcelona Supercomputing Center. Specific projects from a processor design course are summarized, including dual/triple lockstep CPUs, a WCET support implementation, and vector extensions added to the Lagarto RISC-V core. The document concludes by acknowledging those involved

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CONTRIBUTE.
COLLABORATE.
COMMERCIALIZE.
December 8-10 | Virtual Event

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December 8-10 | Virtual Event
Educating the Computer
Architects of Tomorrow's Critical
Systems with RISC-V
Leonidas Kosmidis
Senior Researcher and Junior Faculty
Barcelona Supercomputing Center (BSC) and
Polytechnic University of Catalonia (UPC)
#RISCVSUMMIT

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Safety Critical Systems
Importance
• Human lives at stake
• Society
• Economic
• Large, Multibillion Markets
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Safety Critical Systems
Required properties
Primary:
• Functional Safety
• Real-Time Properties
• Reliability
• Security
• Privacy
Secondary:
• High Performance
• Low Power Consumption
Significant interest from companies in all these industries in RISC-V!
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Why Safety Critical Companies are
interested in RISC-V?
• Customisation
• Cost Reduction
• Open Architecture
• Full access to documentation and implementation details when using open source designs
However RISC-V cores with safety-critical features are underrepresented in the available open source designs
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Computer Architecture Curriculum at UPC
and RISC-V Related projects at BSC
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Computer Science and
Engineering
Undergraduate Program
MSc in Innovation and
Research in Informatics
Computer Architecture
Computer Architecture 2
Computer Eng. Project
High Perf. Computer Arch
Processor Architecture
Processor Design
MSc in Computer
Science and Engineering

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Processor Design
• Advanced Graduate Course, optional subject within the High Performance Computing specialisation of the Master’s
in Innovation and Research in Informatics (MIRI) at UPC
• Project-oriented course with a semester-wide RTL project
• Implementation of an advanced feature within the selected baseline processor
• Complete freedom of choice of baseline processor, HDL, tools, project
• Keeps students motivated
• Promotes creativity
• Groups of 2 or more students to implement larger projects
• Weekly follow-ups and regular deliverables
• Covers the entire design cycle from Specification to Verification
• Optional features with bonus grades: area/delay/power overheads analysis/trade-offs, physical design,
documentation improvement
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Processor Design Fall 2019
Projects Overview
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7 RISC-V based projects
• 5 CPU projects
• 2 accelerators
• 2 based on BSC’s Lagarto
• In-order core refactoring for the tape-out, vector instructions
• 3 based on Western Digital’s SweRV
• Support for WCET computation, dual and triple lock-step designs
• 1 Ariane
• ECC
• 1 Rocket
• Cryptographic Accelerator
Details and source code links: Kosmidis et al, Processor Design Fall 2019: Critical and Real-Time Systems Projects, Tech Report
UPC-DAC-RR-CAP-2020-1, https://www.ac.upc.edu/app/research-reports/public/html/research_center_index-CAP-2020,en.html

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Dual and Triple lockstep
Based on SweRV EH1
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Common solution implemented in safety critical domains to protect against errors
General idea: two or three independent hardware instances execute the same code with small time difference
Same inputs, output comparison every cycle
• Dual-lockstep can only detect an error
• Typically used in the automotive sector (fail-safe approach)
• Triple lockstep can also correct an error
• Used in avionics (fail-operational approach)
The implementation can be:
• fine-grained: check internal signals, e.g. at instruction commit
• coarse-grained: check only core outputs, typically implemented in avionics comparing the output of different chips
The time difference offers diverse redundancy, in order to avoid transient faults
EH1 already contains ECC for cache and TCM protection

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Dual and Triple lockstep
Based on SweRV EH1
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Two different implementations with different trade-offs
Team Members: Jeremy Giesen, Adrian Munera Team Members: Marie Denoo, Jean-Paul Tarot
Dual and Triple lockstep designs
Complete core replication, including caches and
AXI-lite buses
Area and delay overhead analysis using the FPGA
port of EH1
Dual-lockstep
More efficient implementation
The cores are connected in the same AXI-
lite buses
Extensive verification using Cocotb
Replicated components

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WCET Support
Based on SweRV EH1
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Added support for Measurement-Based Probabilistic Timing Analysis (MBPTA) [1]
Minor modifications required in the design [2][3]
• Time-Randomisation in the hard to predict and frequently used hardware
resources
• cache, using random placement [4] and replacement
• Worst-case upper-bounding of resources with small variability and less
frequently used
• divider, fixed latency to its maximum, 34 cycles
• Pseudo-Random Number Generator
Team Members: Javier Barrera, Iván Rodríguez
[1] Cucu et al, Measurement-Based Probabilistic Timing Analysis for Multi-path Programs, ECRTS 2012
[2] Kosmidis et al, Fitting processor architectures for measurement-based probabilistic timing analysis, Microprocessors &
Microsystems 2016
[3] Kosmidis, Enabling Caches in Probabilistic Timing Analysis, PhD Thesis 2017
[4] Kosmidis et al, A cache design for probabilistically analysable real-time systems, DATE 2013
Cache bank0
Cache bank1
Cache bank2
Cache bank3
Cache bank4
Cache bank5
Cache bank6
Cache bank7

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Lagarto In-order BSC’s RISC-V Core
Core improvements for the next tape out
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Baseline (preDRAC):
First open-source core developed in Spain
5-stages in-order core
• Branch Predictor
• Boots Linux on FPGA, passes official RISC-V ISA tests
• First tape out in May 2019, TSMC 65nm, 2.5mm2
• 200MHz frequency
Team Members: Guillem Cabo, Ruben Langarita, Guillem Lopez
Project improvements:
• Migrate the design to System Verilog
• Maintain the performance, fix some known bugs
• Refactored the core dividing it in Control Unit and
Datapath
• Decouple the access to ICache and DCache
• Improved Verification
• Continuous integration
• Update the ISA to the latest one
Lagarto to be open sourced soon by BSC
including these improvements

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Lagarto In-order BSC’s RISC-V Core
Vector extensions
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Add RISC-V vector extensions to Lagarto
• Based on the Working Draft Specification of Nov. 2019
• Subset of the specification implemented
• Integer and Bitwise operations
• Vector-vector
• Vector-register
• Vector-immediate
• Loads
• Parameterizable VBW data bus
• Parameterizable VLEN size
• Out-of-Order issue
• Single in-flight instruction
Team Members: Fabio Banchelli, Kilian Peiro

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Rocket
RSA Montgomery Accelerator
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Take advantage of the RoCC interface
• Implementation of both hardware accelerator and software stack
RSA implementation based on Montgomery Exponentiation and
Multiplication
Encryption and decryption of 128-bit blocks
Verification based on Verilator and Cocotb
• Used arbitrary arithmetic in Python interfaced with the C++
code of Verilator
Docker image available
Team Members: Ruben Cano, Juan Miguel de Haro

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Ariane
ECC Memory protection
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Two solutions implemented
• Error detection based on parity
• 1 parity bit per 64 bits
• Low hardware overhead
• Can only detect an odd number of single event upsets (SEUs)
• Error correction based on triple redundancy
• Very high cost
• Can correct up to 64 bit errors
Team Members: Wout Klingele, Killian Storm

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Processor Design Fall 2020
Projects Overview
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9 RISC-V based projects:
• 5 CPU projects, 4 accelerators
• BSC Lagarto-based: Out-of-order core improvements for the tape-out, integration with EPI’s Vector Accelerator
• Western Digital’s SweRV EL2 based: Support for WCET computation and time-predictable multi-threading
• Custom RISC-V implementation Implemented in the Processor Architecture 2019: Hard real-time multi-threading
• Noel-V/LEON3: Custom vector extensions and timing predictability
• Ariane-based: Modifications for Timing predictability
• 2 GPU projects based on Vortex
• WCET oriented and fault-tolerant design, custom GPU design compatible with Vortex
• Custom Binarised Neural Network Accelerator
• Using ESA’s TASTE Model-Based Design Framework for the software stack
• Custom Google’s TPU-like Accelerator
Details and source code links to be published after the end of the course

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Acknowledgements
My colleagues:
Miquel Moretó (BSC/UPC), Ramon Canal (UPC), Jose Maria Arnau (UPC), Roger Espasa (UPC/Semidynamics)
My students:
• Class 2019: Fabio Banchelli, Javier Barrera, Guillem Cabo, Ruben Cano, Marie Denoo, Jeremy Giesen, Juan Miguel
de Haro, Wout Klingele, Ruben Langarita, Guillem Lopez, Adrian Munera, Kilian Peiro, Ivan Rodríguez, Killian Storm,
Jean-Paul Tarot
• Class 2020: Marco Aguado, David Alvarez, Max Doblas, Mehdi Hassanpour, Victor Jimenez, Alvaro Jover, Julien
Labarre, Cristina Peralta, Mario Rodriguez, Joel, Sanchez, Sergio Sanchez, Marc Sole, Victor Soria, Jannis Wolf
My Funding Agencies:
Spanish Ministry of Science and Innovation (MINECO) grants PID2019-107255GB and FJCI-2017-34095, GPU4S
(GPU for Space) ESA ITT AO/1-9010/17/NL/AF, HiPEAC Network of Excellence
and of course
The RISC-V Foundation and all its Open Source Ecosystem
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December 8-10 | Virtual Event
Thank you for joining us.
Contribute to the RISC-V conversation on social!
#RISCVSUMMIT @risc_v