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WEBINAR: MODELING ABSTRACTION
Presenter:
Akash
Research and Development Engineer
Mirabilis Design Inc.
Email: akashk@mirabilisdesign.com
Organizer:
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com
Agenda
 Example of system abstraction
 Impacts of design and analysis
 VisualSim and its libraries
 Abstract design modeling methodology
 About Mirabilis Design
Stochastic Design
EARLY DESIGN VALIDATION / SPECIFIC SUBSYSTEM VALIDATION
Stochastic Design
 System Resource Modeling
 Custom Traffic generation
 Less Complexity
Stochastic Design
 Key Statistics (CPI, MIPS,
Stall cycles, etc.)
 Utilization of each device
 Power consumption
 End to End Latency
 Buffer Overflow
Impacts of stochastic modeling
 Faster Simulation
 Easy implementation
 Stabilize the system
 Flow control validation
 Improve performance
 Optimal Configuration
 Scheduling algorithm
 Resource Sizing
 Identifies Bottleneck
 Stress testing
Hybrid Design
SPECIFIC OR SET OF SUBSYSTEM ANALYSIS
Hybrid Design
Hybrid Design
 Application Response Time
 Detailed statistics of
external components
 Latency of each task
 Power Analysis
Impacts of Hybrid modeling
 Performance analysis of specific devices
 Optimize resources and their usage
 Optimal configuration for specific devices
 Correctness and stability of certain devices
 Identify devices that cause performance degradation
Cycle Accurate Design
BEHAVIOR AND CORRECTNESS OF THE ENTIRE SYSTEM
Cycle Accurate Design
 Detailed implementation
 Software emulation
 Better Debugging
 Functional Validation
Cycle Accurate Design
 Detailed Statistics
 Observe internal functions
and registers
 Accurate Power analysis
 Performance analysis
throughout the execution.
Impacts of cycle accurate modeling
 Timing Analysis
 Behavior validation
 Functional verification
 Accurate power modeling and analysis
 Data handling
VisualSim Architect
GUI BASED, CODE FREE MODELLING AND SIMULATION PLATFORM
End-to-end System Modeling Solution
Planning
Corporate
Think Tank
Software
Protocols
Missions
FPGA/
ASIC
Network of
Systems
Systems
Engineer
Performance
Engineers
Internal Users
To Implementation
(Schematics, HDL, Embedded C/C++/Java
Emulators, test equipment, FPGA Boards)
RF/Analog/
DSP/Imaging
External Users
Agency
Systems
Integrator
Sub-System
Architect
3rd Party
Provided
Executable
Specification
System
Validation
Performance &
Architecture
Algorithm
Validation
Feasibility &
Risk Reduction
VisualSim Design Flow and Integration
Systems, Semiconductor, Networking and Software
Largest System Level IP
Custom Creator
Support
Power
Listeners, Debuggers,
Tracers, Assertions
Table, Energy harvesters,
Battery
Distribution, Sequence,
Trace file, Instruction
profile
Traffic
Reports
Latency, Throughput,
Utilization, Ave/peak
power, Statistics
RTL-Like
RTOS
Clock, Wire-Delay,
Registers, Latches and
Flip-flop, ALU and FSM,
Mux, DeMux, Lookup
table
Generic RTOS, ARINC
653, AUTOSAR
AMBA (AHB/ APB/ AXI), Corelink,
CoreConnect, Network-on-Chip,
Virtual Channel, DMA, Crossbar,
Serial Switch, Bridge
SOC
Board-
Level
VME, PCI/PCI-X/PCIe, SPI 3.0,
Rapid IO, 1553B, FlexRay, CAN-
FD, AFDX, TTEthernet, OpenVPX
Processors ARM (M-Series), ARM (A8, A72, A53,
A76), RISC-V, Nvidia- Drive-PX,
Configurable GPU, DSP, mP and mC,
PowerPC, X86- Intel and AMD, DSP- TI
and ADI, Others: MIPS, Tensilica,
Renesas SH, Marvel
Stochastic
Queue ,Time
Queue, Quantity
Queue, System
Resources,
Scheduling
algorithms
Script language,
600 RegEx, Task
graph, Use cases,
Programming
languages
Storage Flash, NVMe, Disk
Memory Controller, MPMC,
Fibre Channel, Fire Wire
Switched Ethernet, Resilient Packet Ring,
RP3, Wireless LAN 802.11, Bluetooth and
PAN, Spacewire, Audio-Video Bridging,
IEEE802.1Q
Networking
Memory
• Memory Controller, SDR, DDR
DRAM 2,3,4, LPDDR 2, 3, 4,
HBM, HMC, QDR, RDRAM
FPGA Xilinx- Zynq, Virtex, Kintex,
Intel-Stratix, Arria,
Microsemi- Smartfusion,
Programmable logic
generator, External links to
I/O, Network and Memory
VisualSim Methodology
SELECTING PROPER MODELING ABSTRACTION FOR A SPECIFIC GOAL
Modeling Abstraction
 High-level to low-level design
 Parallel Design
 Specific Design of interest
High-level to Low-level Design
Design Flow of a system
Specification
Stochastic model
Analyze base configuration
with traffic profiles
Add complexity
to the model
Analyze the impact
of each device
Detailed implementation at
cycle level or data level logic
Validate the behavior and
optimize the system
Benefits of High level to Low level design
 Advantages
 Early system analysis
 A better understanding of the design and bottlenecks
 Faster design iteration
 Beneficial for:
 Complex functionality design
 High-performance requirement
 Power constraint design
Initial
Specification Product Management
Team
Verification Team
Hardware Design Team
Software design Team
Parallel Design
Update and Validate Design Spec
Verify specific
logic or a
subsystem
Hardware Design
and Analysis
Software
modeling based
on initial Spec
Generate Traffic
profiles for
stress testing
Collaborate
and update
the design
Collaborate
and update
the design
Analyze the system
for performance
improvement
Stress test the
model for optimal
setting
Integrate the
software and
hardware
Benefits of Parallel design
 Advantages
 Faster Time-to-market
 Efficient use of resources and development cost
 Collaborate with different teams
 Beneficial for:
 Multi-domain design
 hardware software co-design
 Multiple teams collaboration
Specific Design of Interest
 Existing Design
 Recreating low-level design in high-level or hybrid abstraction.
 Optimize the specific device of interest for performance improvement.
 Design a subsystem for a better understanding of bottleneck or issue.
Mirabilis Design
About Mirabilis Design
Headquartered in Silicon Valley
Software company based in Silicon Valley & providing electronics design solutions
Development and Support centers across geographies
US, India, Taiwan, Japan and Czech Republic
VisualSim - Modeling and Simulation software
Visualize, optimize, and validate the system specification prior to development
Reached 18 companies
& 32 universities
HW Modeling;
35 customers
2003
Company Incorporated
2005
First Engagement with
HP
2008
VisualSim
2010
First 10 Customers
2011
Stochastic and
Network modeling
2013 2015 2018
Rearchitected
VisualSim Product
2019
Executable
Document Generator
2022
Antenna and
Mixed-Signal
2020
Functional Safety &
Failure analysis
MIRABILIS DESIGN CONFIDENTIAL
Awards
Stochastic
Modeling
Innovation
Best
Embedded
Systems at
DAC
Simulator of
the Year
Best ESL at
DAC
2nd at Arm
TechCon
Embedded
World Best in
Show
VisualSim drives Efficiency & Productivity
Advantageous over generic modeling environment
due to less time & greater applicability
across the organization
Model Creation (6)
Implementation (18)
Using Current Design Methodology
Project Schedule
)
Implementation (12)
Using VisualSim Design Methodology
Time savings
based on 24
month project
is 20-40%
Note: All times in months
TM
Communication and Refinement (4)
Analysis (2.5)
Model Creation (0.5)
Analysis (1.5)
Communication and Refinement (6)
MIRABILIS DESIGN CONFIDENTIAL
WEBINAR: MODELING ABSTRACTION
Presenter:
Akash
Research and Development Engineer
Mirabilis Design Inc.
Email: akashk@mirabilisdesign.com
Organizer:
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com
Q&A
Website : Mirabilis Design Inc - https://www.mirabilisdesign.com/
Contact us : info@mirabilisdesign.com
LinkedIn : Mirabilis Design Inc. - https://in.linkedin.com/company/mirabilis-design-inc-
Youtube : VisualSimSolutions - https://www.youtube.com/@VisualSimSolutions

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Modeling Abstraction

  • 1. WEBINAR: MODELING ABSTRACTION Presenter: Akash Research and Development Engineer Mirabilis Design Inc. Email: akashk@mirabilisdesign.com Organizer: Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
  • 2. Agenda  Example of system abstraction  Impacts of design and analysis  VisualSim and its libraries  Abstract design modeling methodology  About Mirabilis Design
  • 3. Stochastic Design EARLY DESIGN VALIDATION / SPECIFIC SUBSYSTEM VALIDATION
  • 4. Stochastic Design  System Resource Modeling  Custom Traffic generation  Less Complexity
  • 5. Stochastic Design  Key Statistics (CPI, MIPS, Stall cycles, etc.)  Utilization of each device  Power consumption  End to End Latency  Buffer Overflow
  • 6. Impacts of stochastic modeling  Faster Simulation  Easy implementation  Stabilize the system  Flow control validation  Improve performance  Optimal Configuration  Scheduling algorithm  Resource Sizing  Identifies Bottleneck  Stress testing
  • 7. Hybrid Design SPECIFIC OR SET OF SUBSYSTEM ANALYSIS
  • 9. Hybrid Design  Application Response Time  Detailed statistics of external components  Latency of each task  Power Analysis
  • 10. Impacts of Hybrid modeling  Performance analysis of specific devices  Optimize resources and their usage  Optimal configuration for specific devices  Correctness and stability of certain devices  Identify devices that cause performance degradation
  • 11. Cycle Accurate Design BEHAVIOR AND CORRECTNESS OF THE ENTIRE SYSTEM
  • 12. Cycle Accurate Design  Detailed implementation  Software emulation  Better Debugging  Functional Validation
  • 13. Cycle Accurate Design  Detailed Statistics  Observe internal functions and registers  Accurate Power analysis  Performance analysis throughout the execution.
  • 14. Impacts of cycle accurate modeling  Timing Analysis  Behavior validation  Functional verification  Accurate power modeling and analysis  Data handling
  • 15. VisualSim Architect GUI BASED, CODE FREE MODELLING AND SIMULATION PLATFORM
  • 16. End-to-end System Modeling Solution Planning Corporate Think Tank Software Protocols Missions FPGA/ ASIC Network of Systems Systems Engineer Performance Engineers Internal Users To Implementation (Schematics, HDL, Embedded C/C++/Java Emulators, test equipment, FPGA Boards) RF/Analog/ DSP/Imaging External Users Agency Systems Integrator Sub-System Architect 3rd Party Provided Executable Specification System Validation Performance & Architecture Algorithm Validation Feasibility & Risk Reduction
  • 17. VisualSim Design Flow and Integration Systems, Semiconductor, Networking and Software
  • 18. Largest System Level IP Custom Creator Support Power Listeners, Debuggers, Tracers, Assertions Table, Energy harvesters, Battery Distribution, Sequence, Trace file, Instruction profile Traffic Reports Latency, Throughput, Utilization, Ave/peak power, Statistics RTL-Like RTOS Clock, Wire-Delay, Registers, Latches and Flip-flop, ALU and FSM, Mux, DeMux, Lookup table Generic RTOS, ARINC 653, AUTOSAR AMBA (AHB/ APB/ AXI), Corelink, CoreConnect, Network-on-Chip, Virtual Channel, DMA, Crossbar, Serial Switch, Bridge SOC Board- Level VME, PCI/PCI-X/PCIe, SPI 3.0, Rapid IO, 1553B, FlexRay, CAN- FD, AFDX, TTEthernet, OpenVPX Processors ARM (M-Series), ARM (A8, A72, A53, A76), RISC-V, Nvidia- Drive-PX, Configurable GPU, DSP, mP and mC, PowerPC, X86- Intel and AMD, DSP- TI and ADI, Others: MIPS, Tensilica, Renesas SH, Marvel Stochastic Queue ,Time Queue, Quantity Queue, System Resources, Scheduling algorithms Script language, 600 RegEx, Task graph, Use cases, Programming languages Storage Flash, NVMe, Disk Memory Controller, MPMC, Fibre Channel, Fire Wire Switched Ethernet, Resilient Packet Ring, RP3, Wireless LAN 802.11, Bluetooth and PAN, Spacewire, Audio-Video Bridging, IEEE802.1Q Networking Memory • Memory Controller, SDR, DDR DRAM 2,3,4, LPDDR 2, 3, 4, HBM, HMC, QDR, RDRAM FPGA Xilinx- Zynq, Virtex, Kintex, Intel-Stratix, Arria, Microsemi- Smartfusion, Programmable logic generator, External links to I/O, Network and Memory
  • 19. VisualSim Methodology SELECTING PROPER MODELING ABSTRACTION FOR A SPECIFIC GOAL
  • 20. Modeling Abstraction  High-level to low-level design  Parallel Design  Specific Design of interest
  • 21. High-level to Low-level Design Design Flow of a system Specification Stochastic model Analyze base configuration with traffic profiles Add complexity to the model Analyze the impact of each device Detailed implementation at cycle level or data level logic Validate the behavior and optimize the system
  • 22. Benefits of High level to Low level design  Advantages  Early system analysis  A better understanding of the design and bottlenecks  Faster design iteration  Beneficial for:  Complex functionality design  High-performance requirement  Power constraint design
  • 23. Initial Specification Product Management Team Verification Team Hardware Design Team Software design Team Parallel Design Update and Validate Design Spec Verify specific logic or a subsystem Hardware Design and Analysis Software modeling based on initial Spec Generate Traffic profiles for stress testing Collaborate and update the design Collaborate and update the design Analyze the system for performance improvement Stress test the model for optimal setting Integrate the software and hardware
  • 24. Benefits of Parallel design  Advantages  Faster Time-to-market  Efficient use of resources and development cost  Collaborate with different teams  Beneficial for:  Multi-domain design  hardware software co-design  Multiple teams collaboration
  • 25. Specific Design of Interest  Existing Design  Recreating low-level design in high-level or hybrid abstraction.  Optimize the specific device of interest for performance improvement.  Design a subsystem for a better understanding of bottleneck or issue.
  • 27. About Mirabilis Design Headquartered in Silicon Valley Software company based in Silicon Valley & providing electronics design solutions Development and Support centers across geographies US, India, Taiwan, Japan and Czech Republic VisualSim - Modeling and Simulation software Visualize, optimize, and validate the system specification prior to development Reached 18 companies & 32 universities HW Modeling; 35 customers 2003 Company Incorporated 2005 First Engagement with HP 2008 VisualSim 2010 First 10 Customers 2011 Stochastic and Network modeling 2013 2015 2018 Rearchitected VisualSim Product 2019 Executable Document Generator 2022 Antenna and Mixed-Signal 2020 Functional Safety & Failure analysis MIRABILIS DESIGN CONFIDENTIAL
  • 28. Awards Stochastic Modeling Innovation Best Embedded Systems at DAC Simulator of the Year Best ESL at DAC 2nd at Arm TechCon Embedded World Best in Show
  • 29. VisualSim drives Efficiency & Productivity Advantageous over generic modeling environment due to less time & greater applicability across the organization Model Creation (6) Implementation (18) Using Current Design Methodology Project Schedule ) Implementation (12) Using VisualSim Design Methodology Time savings based on 24 month project is 20-40% Note: All times in months TM Communication and Refinement (4) Analysis (2.5) Model Creation (0.5) Analysis (1.5) Communication and Refinement (6) MIRABILIS DESIGN CONFIDENTIAL
  • 30. WEBINAR: MODELING ABSTRACTION Presenter: Akash Research and Development Engineer Mirabilis Design Inc. Email: akashk@mirabilisdesign.com Organizer: Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
  • 31. Q&A Website : Mirabilis Design Inc - https://www.mirabilisdesign.com/ Contact us : info@mirabilisdesign.com LinkedIn : Mirabilis Design Inc. - https://in.linkedin.com/company/mirabilis-design-inc- Youtube : VisualSimSolutions - https://www.youtube.com/@VisualSimSolutions