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Compare Performance-power of Arm Cortex vs RISC-V for AI applications_oct_2021
- 1. COMPARE PERFORMANCE-POWER OF ARM CORTEX VS RISC-V FOR AI APPLICATIONS. Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 2. Agenda Requirements and motivation for comparison Methodology to systems/SoC/Micro-architectures using different Instruction Sets Examples to show how the methodology can be utilized Improving accuracy of the comparison Motivation for this modeling approach
- 3. Using ISA for Multi-Level Analysis Processor Microarchitecture System SoC Design Embedded and Distributed system Is it ARM v8 or 9, RISC-V Or Leon, ARC, Tensilica? How many cluster? How many per clusters? What is the system-level cache/bus? Vector instr or GPU? ARM or RISC-V? How many cores/memory?
- 4. Requirements for a System Comparison Common benchmark #trial data data=[] for i in range(obs_size+1): indata=[] if i%2 ==0: for j in range(train_data_size): indata.append(np.random.randint(10)) indata.append(0) else: for j in range(train_data_size): indata.append(np.random.randint(3)) indata.append(1) data.append(indata) print(indata) costs=[] learning_rate=0.005 for i in range(5000000): z=0 ri=np.random.randint(len(data)) point=data[ri] dz_dw=[]#partial derivatives Instruction Set System SoC Workflow Network and Traffic Models Failure and Cyber Threat Modes
- 5. Concurrent Software Execution makes System Sizing Challenging Complex behavior - input stream - data dependent behavior Contention - limited resources - scheduling/arbitration Interference of multiple applications - limited resources - scheduling/arbitration - anomalies I/O DSP CPU1 CPU2 task1 task2 task3 task4
- 6. Narrowing the Range of Expected System Operation System with faster Bus is slower in places Unpredictable System Response
- 7. Task Allocations and Timing Deadline T3 Expected T3 Complete Consider three tasks- T1, T2 and T3 All tasks allocated to a single resource Each Task has processing time (Equal) and priority (T1>T2>T3) Design Impacts of buffering, preemption, offset times and processing capacity Challenges must be studied globally, ideally in the context of power, performance, and reliability
- 8. METHODOLOGY Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 9. Architecture Exploration of IP/SoC/Systems Single Model from Microarchitecture, System SoC and Embedded Systems Track 30 targets per minute Wifi or 5G device Process 3 cameras, 4 Lidars & 5 Radars 95% cache hit-ratio Gateways to ECAN, WiFi, BLE and TSN Product Idea Optimized Architecture Core DMA Message Network AI/CCN B U S/ N O C Select IP- Third- party & Custom Assemble Models Conduct Trade-offs Architecture Optimization Functional Analysis Validation Simulation Environment Documentation Traffic, Workload Use-cases IP Models SW Performance Measurement Hardware-in-the-Loop Integrate SoC into System Model
- 10. Optimizing, Diagnosing and Validating Result(statistic) file Recommendation file
- 11. EXAMPLE Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 12. Sample code in C -> Intermediate file 10/22/2021 MIRABILIS DESIGN INC. 12 aarch64-linux-gnu-gcc -g -Wa,-adhln cal2.c 1 .arch armv8-a 2 .file "cal2.c" 3 .text 4 .Ltext0: 5 .cfi_sections .debug_frame 6 .section .rodata 7 .align 3 8 .LC0: 9 0000 256400 .string "%d" 10 .text 11 .align 2 12 .global main 14 main: 15 .LFB5: 16 .file 1 "cal2.c" 1:cal2.c **** #include<stdio.h> 2:cal2.c **** #include<stdbool.h> 3:cal2.c **** #include <stdlib.h> 4:cal2.c **** int main(){ 17 .loc 1 4 0 18 .cfi_startproc 19 0000 FD7BBDA9 stp x29, x30, [sp, -48]! 20 .cfi_def_cfa_offset 48 21 .cfi_offset 29, -48 22 .cfi_offset 30, -40 23 0004 FD030091 add x29, sp, 0 24 .cfi_def_cfa_register 29 5:cal2.c **** int a = 10, b = 20 ; 25 .loc 1 5 0 Generate Assembly using gcc aarch64-linux-gnu-gcc -g -Wa,-adhln cal2.c
- 13. Using VisualSim Cycle-Accurate Library to Create Out-of-Order Custom Processor Integrate Behavior, Timing, Power and Software
- 15. MODELING ACCURACY Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 16. Comparing Results for ARM A53 with Simulated Values Benchmark FPGA VisualSim Difference Integer processing 5.94ms 6.425ms 7.55% Most load operations with random addresses 12.084ms 11.863ms 1.08% Most store operations with random addresses 13.984ms 14.65ms 4.5% Test System Xilinx Ultrascale+ Zynq® UltraScale+™ XCZU9EG-2FFVB1156E MPSoC running on the ZCU102 board 4 core ARM Cortex A53 at 1200Mhz; 32KiB i-cache; 32KiB d-cache, 1MiB L2; 2GB DDR4 DRAM 2400 Over 93-98% accuracy
- 17. Power Comparison between Simulated vs Measured Frequency Simulated Power Measured Power Delta percentage 500.0 Mhz 0.037 W 0.038 W 2.63% 600.0 Mhz 0.053 W 0.051 W -3.92% 700.0 Mhz 0.073 W 0.080 W 8.75% 800.0 Mhz 0.097 W 0.090 W -7.77% 1000.0 Mhz 0.157 W 0.159 W 1.25% 1100.0 Mhz 0.193 W 0.188 W -2.65% 1200.0 Mhz 0.233 W 0.227 W -2.64% 1300.0 Mhz 0.277 W 0.269 W -2.97% Source: Anandtech.com Over 97% accuracy
- 18. COMPARISON BETWEEN ARM CORTEX A53, A77 AND RISCV – U74
- 19. C code
- 20. Model Configurations ARM Cortex A53 Speed = 1200.0 MHz L1 Cache : ◦ I_Cache : 1200 MHz 2 way associative ◦ D_Cache: 1200 MHz 4 way associative L2 Cache : 1200 MHz 16 way associative AXI : 600 MHz DRAM : 1200 MHz ARM Cortex A77 Speed = 3000.0 MHz L0 Cache : 3000.0 MHz : MoP cache L1 cache : ◦ I_Cache : 3000.0 MHz 4 way associative ◦ D_Cache : 3000.0 MHz 4 way associative L2 Cache : 3000.0 MHz 8 way associative DSU Cache : 3000.0 MHz 16 way associative AXI : 1200 MHz DRAM : 1466.67 MHz RISC-V u74 Speed = 1200.0 MHz L1 Cache : ◦ I_Cache : 1200 MHz 4 way associative ◦ D_Cache: 1200 MHz 4 way associative TileLink : 1200 MHz L2 Cache : 1200 MHz 8 way associative AXI : 600 MHz DRAM : 1200 MHz
- 22. Results – Latency for running the same c-code Processor Instructions Latency Max MIPS ARM Cortex A53 ~ 56,66,000 0.0055846 ~ 1039 ARM Cortex A77 ~ 44,78,000 0.0011795 ~ 3960 RISC-V u74 ~ 60,58,000 0.007726 ~ 797
- 23. Results – Cache stats Processor MoP Hit Ratio MoP Mean Latency I1 Hit Ratio I1 Mean Latency D1 Hit Ratio D1 Mean Latency L2 Hit Ratio L2 Mean Latency DSU Hit Ratio DSU Mean Latency ARM Cortex A53 - - 99.97 1.93E-09 99.98 2.02E-09 18.75 9.33E-08 - - ARM Cortex A77 99.90 1.75E-09 67.22 6.25E-08 99.96 7.32E-10 14.19 1.82E-07 6.96 2.05E-09 RISC-V u74 - - 99.98 4.15E-09 99.98 1.86E-09 39.58 5.25E-08 - -
- 24. INTRODUCTION TO MIRABILIS DESIGN
- 25. About Mirabilis Design Started in 2007 and based in Santa Clara, CA, USA. Development and support centers in US, India, Germany, China, Japan, Taiwan and Czech Largest source of system modeling IP with embedded timing and power System architecture exploration of electronics, semiconductors and software Over 250 products worldwide across Semiconductors, Aerospace, Computing and Automotive VisualSim- Modeling and simulation software 100+ man years experience in system design and exploration of digital electronics Select the “Right” configuration to match customer request
- 26. VisualSim Architect Traffic, Traces, Script, Analytics Hardware- Core, DMA, Bus, cache, Memory Software- RTOS, Task graph, code execution Network- Protocols, Gateways, Security, channels Intelligent Diagnostic /multi-core Simulation Graphical and Hierarchical Stochastic &m Cycle- Accurate Comprehensive Architecture Exploration Solution Performance, Power and Functional Trade-off Large library of parameterized components Stochastic, Hybrid and Cycle-Accurate models For multiple core, SoC, System and Software API for simulators, programs and traces Optimizer to detect the best configuration
- 27. Largest Systems-Level Model Library Largest library of traffic, resources, hardware, software and analysis Traffic • Distribution • Sequence • Trace file • Instruction profile Reports • Timing and Buffer • Throughput/Util • Ave/peak power • Statistics Power • State power table • Power management • Energy harvesters • Battery • RegEx operators SoC Buses • AMBA and Corelink • AHB, AB, AXI, ACE, CHI, CMN600 • Network-on-Chip • TileLink System Bus • PCI/PCI-X/PCIe • Rapid IO • AFDX • OpenVPX • VME • SPI 3.0 • 1553B Processors • GPU, DSP, mP and mC • RISC-V • Nvidia- Drive-PX • PowerPC • X86- Intel and AMD • DSP- TI and ADI • MIPS, Tensilica, SH ARM • M-, R-, 7TDMI • A8, A53, A55, A72, A76, A77 Custom Creator • Script language • 600 RegEx fn • Task graph • Tracer • C/C++/Java • Python Support • Listener and Trace • Debuggers • Assertions Stochastic • FIFO/LIFO Queue • Time Queue • Quantity Queue • System Resource • Schedulers • Cyber Security RTOS • Template • ARINC 653 • AUTOSAR Memory • Memory Controller • DDR DRAM 2,3,4, 5 • LPDDR 2, 3, 4 • HBM, HMC • SDR, QDR, RDRAM Storage • Flash & NVMe • Storage Array • Disk and SATA • Fibre Channel • FireWire Networking • Ethernet & GiE • Audio-Video Bridging • 802.11 and Bluetooth • 5G • Spacewire • CAN-FD • TTEthernet • FlexRay • TSN & IEEE802.1Q FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic template • Interface traffic generator Software • GEM5 • Software code integration • Instruction trace • Statistical software model • Task graph Interfaces • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge RTL-like • Clock, Wire-Delay • Registers, Latches • Flip-flop • ALU and FSM • Mux, DeMux • Lookup table
- 28. COMPARE PERFORMANCE-POWER OF ARM CORTEX VS RISC-V FOR AI APPLICATIONS. Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com