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Stupid PCIe Tricks 
Joe FitzPatrick 
44Con 2014
whoami 
● Electrical Engineering education with 
focus on CS and Infosec 
● 8 years doing security research, speed 
debug, and tool development for CPUs 
● Hardware Pen Testing of CPUs 
● Security training for functional validators 
worldwide 
● Software Exploitation via Hardware 
Exploits, AKA SExViaHEx 
Joe FitzPatrick 
@securelyfitz 
joefitz@securinghardware.com
If Joe Fitz... 
Joe Sitz
Disclaimer 
This is not academic-caliber research. 
Lots of this stuff has been done before. 
The difference is that I aim to show that PCIe attacks can 
be easy and cheap
What is PCIe?
PCIe is PCI!
PCIe is NOT PCI! 
Foto tomada por Jorge González http://es.wikipedia.org 
Photo by snikerdo http://en.wikipedia.org
Links and Lanes 
Diagram: PCIe 2.1 specification
Hierarchy 
Diagram: PCIe 2.1 specification
Switching and Routing 
Diagram: PCIe 2.1 specification
Layers 
Diagram: PCIe 2.1 specification
Configuration Space 
Diagram: PCIe 2.1 specification
Configuration Space 
Diagram: PCIe 2.1 specification
Configuration Space 
Diagram: PCIe 2.1 specification
Configuration Space 
Diagram: PCIe 2.1 specification
Configuration Space 
Diagram: PCIe 2.1 specification
Enumeration 
Diagram: PCIe 2.1 specification
Routing PCIe
The Step-By-Step, Complicated, 
Mandatory, Inflexible Rules of 
Routing PCIe:
The Step-By-Step, Complicated, 
Mandatory, Inflexible Rules of 
Routing PCIe: 
1. route pairs adjacent and equal length
The Step-By-Step, Complicated, 
Mandatory, Inflexible Rules of 
Routing PCIe: 
1. route pairs adjacent and equal length 
… that’s mostly it
Routing PCIe 
System Board Traces 12 Inches 
Add-in Card Traces 3.5 inches 
Chip-to-Chip Routes 15 inches 
Follow these rules and your board might work. 
Break them and it might not.
Routing PCIe 
Minimum PCIe: 
● 2.5GHz TX 
● 2.5GHz RX 
● 100MHz Clock (optional)
Routing PCIe 
Cross-section of a USB 3.0 cable. Image courtesy of USB Implementers Forum
A brief history of DMA attacks
Tribble
Firewire Attacks
Thunderbolt
Thunderbolt
USB3380 Firmware
USB3380 Firmware 
> xxd SLOTSCREAMER.bin 
0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........
USB3380 Firmware 
> xxd SLOTSCREAMER.bin 
0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........
USB3380 Firmware 
> xxd SLOTSCREAMER.bin 
0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........ 
That’s all!
nsaplayset.org
Hardware 
http://www.hwtools.net/PLX.html
Software 
tools used in 
preparing this 
presentation: 
● plx’s flashing 
software 
● pyusb + scripts 
● inception_pci 
● volatility for 
memory analysis
Attack-side Software 
Quick ‘n’ dirty 
PCIe memory 
read/write with 
PyUSB
More attack-side Software
More attack-side Software 
# EQUALS: 
# 
# |-- Offset 0x00 
# / 
# / |-patchoffset--------------->[b0 01] 
# 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f .. (byte offset) 
# ----------------------------------------------- 
# c6 0f 85 a0 b8 00 00 b8 ab 05 03 ff ef 01 00 00 .. (chunk of memory data) 
# ----------------------------------------------- 
# ______/ ___/ ______/ 
#    
#   |-- Chunk 2 at internaloffset 0x05 
#  |-- Some data (ignore, don't match this) 
# |-- Chunk 1 at internaloffset 0x00 
# _____________________/ 
#  
# |-- Entire signature 
#
More attack-side Software 
{'OS': 'Mac OS X 10.9', 
'versions': ['10.9'], 
'architectures': ['x64'], 
'name': 'DirectoryService/OpenDirectory unlock/privilege escalation', 
'notes': 'Overwrites the DoShadowHashAuth/ODRecordVerifyPassword return value. 
'signatures': [{'offsets': [0x1e5], # 10.9 
'chunks': [{'chunk': 0x4488e84883c4685b415c415d415e415f5d, 
'internaloffset': 0x00, 
'patch': 0x90b001, # nop; mov al,1; 
'patchoffset': 0x00}]}]}]
Attacking via PCIe
MRd 
Find important values at known locations 
Take memory dumps for later analysis 
Example: 
Dump memory and use Volatility to analyze it
DMA Stool Analysis with Volatility 
dmesg log of the attack recovered from the 
memory dump of the victim
DMA Stool Analysis with Volatility 
names, pids, and uids 
for dumped processes
DMA Stool Analysis with Volatility 
extracted machine 
info 
the perfect amount of 
memory to dump!
MWr 
Modify values at known locations 
Manipulate code!!! 
Example: Use Inception to modify lock screen 
checking, or drop a metasploit payload!
Inception with Metasploit (W7sp1 POC only)
IORd/IOWr 
Only for legacy devices 
(legacy means not thoroughly tested recently)
CfgRd/CfgWr 
Interact with other PCI devices’ config spaces 
Yet another separate address space/different 
means of accessing hardware
Msg/MsgD 
Messages send things like interrupts and 
vendor-defined configuration 
Many message types are very rarely used 
Example: Johanna Rutkowska SNB VT-D stuff
Mitigations
Bus Master Enable 
joefitz@linUX31a:~/Documents/pcie/SLOTSCREAMER/inception_pci$ lspci -vv | grep BusMaster 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Access Control Services
IOMMU
Mitigating the Mitigations
VID:PID 
● Identifies device to the OS 
● OS chooses which driver to load 
● OS configures ACS, BME, etc… 
● OS loads driver
Default Drivers 
● Some drivers are ‘class’ drivers (think USB 
MSC, etc...) 
● Some device specific drivers might be 
installed by default (OSX) 
● Drivers contain bugs 
● Think facedancer for PCIE or Thunderbolt
Early Boot 
● IOMMU is not configured yet 
● Neither is much else 
● Wishlist: Volatility support for EFI shell
Option ROM/EFI drivers 
● Some devices have firmware that gets run at 
early boot 
● Some systems block this (but usually for 
anti-competitive reasons, not security) 
●
Breaking the rules 
● Spoof requesterID for posted transactions 
● Well-timed spoofed requesterID for non-posted 
transactions 
● Setting the ‘translated request’ bit
Misconfigurations 
● Everything is MMIO now - memory 
protections are essential 
● Memory protections are not enough - need 
Cfg and IO protections as well - don’t forget 
about them 
● Does installing a hypervisor change how 
your OS uses its IOMMU?
Putting it all together 
because 0.01% is too much
Thunderbolt 
Diagram: Apple Thunderbolt Device Driver Programming Guide
HALIBUTDUGOUT
Sorry, Previous Track 2 Speakers 
ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
Building ALLOYVIPER
MITMing
⇐ Thanks for the slides, snare & rzn
⇐ Thanks for the slides, snare & rzn
Bypassing VT-d on Macbooks? 
● VT-d is off at boot/reboot 
● Broadcom Ethernet drivers crash the system 
● System reboots - all the doors are open for a 
few moments 
No POC yet (I’ll GTFO soon…)
Can we do it without imitating a 
device? 
● Some PCIe switches have ‘transparent’ 
mode 
● Some PCIe switches have TLP injection 
debug features 
● Can we build one into a genuine device? 
● Can we build one into a cable? 
No POC yet here either
Potential enhancements 
● 64-bit DMA (>4gb access!) 
● Full control over TLP Header 
○ spoofing requester ID 
○ testing ‘reserved’ bits 
Enough unproven concepts… time to GTFO...
Joe FitzPatrick 
@securelyfitz 
Questions? 
joefitz@securinghardware.com 
http://www.securinghardware.com

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44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick

  • 1. Stupid PCIe Tricks Joe FitzPatrick 44Con 2014
  • 2. whoami ● Electrical Engineering education with focus on CS and Infosec ● 8 years doing security research, speed debug, and tool development for CPUs ● Hardware Pen Testing of CPUs ● Security training for functional validators worldwide ● Software Exploitation via Hardware Exploits, AKA SExViaHEx Joe FitzPatrick @securelyfitz joefitz@securinghardware.com
  • 3. If Joe Fitz... Joe Sitz
  • 4. Disclaimer This is not academic-caliber research. Lots of this stuff has been done before. The difference is that I aim to show that PCIe attacks can be easy and cheap
  • 7. PCIe is NOT PCI! Foto tomada por Jorge González http://es.wikipedia.org Photo by snikerdo http://en.wikipedia.org
  • 8. Links and Lanes Diagram: PCIe 2.1 specification
  • 9. Hierarchy Diagram: PCIe 2.1 specification
  • 10. Switching and Routing Diagram: PCIe 2.1 specification
  • 11. Layers Diagram: PCIe 2.1 specification
  • 12. Configuration Space Diagram: PCIe 2.1 specification
  • 13. Configuration Space Diagram: PCIe 2.1 specification
  • 14. Configuration Space Diagram: PCIe 2.1 specification
  • 15. Configuration Space Diagram: PCIe 2.1 specification
  • 16. Configuration Space Diagram: PCIe 2.1 specification
  • 17. Enumeration Diagram: PCIe 2.1 specification
  • 19. The Step-By-Step, Complicated, Mandatory, Inflexible Rules of Routing PCIe:
  • 20. The Step-By-Step, Complicated, Mandatory, Inflexible Rules of Routing PCIe: 1. route pairs adjacent and equal length
  • 21. The Step-By-Step, Complicated, Mandatory, Inflexible Rules of Routing PCIe: 1. route pairs adjacent and equal length … that’s mostly it
  • 22. Routing PCIe System Board Traces 12 Inches Add-in Card Traces 3.5 inches Chip-to-Chip Routes 15 inches Follow these rules and your board might work. Break them and it might not.
  • 23. Routing PCIe Minimum PCIe: ● 2.5GHz TX ● 2.5GHz RX ● 100MHz Clock (optional)
  • 24. Routing PCIe Cross-section of a USB 3.0 cable. Image courtesy of USB Implementers Forum
  • 25.
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  • 32.
  • 33.
  • 34. A brief history of DMA attacks
  • 37.
  • 38.
  • 39.
  • 43. USB3380 Firmware > xxd SLOTSCREAMER.bin 0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........
  • 44. USB3380 Firmware > xxd SLOTSCREAMER.bin 0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........
  • 45. USB3380 Firmware > xxd SLOTSCREAMER.bin 0000000: 5a00 0c00 2310 4970 0000 0000 e414 bc16 Z...#.Ip........ That’s all!
  • 48. Software tools used in preparing this presentation: ● plx’s flashing software ● pyusb + scripts ● inception_pci ● volatility for memory analysis
  • 49. Attack-side Software Quick ‘n’ dirty PCIe memory read/write with PyUSB
  • 51. More attack-side Software # EQUALS: # # |-- Offset 0x00 # / # / |-patchoffset--------------->[b0 01] # 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f .. (byte offset) # ----------------------------------------------- # c6 0f 85 a0 b8 00 00 b8 ab 05 03 ff ef 01 00 00 .. (chunk of memory data) # ----------------------------------------------- # ______/ ___/ ______/ # # |-- Chunk 2 at internaloffset 0x05 # |-- Some data (ignore, don't match this) # |-- Chunk 1 at internaloffset 0x00 # _____________________/ # # |-- Entire signature #
  • 52. More attack-side Software {'OS': 'Mac OS X 10.9', 'versions': ['10.9'], 'architectures': ['x64'], 'name': 'DirectoryService/OpenDirectory unlock/privilege escalation', 'notes': 'Overwrites the DoShadowHashAuth/ODRecordVerifyPassword return value. 'signatures': [{'offsets': [0x1e5], # 10.9 'chunks': [{'chunk': 0x4488e84883c4685b415c415d415e415f5d, 'internaloffset': 0x00, 'patch': 0x90b001, # nop; mov al,1; 'patchoffset': 0x00}]}]}]
  • 54.
  • 55. MRd Find important values at known locations Take memory dumps for later analysis Example: Dump memory and use Volatility to analyze it
  • 56. DMA Stool Analysis with Volatility dmesg log of the attack recovered from the memory dump of the victim
  • 57. DMA Stool Analysis with Volatility names, pids, and uids for dumped processes
  • 58. DMA Stool Analysis with Volatility extracted machine info the perfect amount of memory to dump!
  • 59. MWr Modify values at known locations Manipulate code!!! Example: Use Inception to modify lock screen checking, or drop a metasploit payload!
  • 60. Inception with Metasploit (W7sp1 POC only)
  • 61. IORd/IOWr Only for legacy devices (legacy means not thoroughly tested recently)
  • 62. CfgRd/CfgWr Interact with other PCI devices’ config spaces Yet another separate address space/different means of accessing hardware
  • 63. Msg/MsgD Messages send things like interrupts and vendor-defined configuration Many message types are very rarely used Example: Johanna Rutkowska SNB VT-D stuff
  • 65. Bus Master Enable joefitz@linUX31a:~/Documents/pcie/SLOTSCREAMER/inception_pci$ lspci -vv | grep BusMaster Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
  • 67. IOMMU
  • 69. VID:PID ● Identifies device to the OS ● OS chooses which driver to load ● OS configures ACS, BME, etc… ● OS loads driver
  • 70. Default Drivers ● Some drivers are ‘class’ drivers (think USB MSC, etc...) ● Some device specific drivers might be installed by default (OSX) ● Drivers contain bugs ● Think facedancer for PCIE or Thunderbolt
  • 71. Early Boot ● IOMMU is not configured yet ● Neither is much else ● Wishlist: Volatility support for EFI shell
  • 72. Option ROM/EFI drivers ● Some devices have firmware that gets run at early boot ● Some systems block this (but usually for anti-competitive reasons, not security) ●
  • 73. Breaking the rules ● Spoof requesterID for posted transactions ● Well-timed spoofed requesterID for non-posted transactions ● Setting the ‘translated request’ bit
  • 74. Misconfigurations ● Everything is MMIO now - memory protections are essential ● Memory protections are not enough - need Cfg and IO protections as well - don’t forget about them ● Does installing a hypervisor change how your OS uses its IOMMU?
  • 75. Putting it all together because 0.01% is too much
  • 76. Thunderbolt Diagram: Apple Thunderbolt Device Driver Programming Guide
  • 78. Sorry, Previous Track 2 Speakers ALLOYVIPER
  • 88. ⇐ Thanks for the slides, snare & rzn
  • 89. ⇐ Thanks for the slides, snare & rzn
  • 90. Bypassing VT-d on Macbooks? ● VT-d is off at boot/reboot ● Broadcom Ethernet drivers crash the system ● System reboots - all the doors are open for a few moments No POC yet (I’ll GTFO soon…)
  • 91. Can we do it without imitating a device? ● Some PCIe switches have ‘transparent’ mode ● Some PCIe switches have TLP injection debug features ● Can we build one into a genuine device? ● Can we build one into a cable? No POC yet here either
  • 92. Potential enhancements ● 64-bit DMA (>4gb access!) ● Full control over TLP Header ○ spoofing requester ID ○ testing ‘reserved’ bits Enough unproven concepts… time to GTFO...
  • 93. Joe FitzPatrick @securelyfitz Questions? joefitz@securinghardware.com http://www.securinghardware.com