A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Soft Switched Multi-Output Flyback Converter with Voltage DoublerIJPEDS-IAES
A novel multi-output voltage doubler circuit with resonant switching
technique is proposed in this paper. The resonant topology in the primary
side of the flyback transformer switches the device either at zero voltage or
current thus optimizing the switching devices by mitigating the losses. The
voltage doubler circuit introduced in the load side increases the voltage by
twice the value thereby increasing the load power and density. The proposed
Multi-output Isolated Converter removes the need for mutiple SMPS units
for a particular application. This reduces the size and weight of the
converters considerably leading to a greater payload. This paper aims at
optimizing the proposed converter with some design changes. The results
obtained from the hardware prototype are given in a comprehensive manner
for a 3.5W converter operating at output voltages of 5V and 3.3V at 50 kHz
switching frequency. The converter output is regulated with the PI controller
designed with SG3523 IC. The effects of load and line regulation for ±20%
variations are analyzed in detail.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Soft Switched Multi-Output Flyback Converter with Voltage DoublerIJPEDS-IAES
A novel multi-output voltage doubler circuit with resonant switching
technique is proposed in this paper. The resonant topology in the primary
side of the flyback transformer switches the device either at zero voltage or
current thus optimizing the switching devices by mitigating the losses. The
voltage doubler circuit introduced in the load side increases the voltage by
twice the value thereby increasing the load power and density. The proposed
Multi-output Isolated Converter removes the need for mutiple SMPS units
for a particular application. This reduces the size and weight of the
converters considerably leading to a greater payload. This paper aims at
optimizing the proposed converter with some design changes. The results
obtained from the hardware prototype are given in a comprehensive manner
for a 3.5W converter operating at output voltages of 5V and 3.3V at 50 kHz
switching frequency. The converter output is regulated with the PI controller
designed with SG3523 IC. The effects of load and line regulation for ±20%
variations are analyzed in detail.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Sinusoidal PWM has been a very popular technique used in AC motor control. This is a method that employs a triangular carrier wave modulated by a sine wave and the points of intersection determining the switching points of the power devices in the inverter.
The DC motor is operated by a 555 integrated circuit. The IC 555 in this circuit is being operated in astable mode, which produces a continuous HIGH and LOW pulses. In this mode, the 555 IC can be used as a pulse width modulator with a few small adjustments to the circuit.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Analysis and Improved Operation of PEBB Based 5-Level Voltage Source Convert...IJMER
The paper presents the power-electronic devices are increasing in several applications, and
power-electronic building blocks (PEBBs) are a strategic concept to increase the reliability of the
power-electronic converters and to minimize their cost. Magnetic elements, such as zigzag
transformers, phase-shifted transformers (PST), or zero-sequence blocking transformers (ZSBT), are
used to interconnect the PEBBs. In this paper, by using 5-level voltage source converter the operation
of multi-pulse converters will be analyzed, describing the harmonic cancellation and minimization
techniques that could be used in these multi-pulse converters, focusing on the power-electronics flexible
ac transmission systems devices installed at the NYPA Marcy substation. In order to improve the
dynamic response of this system, the use of selective harmonic elimination modulation is proposed and
implemented
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Sinusoidal PWM has been a very popular technique used in AC motor control. This is a method that employs a triangular carrier wave modulated by a sine wave and the points of intersection determining the switching points of the power devices in the inverter.
The DC motor is operated by a 555 integrated circuit. The IC 555 in this circuit is being operated in astable mode, which produces a continuous HIGH and LOW pulses. In this mode, the 555 IC can be used as a pulse width modulator with a few small adjustments to the circuit.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Analysis and Improved Operation of PEBB Based 5-Level Voltage Source Convert...IJMER
The paper presents the power-electronic devices are increasing in several applications, and
power-electronic building blocks (PEBBs) are a strategic concept to increase the reliability of the
power-electronic converters and to minimize their cost. Magnetic elements, such as zigzag
transformers, phase-shifted transformers (PST), or zero-sequence blocking transformers (ZSBT), are
used to interconnect the PEBBs. In this paper, by using 5-level voltage source converter the operation
of multi-pulse converters will be analyzed, describing the harmonic cancellation and minimization
techniques that could be used in these multi-pulse converters, focusing on the power-electronics flexible
ac transmission systems devices installed at the NYPA Marcy substation. In order to improve the
dynamic response of this system, the use of selective harmonic elimination modulation is proposed and
implemented
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI CircuitsVLSICS Design
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is
robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often
found in critical paths of various large scale high performance circuits. Yet, due to high switching activity
they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we
propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and
Domino logic styles. For a given circuit, we extract the unate and binate components using a unate
decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,
area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate
blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our
approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and
22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS
logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
SMART MULTICROSSBAR ROUTER DESIGN IN NOCVLSICS Design
This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
The Gate diffusion input (GDI) is a novel technique
for low power digital circuit design. This techniq
ue
reduces the power dissipation, propagation delay, a
rea of digital circuits and it maintains low comple
xity
of logic design. In this paper, the 4×1 Multiplexer
, 8×3 Encoder, BCD Counter and Mealy State Machine
were implemented by using Pass Transistors (PT), Tr
ansmission Gate (TG) and Gate Diffusion Input (GDI)
technique and then they were compared with each oth
er for power dissipation. The Multiplexers and
Encoders are combinational circuits and Counters an
d mealy machines are sequential circuits both of th
em
are very important digital systems so power optimiz
ation should be done to those digital circuits. The
whole processes for development of digital circuits
and simulation was done by using the mentor graphi
cs
backend tool. This method can also be extended to t
he processors and other high level designs for
optimization of power dissipation, area and delay i
n order to increase the circuit efficiency.
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
This paper describes about different types of voltage followers. Each follower has its own advantages and limitations. The voltage follower can be characterized with current mirror source current or it can be used as a ideal current source. Voltage Follower is one of the most important analog circuits required in many analog integrated circuits. Input impedance of op amp is very high, giving effective isolation of the output from the signal source.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
This is to certify that the research entitled ((Performance of sustainable Mortar using Calcined clay, fly ash, Limestone powder and reinforced with hybrid fiber)) have been conducted at our Technical Engineering College and there is No funding resource for this research from our University.
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
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DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
DOI : 10.5121/vlsic.2013.4309 91
DESIGN OF A PROGRAMMABLE LOW POWER LOW
DROP-OUT REGULATOR
Jayanthi Vanama and G.L.Sampoorna
Trainee Engineer, Powerwave Technologies Pvt. Ltd., R&D India
jayanthi.vanama@pwav.com
Intern, CONEXANT Systems Pvt. Ltd.
sampoorna.gonella@gmail.com
ABSTRACT
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 ˚C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 µW.
KEYWORDS
Low Drop-Out, Voltage Regulator, Low Power, Low quiescent current.
1. INTRODUCTION
With the advent of low power battery-operated circuits, demanding special emphasis on
compactness and portability, it has become imperative to optimize existing low drop-out regulator
structures for greater all-round performance. Low drop-out regulators are circuits designed to
provide a specified, stable DC voltage, with a low input-to-output voltage difference. The drop-
out voltage of a regulator is defined as that value of differential voltage at which regulation
provided by the control loop stops. Typically, an LDO is characterized by performance metrics
such as drop-out voltage, line regulation, load regulation, power supply rejection ratio, tolerance
over temperature, ESR(equivalent series resistance) range, output capacitance, variation in
voltage due to transient current set up and quiescent and maximum load currents.[1] LDOs today
have become ubiquitous as mobile battery operated products ranging from cellular phones to
laptops require them. Today's LDO's must meet demands of low operating voltages and low
quiescent currents as a consequence of the higher packing densities that process technology
demands.
Perhaps the biggest challenge incumbent on the engineer with regards to design lies in the trade-
off between loop gain, a necessary parameter to accomplish optimal load and line regulation, and
bringing the dominant pole (which in this case, is the pole at the output node) below the unity
gain frequency to achieve a desirable phase margin that satisfies the stability condition. For pole-
zero cancellation to occur at low frequencies, an output capacitor with high ESR(equivalent series
resistance) must be used, which poses the danger of degraded transient response Also, leakage
currents significantly increase when operating voltages are substantially increased, and rise in
temperatures have a hindering effect on loop gain due to thermal leakages. Minimization of drop-
out voltages is essential for maximizing dynamic range within a given power supply voltage,
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
92
owing to the fact that signal to noise ratio decreases with decrease in power supply voltages as
noise is typically a constant phenomenon.
To combat these effects, an LDO design has been proposed that utilises a pole-zero cancellation
scheme for compensation, and a cascode current amplifier together with a large, high threshold
PMOS operated in the sub-threshold region, which is responsible for boosting the gain and
yielding the desired output voltage. The LDO is programmable and offers a range of four
different voltages, by means of the two binary-input control signals at its input. The entire circuit
has been designed in a 65 nm process and simulated using Cadence Tool.
2. ANALYSIS OF CONVENTIONAL LDO
Low-drop out regulators are one of the most conventional applications of operational amplifiers.
Figure1 shows the basic topology. A voltage reference is used with the op-amp to generate a
regulated voltage, Vreg . If the voltage reference is stable with temperature, the fact that the Vreg
is a function of a ratio of resistors (so process or temperature changes in the resistance value don’t
affect the ratio) and the variation in the op-amp’s open loop gain is desensitized using feedback
makes the regulated voltage stable with process and temperature changes. The ideal (meaning that
the op-amp has infinite open-loop gain) regulated voltage is [2]
Figure 1: Conventional Low Drop-Out Regulator
ܸ݃݁ݎ = ܸ݂݁ݎ . ቀ1 +
ோଵ
ோଶ
ቁ (1)
If the op-amp’s open-loop gain is finite, then we can write [2]
ܸ݃݁ݎ = .1ܣ (ݒ − )݉ݒ (2)
and
݉ݒ = ܸ.݃݁ݎ
ܴ2
ܴ1 + ܴ2
ܽ݊݀ ݒ = ܸ݂݁ݎ (3)
Solving for the actual regulated voltage, gives
ܸ݃݁ݎ = ܸ.݂݁ݎ
1
1
1ܣ
+
ܴ2
ܴ1 + ܴ2
(4)
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
93
which implies that the equation simplifies to equation 1 for very large values of Ao1.
The drop out voltage of a regulator depends on the switch ON resistance (Ron) and is given by
the formula [1]
ܸ ݀ݎ − ݐݑ = ܫ ݈݀ܽ × ܴ ݊ (5)
Typical drop-out voltages range from a minimum of 100mV to as high as a volt. This variation in
the output voltage with change in input voltage is termed as line regulation. Load regulation is
defined as variation in the output voltage due to the presence of a load. It is expressed as [1]
ܴ =
∆ܸ݃݁ݎ
∆ݐݑܫ
=
ܴ − ݏݏܽ
1 + ߚݒܣ
(6)
where Ro is the output impedance of the circuit, ∆Vreg and ∆Iout are the changes in regulated
output voltage and the load current respectively. Ro-pass is the output resistance of the pass
transistor. Av is the open-loop gain of the system and β is the feedback factor. As can be seen
from this equation, a high-open loop gain and low output impedance are influential factors in
determining the transient response of an LDO. In addition, a high (W/L) ratio of the pass element,
which results in a low output resistance, is required.
The temperature dependence of the output voltage is a function of the input offset voltage of the
error amplifier and the drift in the voltage reference with changes in temperature. Accuracy of the
system, may hence be defined as [1]
ݕܿܽݎݑܿܿܣ =
ܸ, ݉ܽݔ − ܸ, ݉݅݊
ܸ
(7)
where Vo is the input offset voltage of the error amplifier. Offset voltage of the error amplifier
can be minimized by increasing the open-loop gain of the system, which translates to a higher
transconductance of the differential pair.
The efficiency of an LDO is limited by the quiescent current in the system, and may be expressed
as [1],
ݕ݂݂ܿ݊݁݅ܿ݅ܧ =
݃݁ݎܸݐݑܫ
(ݐݑܫ + ܸ݊݅)ݐ݊݁ܿݏ݅ݑݍܫ
(8)
where Vin is the input voltage.
The open loop gain of the system is given by the equation [1]
ܸ݂ܾ
ܸ݂݁ݎ
= ||ݒܣ =
݃݉ܽ × ܴܽ × ݃݉ × ܼ
1 + ݎܽܥܴܽݏ
.
ܴ1
ܴ1 + ܴ2
(9)
where gma and gmp are the transconductances of the amplifier and the pass element respectively,
Roa is the output resistance of the amplifier, Cpar is the parasitic capacitance due to the pass
element and Z is the output impedance seen when looking into the output node, Vfb is the
feedback voltage to the error amplifier.
3. PROPOSED REGULATOR ARCHITECTURE
In the conventional architecture of an LDO, it is assumed that the error amplifier, by virtue of its
large gain and resistive feedback, desensitizes variations in the gain so that a stable regulated
voltage output is obtained. In our architecture, a current-sourcing PMOS in the output stage has
been introduced. It is required that the PMOS be pulled all the way to ground so as to be biased
further into saturation region. For this reason, the existing topology is modified and a Common-
Source Stage is added, with the amplifying device being large enough so as to be a strong pull-
down device. The Common-Source stage is responsible for enhancing signal swing and boosting
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
94
Rz
Cc
R1
R2
inp
n
inn Rout
Cout
Idc
AVDD33
ctrl1 ctrl2
Common
source
amplifier
Error amplifier
Current-
sourcing
PMOS
Figure 2: Schematic of proposed regulator
the gain at the op-amp output, subsequently pulling the gate of the large PMOS low enough to
increase its gate-to-source voltage.
Programmability has been added to the LDO by means of two external control signals which
appear at the gate inputs of two NMOS transistors. The binary input that appears at the gate is
responsible for bringing in that resistance into the circuit, by biasing the transistor in saturation or
triode region, thereby controlling the output voltage.
Table 1: Range of Output Voltages
The proposed architecture consists of the following stages:
1. Error Amplifier
2. Common Source Amplifier
3. Current-sourcing PMOS
3.1. Error Amplifier
A high gain operational amplifier is used as the error amplifier [5], with a stable voltage reference
fed to one of its inputs. The voltage reference is usually derived from a bandgap reference circuit.
The differential pair of the operational amplifier consists of a current mirror NMOS load and a
PMOS tail current source, with the gate-drain connected load being driven by a 2.5 uA ideal
current source. A current mirror load has the advantage of providing high output impedance, and
consequently, high gain. An operational amplifier connected with this sort of load is termed an
open-transconductance amplifier, where all nodes are low impedance nodes with the exception of
Binary Input Output Voltage
00 1.025
01 1
10 0.975
11 0.95
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
95
the differential pair[2]. The resistive feedback provided to the negative input of the error
amplifier works in a way as to balance the amplifier, minimizing op-amp offset.
3.2. Common-Source Amplifier
In general, a source follower is used as the buffer stage in most LDO’s. The gain of a
source follower is given by the formula [2],
ܸݐݑ
ܸ݅݊
=
݁ܿ݊ܽݐݏ݅ݏ݁ݎ ܿ݀݁ݐܿ݁݊݊ ݐ ݐℎ݁ ݁ܿݎݑݏ
݁ܿ݊ܽݐݏ݅ݏ݁ݎ ܿ݀݁ݐܿ݁݊݊ ݐ ݐℎ݁ ݁ܿݎݑݏ + ݁ܿ݊ܽݐݏ݅ݏ݁ݎ ݈݃݊݅݇ ݅݊ݐ ݐℎ݁ ݁ܿݎݑݏ
(10)
i.e,
ܸݐݑ
ܸ݅݊
=
݃݉1
݃݉2
(11)
where gm1 and gm2 are the transconductances of the amplifying device and load,
respectively.
which implies that the source follower has asymmetric current driving capability, and gain less
than one. Hence a common-source amplifier is used, which has a small signal gain equal to
ݒܣ = ݃݉(1ݎ ||2ݎ) (12)
where gm is the transconductance of the amplifying device, ro1 and ro2 are the output resistances of
the load and the amplifying device.
The equation implies that when the amplifying device (in our case, the NMOS) is made large
enough, the gain at the second stage is improved. Proper sizing of the NMOS also ensures that it
acts as a strong pull down, yielding rail-to-rail swing.
3.3. Current-Sourcing PMOS
The sizing of the current-sourcing PMOS is the most vital part of the entire design. PFETs are
known to have poor current driving capability, as a result of which a large-size PMOS is required.
In our design, a PMOS with high voltage threshold (of upto 540 mV in slow corner) has been
used. The question arises as to why a lower voltage threshold PMOS was not chosen, which
might have provided the advantage of lesser area. Low-voltage threshold FETs are known to
contribute to leakage currents, increasing power dissipation in the device. The PMOS is
responsible for quick charging and discharging of the output node, thereby increasing slew rate to
obtain faster settling times.
4. COMPENSATION METHOD
The load is driven by an external capacitor, which is made large enough so that it can quickly
charge the load during fast transients. However, the size of the capacitor is limited by the
following constraints: the charging capability, the slew rate and the phase margin. Unlike most
architectures where the dominant pole lies at the first node, here the dominant pole occurs at the
output node as a result of which the external capacitor must be used as the compensation
capacitor. Hence there is a lower limit on the size of the capacitor. However, for effective
charging of the output node a large capacitor is necessary, but not too large that the output
response becomes sluggish and the load transient is very slow. A large capacitor can also lead to
poor load regulation.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
96
The three poles can be characterized by the equations below[6]:
1 =
ଵ
௫௧ோ௦
(13),
2 =
ଵ
ଵோଵ
(14)
3 =
ଵ
ଶோଶ
(15).
where p1 is the pole at the output stage, p2 is the pole at the second gain stage and p3 is the pole
at the first gain stage. The compensation is achieved by means of a pole-zero frequency
cancellation scheme [3], where a zero resistor is introduced at the output of the second gain stage.
The value of the capacitance must be chosen so that the pole formed at the second gain stage lies
well beyond the unity-gain bandwidth of the regulator. The capacitance also serves the purpose of
fast recovery in large-signal conditions. When the regulated voltage output drops suddenly, the
decrease in voltage is fed back directly to the gate of the PMOS. This causes the PMOS to turn on
quicker, enabling it to pull up the output node. However, this capacitance might pose the
disadvantage of pushing the pole associated with the output node to a higher frequency, if not
properly sized, leading to instability.
5. SIMULATION RESULTS
Simulations have been carried out using the Cadence tool. The LDO yields a typical (nominal
corner, 65˚C) gain of 31 dB and a worst case (slow corner, 125 ˚C) gain of 27 dB, with a phase
margin of 72˚.
Figure 3: Gain-frequency curve of the regulator at -40˚, 65˚ and 125˚C.
Gain in the slow corner (lightly doped NMOS and PMOS) is lower due to the higher threshold
voltages in this corner, because of the lower conductivities the doping levels introduce.
Subsequently, the gate-to-source voltage at the input of the pass element might not be sufficiently
higher than the threshold voltage, and the pass element is at risk of entering the sub-threshold
region. As a result, the pass element behaves as a linear element, with a higher drain-to-source
drop, reducing the output voltage, and hence, the gain.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
97
Figure 4: Phase response of the regulator at -40˚, 65˚ and 125˚C.
Figure 5: Power supply rejection curve in nominal corner at 65˚C.
A high DC Power Supply Rejection Ratio may be achieved through high open-loop gain. The AC
PSRR (at 100 MHz) may go as low as -3 dB in worst cases.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
98
Figure 6: Power supply rejection curve in slow corner at 125 ˚C
Figure 7:Worst case transient response measured at -10% power supply fluctuation.
The figure above depicts the worst case (slow corner, 125 ˚C) transient response of the LDO at a
power supply of 1.08 V (10% fluctuation). As can be seen, the output voltage drops to 880mV. A
line transient of 33 mV (measured between the output voltages obtained at 1.26(+10%), -40 ˚C
and 1.08(-10%), 125 ˚C has been obtained.
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
99
Figure 8: Line regulation measurement across process corners.
The maximum line ripple is 11mV. This value has been measured in the no-load to full-load
setting.
Figure 9: Load regulation measured across process corners.
The minimum and maximum load ripples are 11mV and 28mV respectively. This has been
measured in the full-load to no-load setting.
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
100
Figure 10: Equivalent Output Noise
6. CONCLUSIONS
We have designed a low power low drop-out regulator that is capable of delivering four different
output voltages, based on the control signals it receives. The design yields a 30 dB gain, but a
gain of upto 50 dB may be achieved by further increase in transconductance of the differential
pair. The design is disadvantaged from an input offset point of view, as the input offset error is
upto 10 mV. Also, a folded cascade topology with resistive biasing can generate greater gain,
reducing the number of stages and making phase margin of the system easier to accomplish at
lower values of external capacitance.
The regulator sinks a maximum quiescent current of 0.5 mA, hence the low power dissipation of
a hundred microwatts. The circuit is capable of furnishing upto 0.88 volts when power supply is
at 90% of the desired value, thereby accounting for power fluctuations. Also, the regulator has
been shown to be stable over a wide range of temperatures, ie -40 ˚C to 125 ˚C, and across
process corners.
Presently, the external capacitor used is quite large (10 µF), but capacitorless architectures[4]
have been proposed and form a significant part of current CMOS LDO design literature. The
current design, hence has scope of improvement in this direction, which may be the subject of our
future research.
REFERENCES
[1] “Study and Design of Low Drop-Out Regulators” by Gabriel Alfonso Rincon-Mora and Philip E.
Allen, Department of Electrical and Computer Engineering, Georgia Institute of Technology.
[2] “CMOS Circuit Design, Layout and Simulation” by R. Jacob Baker, IEEE Press Series on
Microelectronic Systems, Stuart K.Tewksbury and Joe E. Brewer, Series Editors.
[3] “A CMOS Capacitorless Low Drop-Out Voltage Regulator” by Vincent Lixiang Bu, Department of
Electrical and Computer Engineering, Tufts University.
[4] “Full On-Chip CMOS Low DropVoltage Regulator” by Robert J. Milliken, Jose Silva-Martínez,
Senior Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE.
[5] “An Improved CMOS Error Amplifier Design for LDO Regulators in Communication Applications”
by Xinquan Lai, Institute of Electronic CAD and Donglai Xu, School of Science and Technology.
[6] “Design of Analog CMOS Integrated Circuits” by Behzad Razavi.