This document summarizes a research paper that proposes a new low power dual-edge triggered static D flip-flop (DETFF) design. The proposed DETFF architecture uses two latches connected in parallel to sample data on both the rising and falling clock edges. Simulation results show the proposed DETFF has lower power dissipation (improved by 36-48%), lower power-delay product (improved by 24-42%), and smaller layout area (improved by 63-73%) compared to other conventional DETFF designs. Therefore, the proposed DETFF is well-suited for low power and small area applications.