BuckPFC

Fairchild Semiconductor Power Seminar 2013-2014 1
Current Shaping Strategies for Buck Power Factor
Correction (PFC)
Steve Mappus and Hangseok Choi
Abstract - Two possible control techniques, where the input
current is indirectly shaped by shaping the inductor current, are
proposed for a buck PFC converter. A thorough analysis on the
harmonic content of the AC line current is presented for each control
technique to examine the allowable voltage gain (K value) for
meeting EN61000-3-2, Class C, and Class D. Results of the harmonic
analysis are used to derive the required value of K and the VOUT
necessary to meet Class-C and Class-D requirements from a given
AC line voltage. The goal of designing a buck PFC for highest
efficiency, while passing EN61000-3-2, Class D is verified with a
300 W dual interleaved Boundary Conduction Mode (BCM) buck
PFC converter.
I. INTRODUCTION
For universal input applications that require power
factor correction (PFC) to meet input current harmonic
regulations, such as EN61000-3-2; maintaining high
efficiency over the entire load and line range is a major
design challenge. This is because the widely used PFC
boost topology typically exhibits 1%–3% lower
efficiency at low-line compared to that of high-line. The
large switch current at low-line not only causes severe
conduction losses, but also brings about higher switching
loss combined with high output voltage. The high output
voltage of a boost converter, which is typically in the
380-400 V range, also has an unfavorable effect on the
switching losses and electro-magnetic interference (EMI)
of the downstream DC-DC converter. These drawbacks
of the boost PFC pre-regulator can be overcome by
using a buck converter for the PFC. When the output
voltage is properly selected (80~100 V for universal
line), the buck PFC allows high efficiency across the
entire load range, while reducing the switching losses
and EMI of the downstream DC-DC converter. Since
any voltage lower than the peak of the AC line voltage
can be selected for VOUT, the buck PFC can be a
favorable choice as a non-isolated, single-stage PFC. A
single-stage PFC directly supplies the load, bypassing
the need for a downstream DC-DC converter, which
allows a simpler, lower-cost solution. Another merit of
the buck PFC is that it does not experience excessive
inrush current during startup, which can eliminate the
inrush current limit circuit of the boost PFC.
Buck PFC converter operation was first described in
an IEEE paper[5]
. Detailed comparative analyses between
the buck PFC and its boost counterpart have shown that
the buck PFC not only features higher efficiency at low-
line, but also exhibits lower common-mode (CM)
EMI[3],[6]
with proper selection of the output voltage.
Detailed analysis and improvement on control methods
have been proposed to maximize efficiency, while
complying with harmonic current limits[3]-[6]
. Because
average-mode current shaping is difficult due to the
pulsating input current, a clamped current buck PFC was
proposed[3],[4]
to simplify the control of a Continuous
Conduction Mode (CCM) buck PFC. This approach is
suitable for cost-sensitive applications barely meeting
the less-stringent EN61000-3-2 Class-D specification.
Boundary Conduction Mode (BCM) operation of the
buck PFC and its analysis were presented[5],[6]
,
simplifying the control and improving efficiency by
eliminating reverse-recovery loss of the freewheeling
diode. However, no thorough analysis of the harmonic
contents of the line current was presented to meet
various harmonic regulations.
This paper presents two input current-shaping methods
that can be used both for CCM and BCM operation. The
proposed methods control the input current indirectly by
shaping the inductor current, simplifying the control
circuit. The line current harmonics for each control
method are analyzed to investigate the allowable voltage
conversion ratio to meet EN61000-3-2 Class-C and
Class-D. The proposed control method is verified with a
300 W interleaved BCM buck PFC prototype.
II. BUCK CONVERTER OVERVIEW
Fig. 1 shows a simplified schematic of the buck PFC
converter and current flow commutation as the switch, Q,
is turned on and off. When Q is turned on, diode D is
turned off and current flows from input to output
through the inductor. During this time, the inductor is
energized if the instantaneous line voltage is larger than

the output voltage. When the switch is turned off; the
rectifier stage, including the diode, inductor, and output
capacitor; is isolated from the input side. Then, the
inductor current freewheels through the diode, D as the
inductor current ramps down.
The net inductor voltage, VL, averaged over a
switching period, tS, must be zero. For the converter
shown in Fig. 1, operating in BCM or CCM, the inductor
volt-second balance equation is written as:
〈𝑉𝐿〉 𝑇 𝑆
= [(𝑉𝐼𝑁(𝑡) − 𝑉𝑂𝑈𝑇) × 𝑡 𝑂𝑁] − 𝑉𝑂𝑈𝑇 × 𝑡 𝑂𝐹𝐹 = 0 (1)
𝑉𝐼𝑁(𝑡) × 𝑡 𝑂𝑁 = 𝑉𝑂𝑈𝑇 × (𝑡 𝑂𝑁 + 𝑡 𝑂𝐹𝐹)
𝑉𝐼𝑁(𝑡) × 𝑡 𝑂𝑁 = 𝑉𝑂𝑈𝑇 × 𝑡 𝑆
The duty cycle, D, is defined as:
𝐷 =
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁(𝑡)
=
𝑡 𝑂𝑁
𝑇𝑆
(2)
When the instantaneous line voltage, VIN(t), is lower
than the output voltage, VOUT; the bypass capacitor
voltage is maintained at VOUT through the body-diode of
Q, regardless of the switching state of Q. The bridge
rectifier diodes are reverse biased and no current is
supplied from the AC line until VIN(t) is above VOUT.
Since the input is a time-varying rectified AC voltage,
there are instantaneous periods during each half-line
cycle where the buck converter is unable to process
power. As shown in Fig. 2, VAC<VOUT for 0<θ<θz and π-
θz<θ<π. The phase during this time is referred to as the
dead angle. Conversely, the phase during θz<θ<π-θz is
the time that power processing occurs and is referred to
as the conduction angle.
The conversion ratio K, between the DC output
voltage and peak line voltage is defined as:
𝐾 =
𝑉𝑂𝑈𝑇
√2 × 𝑉𝐼𝑁(𝑅𝑀𝑆)
(3)
A higher K value results in a lower conduction angle;
which leads to lower PF, higher THD, and higher
efficiency. Conversely, a lower K value results in a
higher conduction angle; leading to higher PF, lower
THD, and lower efficiency. The choice of VOUT, relative
to VAC, plays a critical role in determining converter
efficiency as well as the conduction angle necessary for
meeting EN61000-3-2 Class-C and Class-D
requirements. VOUT as a function of K value for
115 VRMS and 230 VRMS, as well as conduction angle
verses K value, are shown in Fig. 3. The conduction
angle is given by:
𝜃 𝐶(%) =
2
𝜋
× [cos−1
(𝐾)] (4)
VOUT
VAC
VIN(t)
D
VOUT
VAC
VIN(t)
D
IL
(a)
(b)
Q
L
VL
L
VL
Q COUTCBYP
COUTCBYP
Fig. 1. (a) tON=QON, DOFF (b) tOFF=QOFF, DON
| VAC |
VOUT
θz0 π- θz π
IAC
VAC
θ
t
Fig. 2. Buck PFC input voltage and current waveforms
0
40
80
120
160
200
240
280
320
360
400
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VOUT(V)
ConductionAngle(%)
K (VOUT/√2×VRMS)
K Value
CondAngle
115VRMS
230VRMS
Fig. 3. Conduction angle and VOUT vs. K value

III. SINE-SQUARED MODULATION,
INDUCTOR CURRENT SHAPING
METHOD
Since the buck converter has discontinuous, pulsating,
input current; control of a CCM buck PFC converter is
more challenging compared to its boost counterpart.
Shaping the input current has a detrimental effect on the
performance of the current control loop due to the
relatively large delay in the averaging circuit. The
proposed sine-squared method simplifies the input
current control by shaping the inductor current, which is
continuous. Controlling the inductor current indirectly
shapes the input current, eliminating the complicated
averaging circuit and error amplifier for input current
shaping. Fig. 4 shows the basic concept of the proposed
control method. It is assumed that the output voltage is
very small compared to the AC line voltage, such that
the dead angle is negligible. When the power factor is
unity, the power delivered from the AC line is given as:
𝑃𝐴𝐶(𝑡) = 𝑉𝐴𝐶 𝑠𝑖𝑛(𝜔𝑡) × 𝐼𝐴𝐶 𝑠𝑖𝑛(𝜔𝑡)
= 𝑉𝐴𝐶 × 𝐼𝐴𝐶 × 𝑠𝑖𝑛(𝜔𝑡)2
(5)
Where VAC and IAC are the peak amplitudes of the line
voltage and line current, respectively.
Assuming the output capacitor voltage has negligible
voltage ripple, the power delivered to the output stage,
which includes the output capacitor, is obtained as:
𝑃𝑂𝐶𝐴𝑃(𝑡) = 𝑖 𝐿
𝐴𝑉𝐺
(𝑡) × 𝑉𝑂𝑈𝑇 (6)
Excluding the output capacitor, there is no large
energy storage component in a buck converter.
Therefore, the power delivered from the AC line should
be the same as the power delivered to the output stage,
including the output capacitor. Then, the average
inductor current for unity power factor should be
proportional to the sine square, calculated as:
𝑖 𝐿
𝐴𝑉𝐺
(𝑡) =
𝑉𝐴𝐶 × 𝐼𝐴𝐶
𝑉𝑂𝑈𝑇
𝑠𝑖𝑛(𝜔𝑡)2
(7)
This implies that input current can be indirectly shaped
by shaping the average inductor current as a sine-squared
waveform, referred to here as sine-squared modulation.
IAC
EMI filter
VAC
VOUT
IL
AVG
VAC
IAC
PAC
VOUT
IL
AVG
PO.CAP
Fig. 4. Proposed control method for CCM buck PFC converter
Although the basic concept of the sine-squared
modulation method is derived by assuming that the
output voltage is extremely low and the dead angle is
negligible, the output of most applications tends to be
high enough that the dead angle is not negligible.
Therefore, a more realistic analysis should be given,
covering practical cases for higher values of VOUT.
Fig 5. shows the control circuit implementation of
sine-squared modulation and Fig. 6 its key waveforms.
To control the average inductor current without an
averaging circuit, an on-time doubler is used such that
the switch current, IDS, at half of its conduction time, is
equal to the current reference signal, VIREF.
VOUTQ L
IL
VAC
S
R
Q
Q
+
-
VREF
VEA
VIN
tON
doulbler
IDS
+
-
OSC
VIREF
VGS
Q
RCSIDS
VIREF
RCS
RCSIDS
2
( )IN OUT
OUT
V V
V

Fig. 5. CCM implementation using sine-squared modulation control

IAC
VIN VOUT
IL
θz π-θz π
(VIN-VOUT)2
VOUT
2
Fig. 6. Sine-squared modulation key waveforms
Assuming that the converter operates in CCM, the
average inductor current that is locally averaged over the
corresponding switching period is obtained as:
𝑖 𝐿
𝐴𝑉𝐺
(𝜃) =
𝑉𝐸𝐴
𝑅 𝐶𝑆
×
1
𝐾2
× [sin(𝜃) − 𝐾]2
,
𝑓𝑜𝑟: 𝜃 𝑍 < 𝜃 < 𝜋 − 𝜃 𝑍
=0, otherwise
(8)
𝑤ℎ𝑒𝑟𝑒 𝜃 𝑍 = 𝑠𝑖𝑛−1
(
𝑉 𝑂𝑈𝑇
𝑉 𝐴𝐶
)
𝑎𝑛𝑑 𝐾 =
𝑉𝑂𝑈𝑇
√2 × 𝑉𝐼𝑁(𝑅𝑀𝑆)
=
𝑉𝑂𝑈𝑇
𝑉𝐴𝐶
The AC line current is obtained by multiplying the
average inductor current by duty cycle, calculated as:
𝐼𝐴𝐶(𝜃) = 𝑖 𝐿
𝐴𝑉𝐺
(𝜃) × 𝐷(𝜃)
= 𝑖 𝐿
𝐴𝑉𝐺
(𝜃) ×
𝑉𝑂𝑈𝑇
𝑉𝐴𝐶 × sin(𝜃)
=
𝑉𝐸𝐴 × [sin(𝜃) − 𝐾]2
𝑅 𝐶𝑆 × 𝐾 × sin(𝜃)
,
=0, otherwise
(9)
The line current, which is the locally averaged
MOSFET current, is plotted in Fig. 7 for different K
values. As K increases, the dead angle increases, while
the line current changes from a sine shape to a sine shape
with increasing crossover distortion.
To examine the impact of K on harmonic distortion,
the harmonic current amplitude of the nth
order is
calculated as:
𝐼 𝐻(𝑛) =
2
𝜋
∫ [
𝐼𝐿𝐼𝑁𝐸 × (sin(𝜃) − 𝐾)2
sin(𝜃)
sin(𝑛𝜃)] 𝑑𝜃
𝜋−𝜃 𝑍
𝜃 𝑍
(10)
𝑤ℎ𝑒𝑟𝑒 𝐼𝐿𝑖𝑛𝑒 =
𝑉𝐸𝐴
𝐾 × 𝑅 𝐶𝑆
The amplitude of harmonic current of the nth
order as
a percentage of the amplitude of the fundamental current
is given as:
𝐼 𝐻(𝑛)
𝐼 𝐻(1)
=
(
∫ [
(sin(𝜃) − 𝐾)2
sin(𝜃)
𝜋−𝜃 𝑍
𝜃 𝑍
∫ (sin(𝜃) − 𝐾)2 𝑑𝜃
𝜋−𝜃 𝑍
𝜃 𝑍
) × 100%
(11)
The even harmonics are all zero and the odd
harmonics are calculated using a spreadsheet and plotted
as a percentage of the fundamental current in Fig. 8 and
Fig. 9, together with the EN61000-3-2 Class-C and
Class-D limits. As can be seen, all the harmonics are
below the EN61000-3-2 Class-C and Class-D limits
except for the third harmonic. To make the third
harmonic meet the Class-C and Class-D limits, the K
values should be less than 0.33 and 0.42, respectively,
which is illustrated in Fig. 10.
Even though the K values required to meet the
harmonic limits are low, resulting in an unfavorable
effect on the efficiency, this limitation can be offset
when applying this method to a single-stage PFC. For
example, this can be a cost-effective solution for non-
isolated, light emitting diode (LED) applications. For
nominal low-line voltage (115 VRMS), the allowable LED
string voltage can be as high as 53 V, meeting Class C.
For Class-D applications, such as television and
personal computing equipment, hold-up time of one line
cycle (16 ms) is typically required. The amount of
required hold-up capacitance is proportional to VOUT
2
(refer to Eq. (22)), but the low K value required to meet
Class D forces a low VOUT value. Even though capacitors
with a lower voltage rating can be used, the total
required capacitor volume makes the single-stage PFC
approach impractical for most Class-D applications.

Since the K value is closely related to efficiency, another
modulation method that allows a higher K value and
higher VOUT should be considered. In the next section,
sine modulation is presented to maximize K value, while
meeting Class D.
0
0.2
0.4
0.6
0.8
1
1.2
/ 2
K=0.1
K=0.2
K=0.3
K=0.4
K=0.5
Fig. 7. Input current waveform with different voltage gain K for sine-
squared modulation method
5th
harmonics
7th
9th
Class C limit for 7th
(7%)
(5%)
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
0 0.1 0.2 0.3 0.4 0.5
K
Class C limit for 3rd
(30%)
3rd
harmonics
Class D limit for 3rd
(39.1%)
(10%)
Fig. 8. Harmonic contents (3rd, 5th, 7th, 9th, 11th) as a function of
voltage gain K for sine-squared modulation method
13th15th
17th
19th
21st
0.0%
0.5%
1.0%
1.5%
2.0%
2.5%
3.0%
0 0.1 0.2 0.3 0.4 0.5
K
, 13th
, 15th
, 17th
, 19th
, 21st
(3%)
11th
Class D limit for 17th
(2.6%)
(2.3%)
Class D limit for 21st
(2.1%)
Fig. 9. Harmonic contents (11th, 13th, 15th, 17th, 19th and 21st) as a
function of voltage gain K for sine-squared modulation method
0
40
80
120
160
200
240
280
320
360
400
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 0.2 0.4 0.6 0.8 1
VOUT(V)
ConductionAngle(%)
K (VOUT/√2×VRMS)
K Value, Sine2 Modulation
CLASS C
0.33 0.59
CLASS D
0.42
230VRMS
115VRMS
Cond
Angle
Fig. 10. Sine-squared modulation – K value limits for EN61000-3-2
Class C and Class D
IV. SINE MODULATION, INDUCTOR
CURRENT-SHAPING METHOD
For sine-squared modulation, the third harmonic
increases monotonically with the K value, as can be seen
in Fig. 8. This results in a small K value to meet the
harmonic limits. To extend the allowable K value, a
modified control strategy can be considered, as shown in
Fig. 11. The control circuit of Fig. 11 is similar to sine-
squared modulation. However, the sine modulation
control method is derived from sine-squared modulation
by removing the VIN-VOUT squaring function in Fig. 5.
An on-time doubler is used such that the switch current
at half of its conduction time is equal to the current
reference signal, VIREF. Assuming the converter operates

in CCM, the average inductor current locally averaged
over the corresponding switching period is obtained as:
𝑖 𝐿
𝐴𝑉𝐺
(𝜃) =
𝑉𝐸𝐴
𝑅 𝐶𝑆
×
1
𝐾
× [sin(𝜃) − 𝐾],
=0, otherwise.
(12)
𝑤ℎ𝑒𝑟𝑒 𝜃 𝑍 = 𝑠𝑖𝑛−1
(
𝑉𝑂𝑈𝑇
𝑉𝐴𝐶
)
Whereas, the AC line current is obtained by
multiplying the average inductor current by the duty
cycle, calculated as:
𝐼𝐴𝐶(𝜃) = 𝑖 𝐿
𝐴𝑉𝐺(𝜃) × 𝐷(𝜃)
= 𝑖 𝐿
𝐴𝑉𝐺(𝜃) ×
𝑉𝑂𝑈𝑇
𝑉𝐴𝐶 × sin(𝜃)
=
𝑉𝐸𝐴 × [𝑠𝑖𝑛(𝜃) − 𝐾]
𝑅 𝐶𝑆 × sin(𝜃)
,
=0, otherwise.
(13)
Fig. 13 illustrates how the AC line current is distorted
as K increases. As K increases, the dead angle increases
while the line current changes from a “U” shape to
crossover distorted sine shape.
To examine the impact of K on harmonic distortion,
the harmonic current amplitude of the nth
order is
calculated as:
𝐼 𝐻(𝑛) =
2
𝜋
∫ [
𝐼𝐿𝐼𝑁𝐸 × 𝐾(sin(𝜃) − 𝐾)
sin(𝜃)
𝜋−𝜃 𝑍
𝜃 𝑍
(14)
The amplitude of harmonic current of the nth
order as a
percentage of the amplitude of the fundamental current
is given as:
𝐼 𝐻(𝑛)
𝐼 𝐻(1)
= (
∫ [
sin(𝜃) − 𝐾
sin(𝜃)
𝜋−𝜃 𝑍
𝜃 𝑍
∫ [sin(𝜃) − 𝐾]𝑑𝜃
𝜋−𝜃 𝑍
𝜃 𝑍
) × 100% (15)
The even harmonics are all zero and the odd
harmonics are calculated using a spreadsheet and plotted
as a percentage of the fundamental current in Fig. 14-Fig.
17. The range of K using sine modulation to meet Class
C is 0.09~0.12 because the fifth harmonic exceeds the
limit when K is smaller than 0.09, as shown in Fig. 14.
The 13th harmonic exceeds the limit when K is larger
than 0.12, as shown in Fig. 16. The K range to meet the
Class-C limit is extremely narrow compared to the sine-
squared modulation method where the K range to meet
Class C is 0~0.33. Therefore, it is practically impossible
to use sine modulation for meeting Class C requirements.
However, the K range of the sine modulation method
to meet Class D is 0.22~0.59, since the third harmonic
becomes zero when K is around 0.3. The resulting K
values for Class D can be larger than that of the sine-
squared modulation method where the K range to meet
Class D is 0~0.42. Thus, sine modulation allows higher
output voltage settings for Class-D applications, which
potentially improves efficiency. The allowed K values
for meeting Class-C and -D limits using sine modulation
are summarized in Fig. 18.
VOUTQ L
IL
VAC
S
R
Q
Q
+
-
VREF
VEA
VIN
TON
doulbler
IDS
+
-
OSC
VIREF
RCS
RCSIDS
IN OUT
OUT
V V
V

VGS
Q
RCSIDS
VIREF
Fig. 11. CCM implementation using sine modulation control
IAC
VIN VOUT
IL
VIN-VOUT
θz π-θz π
VOUT
Fig. 12. Key waveforms using sine modulation

Fig. 13. Input current waveform with different voltage gain, K, for sine
modulation
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
0 0.1 0.2 0.3 0.4 0.5 0.6
K
Class C limit for 3rd
(30%)
3rd
harmonics
Class D limit for 3rd
(39.1%)
(10%)
(21.9%)
5th
harmonics
Fig. 14. Harmonic contents (3rd, 5th) as a function of voltage gain, K,
with sine modulation
0%
2%
4%
6%
8%
10%
12%
14%
0 0.1 0.2 0.3 0.4 0.5 0.6
K
(11.5%)
7th
harmonics
9th
harmonics
(5.8%)
(7%)
(5%)
Fig. 15. Harmonic contents (7th, 9th) as a function of voltage gain, K,
11th
harmonics
13th
harmonics
Class C limit
For 11th
, 13th
(3%)
Class D limit
For 13th
(3.4%)
Class D limit
For 11th
(4%)
Fig. 16. Harmonic contents (11th, 13th) as a function of voltage gain, K,
Class C limit
For 15th
, 17th
, 19th
, 21th
(3%)
Class D limit
For 15th
(3%)
Class D limit For 17th
(2.6%)
(2.3%)
(2.1%)
Fig. 17. Harmonic contents (15th, 17th, 19th, 21st) as a function of
voltage gain, K, with sine modulation
0
40
80
120
160
200
240
280
320
360
400
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 0.2 0.4 0.6 0.8 1
VOUT(V)
ConductionAngle(%)
K (VOUT/√2×VRMS)
K Value, Sine Modulation
CLASS D
0.22 0.590.09 0.12
CLASS C
230VRMS
115VRMS
Cond
Angle
Fig. 18. Sine modulation – K value limits for EN61000-3-2 Class C and
Class D
0
0.2
0.4
0.6
0.8
1
1.2
/ 2
K=0.1
K=0.2
K=0.3
K=0.4
K=0.5
K=0.6

V. SINE-SQUARED AND SINE
MODULATION FOR BCM OPERATION
The two control methods proposed in the previous
sections can be also applied to BCM operation, as
illustrated in Fig. 19 and Fig. 20. Compared to CCM
operation, BCM offers better efficiency and lower EMI
since the reverse recovery of the freewheeling diode is
eliminated. BCM PFC control uses zero-current
switching (ZCS), zero-voltage switching (ZVS) during
low-line operation and valley switching during high-line
operation to maintain high efficiency over the entire line
and load range.
From a controller point of view, BCM can also
simplify the control circuit because current information
from the power stage is not required for input current
shaping. Sine modulation can be implemented with any
BCM PFC controller that uses a constant on-time,
variable-frequency control law. Unlike sine modulation,
sine-squared modulation requires additional circuitry to
modulate the on-time of the controller according to the
difference between the line voltage and output voltage,
which is therefore difficult to implement with existing
BCM PFC controllers.
When using any general-purpose BCM PFC controller
for sine modulation, the zero-current detection (ZCD)
circuit controls the MOSFET turn-on time during the
conduction angle, θz<θ<π-θz. However, during the dead
angle, the instantaneous input voltage is less than the
output voltage and, as a result, there is no ZCD signal
detected. When a ZCD signal is missing, a default ZCD
signal is generated at a fixed frequency determined by
the BCM controller, as illustrated in Fig. 20. If the
control bandwidth of the output voltage regulation is
much narrower than twice the line frequency, the on-
time can be kept almost constant during each line cycle,
resulting in proper line current shaping. Since the
MOSFET is turned on at zero current with a constant on-
time, the peak inductor current is proportional to the
difference between the instantaneous line voltage and
output voltage, given as:
𝑖 𝐿
𝐴𝑉𝐺(𝜃) =
𝑡 𝑂𝑁
2 × 𝐿
× 𝑉𝐼𝑁(𝑅𝑀𝑆) × [sin(𝜃) − 𝐾],
=0, otherwise.
(16)
The AC line current is obtained as:
𝐼𝐴𝐶(𝜃) =
𝑡 𝑂𝑁 × 𝑉𝑂𝑈𝑇 × [sin(𝜃) − 𝐾]
2 × 𝐿 × sin(𝜃)
,
=0, otherwise.
(17)
Similar to Eq. (14), the BCM current harmonics vary
with a given K and can be calculated as:
𝐼 𝐻(𝑛)
=
2
𝜋
∫ [
𝑡 𝑂𝑁 × 𝑉𝑂𝑈𝑇(sin(𝜃) − 𝐾)
2 × L × sin(𝜃)
𝜋−𝜃 𝑍
𝜃 𝑍
(18)
Although the efficiency benefits of the BCM PFC
control method are well documented, the high peak
inductor current is a barrier for its use at power levels
higher than about 150 W. This limitation is alleviated by
interleaving two BCM buck PFC power stages operating
180˚ out of phase. Interleaving reduces the peak current
amplitude through input ripple current cancellation,
which has a secondary effect of decreased EMI filter size
compared to a single-channel BCM buck operating at
similar power levels. The output current ripple is also
reduced, easing the RMS ripple current seen by the
output energy storage capacitors. The BCM control of
two variable-frequency buck PFC power stages is non-
trivial, but greatly simplified when using a dedicated
controller, such as the FAN9611.
VOUTQ L
IL
VAC
S
R
Q
Q
+
-
VREF
VEA
VIN
+
-
OSC
ZCD
IDS
VIN-VOUT
Fig. 19. BCM implementation using sine-squared modulation control

Turn-on determined by ZCD
VGS
No ZCD No ZCD
| VAC |
VOUT
VAC
t
t
IDS
θz0 π- θz π
IDS(AVG)
IDIAC
θ
Fig. 20. Key waveforms using sine-squared modulation
VOUTQ L
IL
VAC
S
R
Q
Q
+
-
VREF
VEA
VIN
+
-
OSC
ZCD
IDS
Fig. 21. BCM implementation using sine modulation control
Turn-on determined by ZCD
VGS
No ZCD No ZCD
| VAC |
VOUT
VAC
t
t
IDS
θz0 π- θz π
IDS(AVG)
IDIAC
θ
Fig. 22. Key waveforms using sine modulation
For a given K value and on-time, the output power is
calculated as:
𝑃𝑂𝑈𝑇 =
2
𝜋
∫ 𝑉𝑂𝑈𝑇 × 𝑖 𝐿
𝐴𝑉𝐺
(𝜃)𝑑𝜃
𝜋
2
𝜃 𝑍
=
𝑉𝑂𝑈𝑇 × 𝑇𝑂𝑁 × 𝑉𝐴𝐶
𝜋 × 𝐿
× [cos(𝜃𝑧) − 𝐾 (
𝜋
2
− 𝜃𝑧)]
(19)
The peak inductor current is obtained as:
𝐼𝐿(𝑃𝐾) =
𝑉𝐴𝐶 × sin(𝜃) − 𝑉𝑂𝑈𝑇
𝐿
× 𝑡 𝑂𝑁
=
𝜋 × (𝑉𝐴𝐶sin(𝜃) − 𝑉𝑂𝑈𝑇) × 𝑃𝑂𝑈𝑇
𝑉𝐴𝐶 × 𝑉𝑂𝑈𝑇 [cos(𝜃𝑧) − 𝐾 (
𝜋
2
− 𝜃𝑧)]
(20)
The switching frequency varies with the load condition
and instantaneous line voltage as:
𝑓𝑆𝑊 =
𝑉𝑂𝑈𝑇
2
× [cos(𝜃𝑧) − 𝐾(
𝜋
2
− 𝜃𝑧)]
𝜋 × 𝐿 × 𝑃𝑂𝑈𝑇 × sin(𝜃)
(21)
Since the minimum switching frequency occurs at the
peak of the line voltage (𝜃 = 𝜋/2), the inductor value
should be determined based on the maximum inductor
current and minimum switching frequency.
VI. BUCK PFC IMPLEMENTATION
The conventional buck converter shown in Fig. 23(a)
requires a floating high-side gate drive, whereas the
boost converter drives a low-side referenced MOSFET.
Developing a floating high-side gate drive for an offline
converter can be challenging and requires either a gate
drive transformer or a dedicated high-voltage gate driver.
However, as shown in Fig. 23(b), the output voltage can
be sensed directly because the PWM controller and
output share the same common ground reference. Since
VIN(t) and VOUT are indirectly connected through the
high-side MOSFET, Q, there is no inrush current issue.
As an option, the buck PFC converter can be inverted;
resulting in a low-side, ground-referenced MOSFET.
The inverted buck PFC converter is derived by
repositioning the MOSFET and inductor to the return leg,
as shown in Fig. 24(a).
The MOSFET shown in Fig. 24(b) can be driven
directly from the PWM, eliminating the need for a high-
side gate drive. However, VOUT is floating and therefore
not sharing the same ground reference as the PWM
controller. This means the output voltage must be sensed
differentially and level shifted to ground before being
fed back to the PWM controller.
For low-line operation, VOUT regulation is typically set
for less than 100 V, which has a detrimental effect on
hold-up time. For some applications, the power supply
output must remain in regulation for a specified time

after input power is removed. Power is stored in a bank
of capacitors connected to the output of the PFC
regulator. Hold-up time, thu, is proportional to the PFC
output capacitance, COUT and VOUT
2
, calculated as:
𝑡ℎ𝑢 =
𝐶 𝑂𝑈𝑇 × (𝑉𝑂𝑈𝑇
2
− 𝑉𝑂𝑈𝑇(𝑀𝐼𝑁)
2
)
2 × 𝑃𝑂𝑈𝑇
(22)
Eq. (22) is independent of any particular topology and
is therefore valid for the boost and buck converters. The
boost topology PFC output voltage is normally set to
380-400 V when operating from a universal AC input.
This high output voltage greatly reduces the required
amount of hold-up capacitance for a given power level.
Conversely, the buck topology PFC output voltage is
normally set to less than 100 V. A comparative 4:1
reduction in output voltage results in a 16x increase in
output capacitance for a given hold-up time requirement.
Even though lower voltage capacitors can be used, the
overall impact on total capacitor volume is not as
favorable for buck PFC converters.
In spite of this, there are power applications where the
buck PFC can prove beneficial. Adaptors, LED power
supplies, and battery chargers are a few examples where
hold-up requirements are minimal.
It is also worth mentioning that the buck PFC output
voltage ripple, at twice the line frequency, is larger than
that of its boost alterative. The large dead angle,
characteristic of the buck PFC, forces more current to be
drawn from the AC line during the conduction angle.
However, the high-frequency ripple current of the output
capacitor is much smaller compared to the boost
converter because the continuous inductor current
supplies the load current. Lower mean time between
failure (MTBF) and higher reliability of the output
capacitor can be expected with a buck PFC converter.
VOUTQ L
VAC
VIN(t)
(a)
VOUTQ L
VAC
VIN(t)
(b)
PWM
HS
Fig. 23. Conventional buck PFC converter
VOUT
Q L
VAC
VIN(t)
VOUT
Q
LVAC
VIN(t)
VSNS
PWM
(a)
(b)
Fig. 24. Inverted buck PFC converter

VII. 300 W, DUAL INTERLEAVED, BCM,
BUCK PFC, REFERENCE DESIGN
The sine modulation control technique can be
implemented using any BCM PFC controller that uses a
constant on-time control algorithm.
Due to the power losses and additional EMI filter
requirements associated with high peak inductor current,
BCM PFC converters are typically limited to about
200 W of output power. However, this power level can
be extended to greater than 500 W when two BCM
power stages are interleaved[7],[8]
.
Using the FAN9611 interleaved dual-BCM PFC
controller, a 300 W interleaved BCM buck PFC
converter was built and tested according to the
specifications listed in Table 1.
The primary design goals are:
 High efficiency, especially low-line
 Verify theoretical K value limits using sine
modulation
 Meet EN61000-3-2, Class D
TABLE 1. INTERLEAVED, DUAL, BCM, BUCK PFC, REFERENCE
DESIGN SPECIFICATIONS
Parameter Min. Typ. Max.
VAC 85 VRMS 265 VRMS
fVIN(AC_LINE) 50 Hz 60 Hz 65 Hz
VOUT 90 V
POUT_PFC 300 W
fSW_PFC 16 kHz 500 kHz
tSOFT_START 100 ms
tON_OVERSHOOT 10 V
η_PFC 0.97
The output voltage is regulated at 90 V for 85 VRMS <
VIN(RMS) < 265 VRMS. As VIN(RMS) varies, the K value
varies according to Eq. (2). Therefore, the sine
modulation, K, value limits summarized in Fig. 18 can
be verified by varying VIN(RMS) and measuring the
current harmonics.

Fig. 25. 300 W interleaved BCM buck PFC schematic

VIII. 300 W INTERLEAVED BCM BUCK
PFC PERFORMANCE
Fig. 26 and Fig. 27 show the effect of changing K
value on input line current. The “U-shaped” line current
introduced in Fig. 13 is verified by the measured data for
K=0.55 and K=0.28 when VIN(AC)=115VRMS and
230VRMS, respectively. As shown in Fig. 26, when
K=0.55, the line current appears more sinusoidal but
with increasing dead angle.
Fig. 26. CH1-VAC, CH2-IAC, CH3-IL2, CH4-IL1; VIN(AC)=115 VRMS,
POUT=300 W, VOUT=90 V, K=0.55
Increasing VIN(AC) to 230 VRMS decreases the K value
to K=0.28. Compared to Fig. 26, the dead angle
decreases, but the waveform is more “U-shaped,” as
indicated in Fig. 27.
Fig. 27. CH1-VAC, CH2-IAC, CH3-IL2, CH4-IL1; VIN(AC)=230 VRMS,
POUT=300 W, VOUT=90 V, K=0.28
The steady-state operation showing the two phases
perfectly synchronized 180˚ out of phase with respect to
each other is highlighted in Fig. 28.
Fig. 28. CH1-OUT1, CH2-OUT2, CH3-IL2, CH4-IL1; VIN(AC)=115 VRMS,
POUT=300 W, VOUT=90 V, K=0.55, f=42 kHz
During the dead angle, ZCD pulses are missing and
the FAN9611 operates according to the internal restart
timer frequency of 16 kHz, as shown in Fig. 29. Note the
high frequency of operation near the zero crossing, just
prior to restart timer mode.
Fig. 29. CH1-OUT1, CH2-OUT2, CH3-IL2, CH4-IL1; VIN(AC)=115 VRMS,
POUT=300 W, VOUT=90 V, K=0.55, f=16 kHz (Restart Timer Frequency)
Fig. 30 shows the discontinuous, drain-to-source
MOSFET current for each phase. The drain-to-source
current for the buck PFC converter is the pulsating input
current that is indirectly controlled by shaping the
inductor current.

Fig. 30. CH1-OUT1, CH2-OUT2, CH3-IDS1, CH4-IDS2; VIN(AC)=115 VRMS,
POUT=135 W, VOUT=90 V, K=0.55
Fig. 31 and Fig. 32 show the phase management
functionality of the FAN9611. Fig. 31 highlights single-
phase to two-phase operation occurring as the load is
suddenly increased above 48 W (16%). During this
transition, the switching frequency is doubled and the
inductor current (drain-source current shown) is halved
within a single switching cycle.
POUT≈48 W, VOUT=90 V, K=0.55, 1 phase to 2 phase
Conversely, Fig. 32 highlights two-phase to single-
phase operation occurring as the load is suddenly
decreased below 37 W (12%). During this transition, the
switching frequency is halved and the inductor current
(drain-to-source current shown) is doubled within a
single switching cycle.
POUT≈37 W, VOUT=90 V, K=0.55, 2 phase to 1 phase
As mentioned, one advantage of the buck PFC is the
inherent inrush current limitation. Fig. 33 shows the
typical AC line current during initial startup. The peak
inrush current is about 4 APK due to the input EMI filter
capacitors and bypass capacitor. Comparatively, the
inrush current for a boost converter can be as much as
10x this amount under similar startup conditions.
Fig. 33. CH1-VAC, CH2-IAC; VIN(AC)=115 VRMS, POUT=90 W, VOUT=90 V,
inrush startup current
The floating output voltage is a unique characteristic
of the inverted buck PFC regulator and is shown, along
with the output current during startup, in Fig. 34. The
output voltage rises monotonically in approximately
100 ms with less than 10 V overshoot.

Fig. 34. CH1-VOUT, CH2-ICOUT=IL1+IL2; VIN(AC)=115 VRMS, POUT=90 W,
VOUT=90 V, tRISE=100 ms, VOS=8 V
Another significant advantage of the buck PFC is the
high efficiency obtainable during low-line operation.
The efficiency verses load curve for VOUT=90 V is
shown in Fig. 35. For VIN(AC)=115 VRMS, K=0.55 with a
K value limit of 0.59 for passing EN61000-3-2 Class D.
The measured efficiency is >96% over the entire load
range. At 10%-20% load the efficiency of a PFC boost
converter tends to decrease 1%-3% compared to a buck
PFC. Within the load range of 10%-20%, the buck PFC
efficiency was measured at or slightly above 97%.
90%
95%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Efficiency(%)
Output Power (%)
Interleaved Buck PFC, Efficiency vs. Load
(90VOUT, 100%=300W)
115Vrms
230Vrms
Fig. 35. 300 W interleaved BCM buck PFC, efficiency vs. load
For VIN(AC)=230 VRMS, K=0.28 with a K value limit of
0.59 for passing EN61000-3-2 Class D. The decrease in
high-line efficiency is attributed to the K value being
less than half the limit value of 0.59 and confirms the
fact that the buck converter operates most efficiently at
higher duty cycle. This also implies that EN61000-3-2
Class D could be met under this condition and is verified
by the measured current harmonics shown in Fig. 42.
Fig. 36 shows a comparison between VOUT=80 V and
VOUT=90 V for 85VRMS < VIN(AC) < 265 VRMS at 300 W.
Efficiency increases as VOUT (K value) increases.
90%
95%
100%
85 105 125 145 165 185 205 225 245 265
Efficiency(%)
AC Line Voltage (VRMS)
Interleaved Buck PFC, Efficiency vs. AC Line
(90VOUT, 300W)
90Vout
80Vout
Fig. 36. 300 W interleaved BCM buck PFC, efficiency vs. AC line
As mentioned, higher THD and lower PF is a natural
consequence of the buck PFC. PF verses load is shown
in Fig. 37 for VIN(AC)=115 VRMS and VIN(AC)=230 VRMS.
For low-line operation, the PF is greater than 0.9 from
20%-100% load.
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
PF
Output Power (%)
Interleaved Buck PFC, PF vs. Load
(90VOUT, 100%=300W)
115Vrms
230Vrms
Fig. 37. 300 W interleaved BCM buck PFC, PF vs. load
Fig. 34-Fig. 37, highlight the effect that varying VOUT
(K value) has on PF and THD. As verified by Fig. 34,
PF increases as VOUT (K value) decreases due to the
increasing conduction angle.

0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
85 105 125 145 165 185 205 225 245 265
PF
Interleaved Buck PFC, PF vs. AC Line
(90VOUT, 300W)
90Vout
80Vout
Fig. 38. 300 W interleaved BCM buck PFC, PF vs. AC line
Similarly, THD also increases with increasing output
voltage (K value) due to smaller conduction angle. As
shown in Fig. 39 and Fig. 40, high THD is a natural
consequence of the buck PFC topology.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
THD
Output Power (300W=100%)
Interleaved Buck PFC, VIN=115VRMS
90VOUT
80VOUT
Fig. 39. 300 W interleaved BCM buck PFC, THD vs. load
Fig. 40 shows the THD discrepancy between
VOUT=80 V and VOUT=90 V converging at high-line.
During high-line, the K value is smaller and the
conduction angle is large, which has less impact on THD.
0%
10%
20%
30%
40%
50%
60%
70%
85 105 125 145 165 185 205 225 245 265
THD(%)
Interleaved Buck PFC, THD vs. AC Line
(90VOUT, 300W)
90Vout
80Vout
Fig. 40. 300 W interleaved BCM buck PFC, THD vs. AC line
Based on the sine modulation current harmonic
analysis method, a K value less than 0.59 was deemed
necessary for meeting EN61000-3-2 Class D. K<0.59
translates to VOUT<95 V for VIN(AC)=115 VRMS. The
measured harmonic data for the buck PFC with
VOUT=90 V is shown in Fig. 41. As can be seen, the
converter barely passes the Class-D limits, validating the
sine modulation current harmonic analysis method for
designing a buck PFC regulator.
0
0.2
0.4
0.6
0.8
1
1.2
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
HarmonicCurrent(A)
Harmonic Number
Interleaved Buck PFC
EN61000-3-2, Class D, 115VAC, 90VOUT, 300W, K=0.55
Measured Harmonic Current
Class D (Computing) Limit
Fig. 41. 300 W interleaved BCM buck PFC, input current harmonics,
115VAC, K=0.55
When VIN(AC) is increased to 230 VRMS, the K value
decreases to 0.28 for VOUT=90 V. Under theses operating
conditions, the buck PFC should more easily pass the
Class-D limits, verified by the harmonic data shown in
Fig. 42. The trade-off for easily passing Class D is seen
as lower efficiency, confirmed by the 230 VRMS
efficiency curve shown in Fig. 35.
0
0.2
0.4
0.6
0.8
1
1.2
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
HarmonicCurrent(A)
Harmonic Number
Interleaved Buck PFC
EN61000-3-2, Class D, 230VAC, 90VOUT, 300W, K=0.28
MeasuredHarmonic Current
Class D (Computing) Limit
Fig. 42. 300 W interleaved BCM buck PFC, input current harmonics,
230 VAC, K=0.28

IX. CONCLUSION
The sine-squared and sine-modulation control methods
were proposed as possible solutions for a buck PFC
regulator. A thorough harmonic analysis was completed
for each case. The results of the harmonic analysis
impose strict limits on the allowable voltage conversion
ratio, defined as K value, necessary for meeting
EN61000-3-2 Class C and Class D. Both control
techniques can be implemented using many
commercially available BCM PFC controllers typically
used in the power range up to about 150 W. A 300 W,
90 VOUT, interleaved BCM buck PFC regulator was
designed based on the FAN9611 control IC. The design
was used to verify the K value and VOUT limitations
necessary to pass EN610000-3-2 Class D. From the
current harmonic analysis for sine squared and sine
modulation, a summary of K values and VOUT limitations
for meeting EN61000-3-2 Class C and Class D is shown
in Table 2. The results shown in Table 2 conclude that
the BCM buck PFC regulator, using sine modulation,
can be a viable PFC solution for meeting Class D when
the input voltage is limited to either low-line or high-line
only. However, hold-up requirements verses VOUT (K
value) must be carefully weighed. Sine-squared
modulation can be considered for some low-cost, low-
VOUT applications mostly favoring EN61000-3-2 Class C,
such as LED lighting.
TABLE 2. DESIGN LIMITS FOR MEETING EN61000-3-2 CLASS C & D
Sine-Squared Modulation
Parameter EN61000-3-2
VIN
(VRMS)
K VOUT (V) Efficiency Class C Class D
85
<0.33 <39 MEDIUM YES NO
<0.42 <50 MEDIUM YES YES
115
230
265
Sine Modulation
Parameter EN61000-3-2
VIN
(VRMS)
K VOUT (V) Efficiency Class C Class D
85 >0.22 <0.59 >27 <70 HIGH NO YES
115 >0.22 <0.59 >36 <95 HIGH NO YES
230 >0.22 <0.59 >72 <191 HIGH NO YES
265 >0.22 <0.59 >83 <221 HIGH NO YES
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Steve Mappus is a principal Systems Engineer working
in Fairchild Semiconductor’s Power Conversion group
located in Bedford, NH, USA. In his current role, he is
responsible for new product development of power-
supply control and MOSFET gate drive ICs. He has more
than 22 years of power supply design experience,
including ten years designing military and commercial
power systems for avionic applications. He has spent the last twelve years
working within the field of power-management semiconductors, specializing
in systems and applications engineering. His areas of interest include high-
power converter topologies, soft-switching converters, synchronous
rectification, high-frequency power conversion, and power factor correction.
Hangseok Choi received B.S., M.S., and Ph.D degrees in
electrical engineering from Seoul National University.
From 2002 to 2007, he was a system and application
engineer at Fairchild Semiconductor Korea. Since 2008,
he has been a principal system and application engineer at
Fairchild Semiconductor in Bedford, NH, USA, where he
is developing high-performance power management ICs.
He has authored or coauthored more than 50 technical papers and holds 27
U.S. patents. He has conducted Fairchild power seminars since 2007. His
research interests include analysis, simulation, and design of high-frequency,
high-power-density power converters.

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